| blob | 36cb78241b01f5eb7a6f176389b8a874f3ce8610 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -march=amdgcn -mcpu=gfx1013 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX1013 %s
3 ; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX1030 %s
4 ; RUN: not --crash llc -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERR %s
5 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11 %s
7 ; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(uint node_ptr, float ray_extent, float3 ray_origin, float3 ray_dir, float3 ray_inv_dir, uint4 texture_descr)
8 ; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(uint node_ptr, float ray_extent, float3 ray_origin, half3 ray_dir, half3 ray_inv_dir, uint4 texture_descr)
9 ; uint4 llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(ulong node_ptr, float ray_extent, float3 ray_origin, float3 ray_dir, float3 ray_inv_dir, uint4 texture_descr)
10 ; uint4 llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(ulong node_ptr, float ray_extent, float3 ray_origin, half3 ray_dir, half3 ray_inv_dir, uint4 texture_descr)
12 declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32, float, <3 x float>, <3 x float>, <3 x float>, <4 x i32>)
13 declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32, float, <3 x float>, <3 x half>, <3 x half>, <4 x i32>)
14 declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64, float, <3 x float>, <3 x float>, <3 x float>, <4 x i32>)
15 declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64, float, <3 x float>, <3 x half>, <3 x half>, <4 x i32>)
17 ; ERR: in function image_bvh_intersect_ray{{.*}}intrinsic not supported on subtarget
18 ; Arguments are flattened to represent the actual VGPR_A layout, so we have no
19 ; extra moves in the generated kernel.
20 define amdgpu_ps <4 x float> @image_bvh_intersect_ray(i32 %node_ptr, float %ray_extent, float %ray_origin_x, float %ray_origin_y, float %ray_origin_z, float %ray_dir_x, float %ray_dir_y, float %ray_dir_z, float %ray_inv_dir_x, float %ray_inv_dir_y, float %ray_inv_dir_z, <4 x i32> inreg %tdescr) {
21 ; GCN-LABEL: image_bvh_intersect_ray:
22 ; GCN: ; %bb.0: ; %main_body
23 ; GCN-NEXT: image_bvh_intersect_ray v[0:3], v[0:15], s[0:3]
24 ; GCN-NEXT: s_waitcnt vmcnt(0)
25 ; GCN-NEXT: ; return to shader part epilog
26 main_body:
27 %ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0
28 %ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1
29 %ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2
30 %ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0
31 %ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1
32 %ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2
33 %ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0
34 %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
35 %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
36 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
37 %r = bitcast <4 x i32> %v to <4 x float>
38 ret <4 x float> %r
39 }
41 define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 inreg %node_ptr, float inreg %ray_extent, <3 x float> inreg %ray_origin, <3 x half> inreg %ray_dir, <3 x half> inreg %ray_inv_dir, <4 x i32> inreg %tdescr) {
42 ; GFX10-LABEL: image_bvh_intersect_ray_a16:
43 ; GFX10: ; %bb.0: ; %main_body
44 ; GFX10-NEXT: s_mov_b32 s15, s12
45 ; GFX10-NEXT: s_mov_b32 s12, s9
46 ; GFX10-NEXT: s_lshr_b32 s9, s7, 16
47 ; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s7
48 ; GFX10-NEXT: s_pack_ll_b32_b16 s7, s9, s8
49 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
50 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
51 ; GFX10-NEXT: v_mov_b32_e32 v2, s2
52 ; GFX10-NEXT: v_mov_b32_e32 v3, s3
53 ; GFX10-NEXT: v_mov_b32_e32 v4, s4
54 ; GFX10-NEXT: v_mov_b32_e32 v5, s5
55 ; GFX10-NEXT: v_mov_b32_e32 v6, s6
56 ; GFX10-NEXT: v_mov_b32_e32 v7, s7
57 ; GFX10-NEXT: s_mov_b32 s14, s11
58 ; GFX10-NEXT: s_mov_b32 s13, s10
59 ; GFX10-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[12:15] a16
60 ; GFX10-NEXT: s_waitcnt vmcnt(0)
61 ; GFX10-NEXT: ; return to shader part epilog
62 ;
63 ; GFX11-LABEL: image_bvh_intersect_ray_a16:
64 ; GFX11: ; %bb.0: ; %main_body
65 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
66 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
67 ; GFX11-NEXT: s_lshr_b32 s2, s7, 16
68 ; GFX11-NEXT: s_lshr_b32 s3, s5, 16
69 ; GFX11-NEXT: v_mov_b32_e32 v2, s4
70 ; GFX11-NEXT: s_pack_ll_b32_b16 s2, s3, s2
71 ; GFX11-NEXT: s_pack_ll_b32_b16 s3, s5, s7
72 ; GFX11-NEXT: s_pack_ll_b32_b16 s4, s6, s8
73 ; GFX11-NEXT: v_mov_b32_e32 v3, s3
74 ; GFX11-NEXT: v_mov_b32_e32 v4, s2
75 ; GFX11-NEXT: v_mov_b32_e32 v5, s4
76 ; GFX11-NEXT: v_mov_b32_e32 v6, s0
77 ; GFX11-NEXT: v_mov_b32_e32 v7, s1
78 ; GFX11-NEXT: s_mov_b32 s15, s12
79 ; GFX11-NEXT: s_mov_b32 s14, s11
80 ; GFX11-NEXT: s_mov_b32 s13, s10
81 ; GFX11-NEXT: s_mov_b32 s12, s9
82 ; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[12:15] a16
83 ; GFX11-NEXT: s_waitcnt vmcnt(0)
84 ; GFX11-NEXT: ; return to shader part epilog
85 main_body:
86 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
87 %r = bitcast <4 x i32> %v to <4 x float>
88 ret <4 x float> %r
89 }
91 ; Arguments are flattened to represent the actual VGPR_A layout, so we have no
92 ; extra moves in the generated kernel.
93 define amdgpu_ps <4 x float> @image_bvh64_intersect_ray(<2 x i32> %node_ptr_vec, float %ray_extent, float %ray_origin_x, float %ray_origin_y, float %ray_origin_z, float %ray_dir_x, float %ray_dir_y, float %ray_dir_z, float %ray_inv_dir_x, float %ray_inv_dir_y, float %ray_inv_dir_z, <4 x i32> inreg %tdescr) {
94 ; GCN-LABEL: image_bvh64_intersect_ray:
95 ; GCN: ; %bb.0: ; %main_body
96 ; GCN-NEXT: image_bvh64_intersect_ray v[0:3], v[0:15], s[0:3]
97 ; GCN-NEXT: s_waitcnt vmcnt(0)
98 ; GCN-NEXT: ; return to shader part epilog
99 main_body:
100 %node_ptr = bitcast <2 x i32> %node_ptr_vec to i64
101 %ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0
102 %ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1
103 %ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2
104 %ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0
105 %ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1
106 %ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2
107 %ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0
108 %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
109 %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
110 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
111 %r = bitcast <4 x i32> %v to <4 x float>
112 ret <4 x float> %r
113 }
115 define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 inreg %node_ptr, float inreg %ray_extent, <3 x float> inreg %ray_origin, <3 x half> inreg %ray_dir, <3 x half> inreg %ray_inv_dir, <4 x i32> inreg %tdescr) {
116 ; GFX10-LABEL: image_bvh64_intersect_ray_a16:
117 ; GFX10: ; %bb.0: ; %main_body
118 ; GFX10-NEXT: s_mov_b32 s14, s12
119 ; GFX10-NEXT: s_mov_b32 s12, s10
120 ; GFX10-NEXT: s_lshr_b32 s10, s8, 16
121 ; GFX10-NEXT: s_pack_ll_b32_b16 s7, s7, s8
122 ; GFX10-NEXT: s_pack_ll_b32_b16 s8, s10, s9
123 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
124 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
125 ; GFX10-NEXT: v_mov_b32_e32 v2, s2
126 ; GFX10-NEXT: v_mov_b32_e32 v3, s3
127 ; GFX10-NEXT: v_mov_b32_e32 v4, s4
128 ; GFX10-NEXT: v_mov_b32_e32 v5, s5
129 ; GFX10-NEXT: v_mov_b32_e32 v6, s6
130 ; GFX10-NEXT: v_mov_b32_e32 v7, s7
131 ; GFX10-NEXT: v_mov_b32_e32 v8, s8
132 ; GFX10-NEXT: s_mov_b32 s15, s13
133 ; GFX10-NEXT: s_mov_b32 s13, s11
134 ; GFX10-NEXT: image_bvh64_intersect_ray v[0:3], v[0:15], s[12:15] a16
135 ; GFX10-NEXT: s_waitcnt vmcnt(0)
136 ; GFX10-NEXT: ; return to shader part epilog
137 ;
138 ; GFX11-LABEL: image_bvh64_intersect_ray_a16:
139 ; GFX11: ; %bb.0: ; %main_body
140 ; GFX11-NEXT: v_mov_b32_e32 v0, s3
141 ; GFX11-NEXT: v_mov_b32_e32 v6, s0
142 ; GFX11-NEXT: s_lshr_b32 s0, s8, 16
143 ; GFX11-NEXT: s_lshr_b32 s3, s6, 16
144 ; GFX11-NEXT: v_mov_b32_e32 v7, s1
145 ; GFX11-NEXT: s_pack_ll_b32_b16 s0, s3, s0
146 ; GFX11-NEXT: s_pack_ll_b32_b16 s1, s6, s8
147 ; GFX11-NEXT: s_pack_ll_b32_b16 s3, s7, s9
148 ; GFX11-NEXT: v_mov_b32_e32 v1, s4
149 ; GFX11-NEXT: v_mov_b32_e32 v2, s5
150 ; GFX11-NEXT: v_mov_b32_e32 v3, s1
151 ; GFX11-NEXT: v_mov_b32_e32 v4, s0
152 ; GFX11-NEXT: v_mov_b32_e32 v5, s3
153 ; GFX11-NEXT: v_mov_b32_e32 v8, s2
154 ; GFX11-NEXT: s_mov_b32 s15, s13
155 ; GFX11-NEXT: s_mov_b32 s14, s12
156 ; GFX11-NEXT: s_mov_b32 s13, s11
157 ; GFX11-NEXT: s_mov_b32 s12, s10
158 ; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[12:15] a16
159 ; GFX11-NEXT: s_waitcnt vmcnt(0)
160 ; GFX11-NEXT: ; return to shader part epilog
161 main_body:
162 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
163 %r = bitcast <4 x i32> %v to <4 x float>
164 ret <4 x float> %r
165 }
167 ; TODO: NSA reassign is very limited and cannot work with VGPR tuples and subregs.
169 define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(i32* %p_node_ptr, float* %p_ray, <4 x i32> inreg %tdescr) {
170 ; GFX1013-LABEL: image_bvh_intersect_ray_nsa_reassign:
171 ; GFX1013: ; %bb.0: ; %main_body
172 ; GFX1013-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
173 ; GFX1013-NEXT: v_lshlrev_b32_e32 v0, 2, v0
174 ; GFX1013-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
175 ; GFX1013-NEXT: v_mov_b32_e32 v6, 4.0
176 ; GFX1013-NEXT: v_mov_b32_e32 v7, 0x40a00000
177 ; GFX1013-NEXT: v_mov_b32_e32 v8, 0x40c00000
178 ; GFX1013-NEXT: v_mov_b32_e32 v9, 0x40e00000
179 ; GFX1013-NEXT: v_mov_b32_e32 v10, 0x41000000
180 ; GFX1013-NEXT: s_waitcnt lgkmcnt(0)
181 ; GFX1013-NEXT: v_add_co_u32 v2, s4, s4, v0
182 ; GFX1013-NEXT: v_add_co_ci_u32_e64 v3, s4, s5, 0, s4
183 ; GFX1013-NEXT: v_add_co_u32 v4, s4, s6, v0
184 ; GFX1013-NEXT: v_add_co_ci_u32_e64 v5, s4, s7, 0, s4
185 ; GFX1013-NEXT: flat_load_dword v0, v[2:3]
186 ; GFX1013-NEXT: flat_load_dword v1, v[4:5]
187 ; GFX1013-NEXT: v_mov_b32_e32 v2, 0
188 ; GFX1013-NEXT: v_mov_b32_e32 v3, 1.0
189 ; GFX1013-NEXT: v_mov_b32_e32 v4, 2.0
190 ; GFX1013-NEXT: v_mov_b32_e32 v5, 0x40400000
191 ; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
192 ; GFX1013-NEXT: image_bvh_intersect_ray v[0:3], v[0:15], s[0:3]
193 ; GFX1013-NEXT: s_waitcnt vmcnt(0)
194 ; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
195 ; GFX1013-NEXT: s_endpgm
196 ;
197 ; GFX1030-LABEL: image_bvh_intersect_ray_nsa_reassign:
198 ; GFX1030: ; %bb.0: ; %main_body
199 ; GFX1030-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
200 ; GFX1030-NEXT: v_lshlrev_b32_e32 v2, 2, v0
201 ; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
202 ; GFX1030-NEXT: v_mov_b32_e32 v10, 0x41000000
203 ; GFX1030-NEXT: v_mov_b32_e32 v9, 0x40e00000
204 ; GFX1030-NEXT: v_mov_b32_e32 v8, 0x40c00000
205 ; GFX1030-NEXT: v_mov_b32_e32 v7, 0x40a00000
206 ; GFX1030-NEXT: v_mov_b32_e32 v6, 4.0
207 ; GFX1030-NEXT: v_mov_b32_e32 v5, 0x40400000
208 ; GFX1030-NEXT: v_mov_b32_e32 v4, 2.0
209 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
210 ; GFX1030-NEXT: v_add_co_u32 v0, s4, s4, v2
211 ; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4
212 ; GFX1030-NEXT: v_add_co_u32 v2, s4, s6, v2
213 ; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, s7, 0, s4
214 ; GFX1030-NEXT: flat_load_dword v0, v[0:1]
215 ; GFX1030-NEXT: flat_load_dword v1, v[2:3]
216 ; GFX1030-NEXT: v_mov_b32_e32 v2, 0
217 ; GFX1030-NEXT: v_mov_b32_e32 v3, 1.0
218 ; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
219 ; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[0:15], s[0:3]
220 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
221 ; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
222 ; GFX1030-NEXT: s_endpgm
223 ;
224 ; GFX11-LABEL: image_bvh_intersect_ray_nsa_reassign:
225 ; GFX11: ; %bb.0: ; %main_body
226 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
227 ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0
228 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x34
229 ; GFX11-NEXT: v_mov_b32_e32 v4, 4.0
230 ; GFX11-NEXT: v_mov_b32_e32 v5, 0x40a00000
231 ; GFX11-NEXT: v_mov_b32_e32 v6, 0
232 ; GFX11-NEXT: v_mov_b32_e32 v7, 1.0
233 ; GFX11-NEXT: v_mov_b32_e32 v8, 2.0
234 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
235 ; GFX11-NEXT: v_add_co_u32 v0, s4, s4, v2
236 ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4
237 ; GFX11-NEXT: v_add_co_u32 v2, s4, s6, v2
238 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s7, 0, s4
239 ; GFX11-NEXT: flat_load_b32 v9, v[0:1]
240 ; GFX11-NEXT: flat_load_b32 v10, v[2:3]
241 ; GFX11-NEXT: v_mov_b32_e32 v0, 0x40c00000
242 ; GFX11-NEXT: v_mov_b32_e32 v1, 0x40e00000
243 ; GFX11-NEXT: v_mov_b32_e32 v2, 0x41000000
244 ; GFX11-NEXT: v_mov_b32_e32 v3, 0x40400000
245 ; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
246 ; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v9, v10, v[6:8], v[3:5], v[0:2]], s[0:3]
247 ; GFX11-NEXT: s_waitcnt vmcnt(0)
248 ; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3]
249 ; GFX11-NEXT: s_endpgm
250 main_body:
251 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
252 %gep_node_ptr = getelementptr inbounds i32, i32* %p_node_ptr, i32 %lid
253 %node_ptr = load i32, i32* %gep_node_ptr, align 4
254 %gep_ray = getelementptr inbounds float, float* %p_ray, i32 %lid
255 %ray_extent = load float, float* %gep_ray, align 4
256 %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
257 %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
258 %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
259 %ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0
260 %ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1
261 %ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2
262 %ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0
263 %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
264 %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
265 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
266 store <4 x i32> %v, <4 x i32>* undef
267 ret void
268 }
270 define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(i32* %p_node_ptr, float* %p_ray, <4 x i32> inreg %tdescr) {
271 ; GFX1013-LABEL: image_bvh_intersect_ray_a16_nsa_reassign:
272 ; GFX1013: ; %bb.0: ; %main_body
273 ; GFX1013-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
274 ; GFX1013-NEXT: v_lshlrev_b32_e32 v0, 2, v0
275 ; GFX1013-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
276 ; GFX1013-NEXT: v_mov_b32_e32 v6, 0x46004500
277 ; GFX1013-NEXT: v_mov_b32_e32 v7, 0x48004700
278 ; GFX1013-NEXT: s_waitcnt lgkmcnt(0)
279 ; GFX1013-NEXT: v_add_co_u32 v2, s4, s4, v0
280 ; GFX1013-NEXT: v_add_co_ci_u32_e64 v3, s4, s5, 0, s4
281 ; GFX1013-NEXT: v_add_co_u32 v4, s4, s6, v0
282 ; GFX1013-NEXT: v_add_co_ci_u32_e64 v5, s4, s7, 0, s4
283 ; GFX1013-NEXT: flat_load_dword v0, v[2:3]
284 ; GFX1013-NEXT: flat_load_dword v1, v[4:5]
285 ; GFX1013-NEXT: v_mov_b32_e32 v2, 0
286 ; GFX1013-NEXT: v_mov_b32_e32 v3, 1.0
287 ; GFX1013-NEXT: v_mov_b32_e32 v4, 2.0
288 ; GFX1013-NEXT: v_mov_b32_e32 v5, 0x44004200
289 ; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
290 ; GFX1013-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[0:3] a16
291 ; GFX1013-NEXT: s_waitcnt vmcnt(0)
292 ; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
293 ; GFX1013-NEXT: s_endpgm
294 ;
295 ; GFX1030-LABEL: image_bvh_intersect_ray_a16_nsa_reassign:
296 ; GFX1030: ; %bb.0: ; %main_body
297 ; GFX1030-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
298 ; GFX1030-NEXT: v_lshlrev_b32_e32 v2, 2, v0
299 ; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
300 ; GFX1030-NEXT: v_mov_b32_e32 v4, 2.0
301 ; GFX1030-NEXT: v_mov_b32_e32 v5, 0x44004200
302 ; GFX1030-NEXT: v_mov_b32_e32 v6, 0x46004500
303 ; GFX1030-NEXT: v_mov_b32_e32 v7, 0x48004700
304 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
305 ; GFX1030-NEXT: v_add_co_u32 v0, s4, s4, v2
306 ; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4
307 ; GFX1030-NEXT: v_add_co_u32 v2, s4, s6, v2
308 ; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, s7, 0, s4
309 ; GFX1030-NEXT: flat_load_dword v0, v[0:1]
310 ; GFX1030-NEXT: flat_load_dword v1, v[2:3]
311 ; GFX1030-NEXT: v_mov_b32_e32 v2, 0
312 ; GFX1030-NEXT: v_mov_b32_e32 v3, 1.0
313 ; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
314 ; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[0:3] a16
315 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
316 ; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
317 ; GFX1030-NEXT: s_endpgm
318 ;
319 ; GFX11-LABEL: image_bvh_intersect_ray_a16_nsa_reassign:
320 ; GFX11: ; %bb.0: ; %main_body
321 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
322 ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0
323 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x34
324 ; GFX11-NEXT: v_mov_b32_e32 v4, 1.0
325 ; GFX11-NEXT: v_mov_b32_e32 v5, 2.0
326 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
327 ; GFX11-NEXT: v_add_co_u32 v0, s4, s4, v2
328 ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4
329 ; GFX11-NEXT: v_add_co_u32 v2, s4, s6, v2
330 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s7, 0, s4
331 ; GFX11-NEXT: flat_load_b32 v6, v[0:1]
332 ; GFX11-NEXT: flat_load_b32 v7, v[2:3]
333 ; GFX11-NEXT: v_mov_b32_e32 v0, 0x46004200
334 ; GFX11-NEXT: v_mov_b32_e32 v1, 0x47004400
335 ; GFX11-NEXT: v_mov_b32_e32 v2, 0x48004500
336 ; GFX11-NEXT: v_mov_b32_e32 v3, 0
337 ; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
338 ; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v6, v7, v[3:5], v[0:2]], s[0:3] a16
339 ; GFX11-NEXT: s_waitcnt vmcnt(0)
340 ; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3]
341 ; GFX11-NEXT: s_endpgm
342 main_body:
343 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
344 %gep_node_ptr = getelementptr inbounds i32, i32* %p_node_ptr, i32 %lid
345 %node_ptr = load i32, i32* %gep_node_ptr, align 4
346 %gep_ray = getelementptr inbounds float, float* %p_ray, i32 %lid
347 %ray_extent = load float, float* %gep_ray, align 4
348 %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
349 %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
350 %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
351 %ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0
352 %ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1
353 %ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2
354 %ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0
355 %ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
356 %ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
357 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
358 store <4 x i32> %v, <4 x i32>* undef
359 ret void
360 }
362 define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(float* %p_ray, <4 x i32> inreg %tdescr) {
363 ; GFX1013-LABEL: image_bvh64_intersect_ray_nsa_reassign:
364 ; GFX1013: ; %bb.0: ; %main_body
365 ; GFX1013-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
366 ; GFX1013-NEXT: v_lshlrev_b32_e32 v0, 2, v0
367 ; GFX1013-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
368 ; GFX1013-NEXT: v_mov_b32_e32 v3, 0
369 ; GFX1013-NEXT: v_mov_b32_e32 v4, 1.0
370 ; GFX1013-NEXT: v_mov_b32_e32 v5, 2.0
371 ; GFX1013-NEXT: v_mov_b32_e32 v6, 0x40400000
372 ; GFX1013-NEXT: v_mov_b32_e32 v7, 4.0
373 ; GFX1013-NEXT: v_mov_b32_e32 v8, 0x40a00000
374 ; GFX1013-NEXT: v_mov_b32_e32 v9, 0x40c00000
375 ; GFX1013-NEXT: v_mov_b32_e32 v10, 0x40e00000
376 ; GFX1013-NEXT: v_mov_b32_e32 v11, 0x41000000
377 ; GFX1013-NEXT: s_waitcnt lgkmcnt(0)
378 ; GFX1013-NEXT: v_add_co_u32 v0, s4, s4, v0
379 ; GFX1013-NEXT: v_add_co_ci_u32_e64 v1, s4, s5, 0, s4
380 ; GFX1013-NEXT: flat_load_dword v2, v[0:1]
381 ; GFX1013-NEXT: v_mov_b32_e32 v0, 0xb36211c7
382 ; GFX1013-NEXT: v_mov_b32_e32 v1, 0x102
383 ; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
384 ; GFX1013-NEXT: image_bvh64_intersect_ray v[0:3], v[0:15], s[0:3]
385 ; GFX1013-NEXT: s_waitcnt vmcnt(0)
386 ; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
387 ; GFX1013-NEXT: s_endpgm
388 ;
389 ; GFX1030-LABEL: image_bvh64_intersect_ray_nsa_reassign:
390 ; GFX1030: ; %bb.0: ; %main_body
391 ; GFX1030-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
392 ; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 2, v0
393 ; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
394 ; GFX1030-NEXT: v_mov_b32_e32 v3, 0
395 ; GFX1030-NEXT: v_mov_b32_e32 v11, 0x41000000
396 ; GFX1030-NEXT: v_mov_b32_e32 v10, 0x40e00000
397 ; GFX1030-NEXT: v_mov_b32_e32 v9, 0x40c00000
398 ; GFX1030-NEXT: v_mov_b32_e32 v8, 0x40a00000
399 ; GFX1030-NEXT: v_mov_b32_e32 v7, 4.0
400 ; GFX1030-NEXT: v_mov_b32_e32 v6, 0x40400000
401 ; GFX1030-NEXT: v_mov_b32_e32 v5, 2.0
402 ; GFX1030-NEXT: v_mov_b32_e32 v4, 1.0
403 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
404 ; GFX1030-NEXT: v_add_co_u32 v0, s4, s4, v0
405 ; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4
406 ; GFX1030-NEXT: flat_load_dword v2, v[0:1]
407 ; GFX1030-NEXT: v_mov_b32_e32 v1, 0x102
408 ; GFX1030-NEXT: v_mov_b32_e32 v0, 0xb36211c7
409 ; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
410 ; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[0:15], s[0:3]
411 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
412 ; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
413 ; GFX1030-NEXT: s_endpgm
414 ;
415 ; GFX11-LABEL: image_bvh64_intersect_ray_nsa_reassign:
416 ; GFX11: ; %bb.0: ; %main_body
417 ; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x24
418 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
419 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x34
420 ; GFX11-NEXT: v_mov_b32_e32 v2, 0x41000000
421 ; GFX11-NEXT: v_mov_b32_e32 v3, 0x40400000
422 ; GFX11-NEXT: v_mov_b32_e32 v4, 4.0
423 ; GFX11-NEXT: v_mov_b32_e32 v5, 0x40a00000
424 ; GFX11-NEXT: v_mov_b32_e32 v6, 0
425 ; GFX11-NEXT: v_mov_b32_e32 v7, 1.0
426 ; GFX11-NEXT: v_mov_b32_e32 v8, 2.0
427 ; GFX11-NEXT: v_mov_b32_e32 v9, 0xb36211c7
428 ; GFX11-NEXT: v_mov_b32_e32 v10, 0x102
429 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
430 ; GFX11-NEXT: v_add_co_u32 v0, s4, s4, v0
431 ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4
432 ; GFX11-NEXT: flat_load_b32 v11, v[0:1]
433 ; GFX11-NEXT: v_mov_b32_e32 v0, 0x40c00000
434 ; GFX11-NEXT: v_mov_b32_e32 v1, 0x40e00000
435 ; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
436 ; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[9:10], v11, v[6:8], v[3:5], v[0:2]], s[0:3]
437 ; GFX11-NEXT: s_waitcnt vmcnt(0)
438 ; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3]
439 ; GFX11-NEXT: s_endpgm
440 main_body:
441 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
442 %gep_ray = getelementptr inbounds float, float* %p_ray, i32 %lid
443 %ray_extent = load float, float* %gep_ray, align 4
444 %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
445 %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
446 %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
447 %ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0
448 %ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1
449 %ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2
450 %ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0
451 %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
452 %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
453 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 1111111111111, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
454 store <4 x i32> %v, <4 x i32>* undef
455 ret void
456 }
458 define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(float* %p_ray, <4 x i32> inreg %tdescr) {
459 ; GFX1013-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign:
460 ; GFX1013: ; %bb.0: ; %main_body
461 ; GFX1013-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
462 ; GFX1013-NEXT: v_lshlrev_b32_e32 v0, 2, v0
463 ; GFX1013-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
464 ; GFX1013-NEXT: v_mov_b32_e32 v3, 0
465 ; GFX1013-NEXT: v_mov_b32_e32 v4, 1.0
466 ; GFX1013-NEXT: v_mov_b32_e32 v5, 2.0
467 ; GFX1013-NEXT: v_mov_b32_e32 v6, 0x44004200
468 ; GFX1013-NEXT: v_mov_b32_e32 v7, 0x46004500
469 ; GFX1013-NEXT: v_mov_b32_e32 v8, 0x48004700
470 ; GFX1013-NEXT: s_waitcnt lgkmcnt(0)
471 ; GFX1013-NEXT: v_add_co_u32 v0, s4, s4, v0
472 ; GFX1013-NEXT: v_add_co_ci_u32_e64 v1, s4, s5, 0, s4
473 ; GFX1013-NEXT: flat_load_dword v2, v[0:1]
474 ; GFX1013-NEXT: v_mov_b32_e32 v0, 0xb36211c6
475 ; GFX1013-NEXT: v_mov_b32_e32 v1, 0x102
476 ; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
477 ; GFX1013-NEXT: image_bvh64_intersect_ray v[0:3], v[0:15], s[0:3] a16
478 ; GFX1013-NEXT: s_waitcnt vmcnt(0)
479 ; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
480 ; GFX1013-NEXT: s_endpgm
481 ;
482 ; GFX1030-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign:
483 ; GFX1030: ; %bb.0: ; %main_body
484 ; GFX1030-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
485 ; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 2, v0
486 ; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
487 ; GFX1030-NEXT: v_mov_b32_e32 v3, 0
488 ; GFX1030-NEXT: v_mov_b32_e32 v5, 2.0
489 ; GFX1030-NEXT: v_mov_b32_e32 v4, 1.0
490 ; GFX1030-NEXT: v_mov_b32_e32 v6, 0x44004200
491 ; GFX1030-NEXT: v_mov_b32_e32 v7, 0x46004500
492 ; GFX1030-NEXT: v_mov_b32_e32 v8, 0x48004700
493 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
494 ; GFX1030-NEXT: v_add_co_u32 v0, s4, s4, v0
495 ; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4
496 ; GFX1030-NEXT: flat_load_dword v2, v[0:1]
497 ; GFX1030-NEXT: v_mov_b32_e32 v1, 0x102
498 ; GFX1030-NEXT: v_mov_b32_e32 v0, 0xb36211c6
499 ; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
500 ; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[0:15], s[0:3] a16
501 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
502 ; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
503 ; GFX1030-NEXT: s_endpgm
504 ;
505 ; GFX11-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign:
506 ; GFX11: ; %bb.0: ; %main_body
507 ; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x24
508 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
509 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x34
510 ; GFX11-NEXT: v_mov_b32_e32 v2, 0x48004500
511 ; GFX11-NEXT: v_mov_b32_e32 v3, 0
512 ; GFX11-NEXT: v_mov_b32_e32 v4, 1.0
513 ; GFX11-NEXT: v_mov_b32_e32 v5, 2.0
514 ; GFX11-NEXT: v_mov_b32_e32 v6, 0xb36211c6
515 ; GFX11-NEXT: v_mov_b32_e32 v7, 0x102
516 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
517 ; GFX11-NEXT: v_add_co_u32 v0, s4, s4, v0
518 ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4
519 ; GFX11-NEXT: flat_load_b32 v8, v[0:1]
520 ; GFX11-NEXT: v_mov_b32_e32 v0, 0x46004200
521 ; GFX11-NEXT: v_mov_b32_e32 v1, 0x47004400
522 ; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
523 ; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[3:5], v[0:2]], s[0:3] a16
524 ; GFX11-NEXT: s_waitcnt vmcnt(0)
525 ; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3]
526 ; GFX11-NEXT: s_endpgm
527 main_body:
528 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
529 %gep_ray = getelementptr inbounds float, float* %p_ray, i32 %lid
530 %ray_extent = load float, float* %gep_ray, align 4
531 %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
532 %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
533 %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
534 %ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0
535 %ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1
536 %ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2
537 %ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0
538 %ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
539 %ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
540 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 1111111111110, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
541 store <4 x i32> %v, <4 x i32>* undef
542 ret void
543 }
545 declare i32 @llvm.amdgcn.workitem.id.x()