| blob | 3e3f8c33e3c2ec522bb861947d5d836389a94ad3 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
3 ; RUN: -disable-strictnode-mutation -target-abi=ilp32d \
4 ; RUN: | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
5 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
6 ; RUN: -disable-strictnode-mutation -target-abi=lp64d \
7 ; RUN: | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
8 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
9 ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
10 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
11 ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
13 ; NOTE: The rounding mode metadata does not effect which instruction is
14 ; selected. Dynamic rounding mode is always used for operations that
15 ; support rounding mode.
17 define float @fcvt_s_d(double %a) nounwind strictfp {
18 ; CHECKIFD-LABEL: fcvt_s_d:
19 ; CHECKIFD: # %bb.0:
20 ; CHECKIFD-NEXT: fcvt.s.d fa0, fa0
21 ; CHECKIFD-NEXT: ret
22 ;
23 ; RV32I-LABEL: fcvt_s_d:
24 ; RV32I: # %bb.0:
25 ; RV32I-NEXT: addi sp, sp, -16
26 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
27 ; RV32I-NEXT: call __truncdfsf2@plt
28 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
29 ; RV32I-NEXT: addi sp, sp, 16
30 ; RV32I-NEXT: ret
31 ;
32 ; RV64I-LABEL: fcvt_s_d:
33 ; RV64I: # %bb.0:
34 ; RV64I-NEXT: addi sp, sp, -16
35 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
36 ; RV64I-NEXT: call __truncdfsf2@plt
37 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
38 ; RV64I-NEXT: addi sp, sp, 16
39 ; RV64I-NEXT: ret
40 %1 = call float @llvm.experimental.constrained.fptrunc.f32.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
41 ret float %1
42 }
43 declare float @llvm.experimental.constrained.fptrunc.f32.f64(double, metadata, metadata)
45 define double @fcvt_d_s(float %a) nounwind strictfp {
46 ; CHECKIFD-LABEL: fcvt_d_s:
47 ; CHECKIFD: # %bb.0:
48 ; CHECKIFD-NEXT: fcvt.d.s fa0, fa0
49 ; CHECKIFD-NEXT: ret
50 ;
51 ; RV32I-LABEL: fcvt_d_s:
52 ; RV32I: # %bb.0:
53 ; RV32I-NEXT: addi sp, sp, -16
54 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
55 ; RV32I-NEXT: call __extendsfdf2@plt
56 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
57 ; RV32I-NEXT: addi sp, sp, 16
58 ; RV32I-NEXT: ret
59 ;
60 ; RV64I-LABEL: fcvt_d_s:
61 ; RV64I: # %bb.0:
62 ; RV64I-NEXT: addi sp, sp, -16
63 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
64 ; RV64I-NEXT: call __extendsfdf2@plt
65 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
66 ; RV64I-NEXT: addi sp, sp, 16
67 ; RV64I-NEXT: ret
68 %1 = call double @llvm.experimental.constrained.fpext.f64.f32(float %a, metadata !"fpexcept.strict")
69 ret double %1
70 }
71 declare double @llvm.experimental.constrained.fpext.f64.f32(float, metadata)
73 define i32 @fcvt_w_d(double %a) nounwind strictfp {
74 ; CHECKIFD-LABEL: fcvt_w_d:
75 ; CHECKIFD: # %bb.0:
76 ; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz
77 ; CHECKIFD-NEXT: ret
78 ;
79 ; RV32I-LABEL: fcvt_w_d:
80 ; RV32I: # %bb.0:
81 ; RV32I-NEXT: addi sp, sp, -16
82 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
83 ; RV32I-NEXT: call __fixdfsi@plt
84 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
85 ; RV32I-NEXT: addi sp, sp, 16
86 ; RV32I-NEXT: ret
87 ;
88 ; RV64I-LABEL: fcvt_w_d:
89 ; RV64I: # %bb.0:
90 ; RV64I-NEXT: addi sp, sp, -16
91 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
92 ; RV64I-NEXT: call __fixdfsi@plt
93 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
94 ; RV64I-NEXT: addi sp, sp, 16
95 ; RV64I-NEXT: ret
96 %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict") strictfp
97 ret i32 %1
98 }
99 declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
101 ; For RV64D, fcvt.lu.d is semantically equivalent to fcvt.wu.d in this case
102 ; because fptosi will produce poison if the result doesn't fit into an i32.
103 define i32 @fcvt_wu_d(double %a) nounwind strictfp {
104 ; CHECKIFD-LABEL: fcvt_wu_d:
105 ; CHECKIFD: # %bb.0:
106 ; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rtz
107 ; CHECKIFD-NEXT: ret
108 ;
109 ; RV32I-LABEL: fcvt_wu_d:
110 ; RV32I: # %bb.0:
111 ; RV32I-NEXT: addi sp, sp, -16
112 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
113 ; RV32I-NEXT: call __fixunsdfsi@plt
114 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
115 ; RV32I-NEXT: addi sp, sp, 16
116 ; RV32I-NEXT: ret
117 ;
118 ; RV64I-LABEL: fcvt_wu_d:
119 ; RV64I: # %bb.0:
120 ; RV64I-NEXT: addi sp, sp, -16
121 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
122 ; RV64I-NEXT: call __fixunsdfsi@plt
123 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
124 ; RV64I-NEXT: addi sp, sp, 16
125 ; RV64I-NEXT: ret
126 %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict") strictfp
127 ret i32 %1
128 }
129 declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
131 ; Test where the fptoui has multiple uses, one of which causes a sext to be
132 ; inserted on RV64.
133 define i32 @fcvt_wu_d_multiple_use(double %x, i32* %y) nounwind {
134 ; CHECKIFD-LABEL: fcvt_wu_d_multiple_use:
135 ; CHECKIFD: # %bb.0:
136 ; CHECKIFD-NEXT: fcvt.wu.d a1, fa0, rtz
137 ; CHECKIFD-NEXT: li a0, 1
138 ; CHECKIFD-NEXT: beqz a1, .LBB4_2
139 ; CHECKIFD-NEXT: # %bb.1:
140 ; CHECKIFD-NEXT: mv a0, a1
141 ; CHECKIFD-NEXT: .LBB4_2:
142 ; CHECKIFD-NEXT: ret
143 ;
144 ; RV32I-LABEL: fcvt_wu_d_multiple_use:
145 ; RV32I: # %bb.0:
146 ; RV32I-NEXT: addi sp, sp, -16
147 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
148 ; RV32I-NEXT: call __fixunsdfsi@plt
149 ; RV32I-NEXT: mv a1, a0
150 ; RV32I-NEXT: li a0, 1
151 ; RV32I-NEXT: beqz a1, .LBB4_2
152 ; RV32I-NEXT: # %bb.1:
153 ; RV32I-NEXT: mv a0, a1
154 ; RV32I-NEXT: .LBB4_2:
155 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
156 ; RV32I-NEXT: addi sp, sp, 16
157 ; RV32I-NEXT: ret
158 ;
159 ; RV64I-LABEL: fcvt_wu_d_multiple_use:
160 ; RV64I: # %bb.0:
161 ; RV64I-NEXT: addi sp, sp, -16
162 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
163 ; RV64I-NEXT: call __fixunsdfsi@plt
164 ; RV64I-NEXT: mv a1, a0
165 ; RV64I-NEXT: li a0, 1
166 ; RV64I-NEXT: beqz a1, .LBB4_2
167 ; RV64I-NEXT: # %bb.1:
168 ; RV64I-NEXT: mv a0, a1
169 ; RV64I-NEXT: .LBB4_2:
170 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
171 ; RV64I-NEXT: addi sp, sp, 16
172 ; RV64I-NEXT: ret
173 %a = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %x, metadata !"fpexcept.strict") strictfp
174 %b = icmp eq i32 %a, 0
175 %c = select i1 %b, i32 1, i32 %a
176 ret i32 %c
177 }
179 define double @fcvt_d_w(i32 %a) nounwind strictfp {
180 ; CHECKIFD-LABEL: fcvt_d_w:
181 ; CHECKIFD: # %bb.0:
182 ; CHECKIFD-NEXT: fcvt.d.w fa0, a0
183 ; CHECKIFD-NEXT: ret
184 ;
185 ; RV32I-LABEL: fcvt_d_w:
186 ; RV32I: # %bb.0:
187 ; RV32I-NEXT: addi sp, sp, -16
188 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
189 ; RV32I-NEXT: call __floatsidf@plt
190 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
191 ; RV32I-NEXT: addi sp, sp, 16
192 ; RV32I-NEXT: ret
193 ;
194 ; RV64I-LABEL: fcvt_d_w:
195 ; RV64I: # %bb.0:
196 ; RV64I-NEXT: addi sp, sp, -16
197 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
198 ; RV64I-NEXT: sext.w a0, a0
199 ; RV64I-NEXT: call __floatsidf@plt
200 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
201 ; RV64I-NEXT: addi sp, sp, 16
202 ; RV64I-NEXT: ret
203 %1 = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
204 ret double %1
205 }
206 declare double @llvm.experimental.constrained.sitofp.f64.i32(i32, metadata, metadata)
208 define double @fcvt_d_w_load(i32* %p) nounwind strictfp {
209 ; CHECKIFD-LABEL: fcvt_d_w_load:
210 ; CHECKIFD: # %bb.0:
211 ; CHECKIFD-NEXT: lw a0, 0(a0)
212 ; CHECKIFD-NEXT: fcvt.d.w fa0, a0
213 ; CHECKIFD-NEXT: ret
214 ;
215 ; RV32I-LABEL: fcvt_d_w_load:
216 ; RV32I: # %bb.0:
217 ; RV32I-NEXT: addi sp, sp, -16
218 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
219 ; RV32I-NEXT: lw a0, 0(a0)
220 ; RV32I-NEXT: call __floatsidf@plt
221 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
222 ; RV32I-NEXT: addi sp, sp, 16
223 ; RV32I-NEXT: ret
224 ;
225 ; RV64I-LABEL: fcvt_d_w_load:
226 ; RV64I: # %bb.0:
227 ; RV64I-NEXT: addi sp, sp, -16
228 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
229 ; RV64I-NEXT: lw a0, 0(a0)
230 ; RV64I-NEXT: call __floatsidf@plt
231 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
232 ; RV64I-NEXT: addi sp, sp, 16
233 ; RV64I-NEXT: ret
234 %a = load i32, i32* %p
235 %1 = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
236 ret double %1
237 }
239 define double @fcvt_d_wu(i32 %a) nounwind strictfp {
240 ; CHECKIFD-LABEL: fcvt_d_wu:
241 ; CHECKIFD: # %bb.0:
242 ; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
243 ; CHECKIFD-NEXT: ret
244 ;
245 ; RV32I-LABEL: fcvt_d_wu:
246 ; RV32I: # %bb.0:
247 ; RV32I-NEXT: addi sp, sp, -16
248 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
249 ; RV32I-NEXT: call __floatunsidf@plt
250 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
251 ; RV32I-NEXT: addi sp, sp, 16
252 ; RV32I-NEXT: ret
253 ;
254 ; RV64I-LABEL: fcvt_d_wu:
255 ; RV64I: # %bb.0:
256 ; RV64I-NEXT: addi sp, sp, -16
257 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
258 ; RV64I-NEXT: sext.w a0, a0
259 ; RV64I-NEXT: call __floatunsidf@plt
260 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
261 ; RV64I-NEXT: addi sp, sp, 16
262 ; RV64I-NEXT: ret
263 %1 = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
264 ret double %1
265 }
266 declare double @llvm.experimental.constrained.uitofp.f64.i32(i32, metadata, metadata)
268 define double @fcvt_d_wu_load(i32* %p) nounwind strictfp {
269 ; RV32IFD-LABEL: fcvt_d_wu_load:
270 ; RV32IFD: # %bb.0:
271 ; RV32IFD-NEXT: lw a0, 0(a0)
272 ; RV32IFD-NEXT: fcvt.d.wu fa0, a0
273 ; RV32IFD-NEXT: ret
274 ;
275 ; RV64IFD-LABEL: fcvt_d_wu_load:
276 ; RV64IFD: # %bb.0:
277 ; RV64IFD-NEXT: lwu a0, 0(a0)
278 ; RV64IFD-NEXT: fcvt.d.wu fa0, a0
279 ; RV64IFD-NEXT: ret
280 ;
281 ; RV32I-LABEL: fcvt_d_wu_load:
282 ; RV32I: # %bb.0:
283 ; RV32I-NEXT: addi sp, sp, -16
284 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
285 ; RV32I-NEXT: lw a0, 0(a0)
286 ; RV32I-NEXT: call __floatunsidf@plt
287 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
288 ; RV32I-NEXT: addi sp, sp, 16
289 ; RV32I-NEXT: ret
290 ;
291 ; RV64I-LABEL: fcvt_d_wu_load:
292 ; RV64I: # %bb.0:
293 ; RV64I-NEXT: addi sp, sp, -16
294 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
295 ; RV64I-NEXT: lw a0, 0(a0)
296 ; RV64I-NEXT: call __floatunsidf@plt
297 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
298 ; RV64I-NEXT: addi sp, sp, 16
299 ; RV64I-NEXT: ret
300 %a = load i32, i32* %p
301 %1 = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
302 ret double %1
303 }
305 define i64 @fcvt_l_d(double %a) nounwind strictfp {
306 ; RV32IFD-LABEL: fcvt_l_d:
307 ; RV32IFD: # %bb.0:
308 ; RV32IFD-NEXT: addi sp, sp, -16
309 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
310 ; RV32IFD-NEXT: call __fixdfdi@plt
311 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
312 ; RV32IFD-NEXT: addi sp, sp, 16
313 ; RV32IFD-NEXT: ret
314 ;
315 ; RV64IFD-LABEL: fcvt_l_d:
316 ; RV64IFD: # %bb.0:
317 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
318 ; RV64IFD-NEXT: ret
319 ;
320 ; RV32I-LABEL: fcvt_l_d:
321 ; RV32I: # %bb.0:
322 ; RV32I-NEXT: addi sp, sp, -16
323 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
324 ; RV32I-NEXT: call __fixdfdi@plt
325 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
326 ; RV32I-NEXT: addi sp, sp, 16
327 ; RV32I-NEXT: ret
328 ;
329 ; RV64I-LABEL: fcvt_l_d:
330 ; RV64I: # %bb.0:
331 ; RV64I-NEXT: addi sp, sp, -16
332 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
333 ; RV64I-NEXT: call __fixdfdi@plt
334 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
335 ; RV64I-NEXT: addi sp, sp, 16
336 ; RV64I-NEXT: ret
337 %1 = call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %a, metadata !"fpexcept.strict") strictfp
338 ret i64 %1
339 }
340 declare i64 @llvm.experimental.constrained.fptosi.i64.f64(double, metadata)
342 define i64 @fcvt_lu_d(double %a) nounwind strictfp {
343 ; RV32IFD-LABEL: fcvt_lu_d:
344 ; RV32IFD: # %bb.0:
345 ; RV32IFD-NEXT: addi sp, sp, -16
346 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
347 ; RV32IFD-NEXT: call __fixunsdfdi@plt
348 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
349 ; RV32IFD-NEXT: addi sp, sp, 16
350 ; RV32IFD-NEXT: ret
351 ;
352 ; RV64IFD-LABEL: fcvt_lu_d:
353 ; RV64IFD: # %bb.0:
354 ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
355 ; RV64IFD-NEXT: ret
356 ;
357 ; RV32I-LABEL: fcvt_lu_d:
358 ; RV32I: # %bb.0:
359 ; RV32I-NEXT: addi sp, sp, -16
360 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
361 ; RV32I-NEXT: call __fixunsdfdi@plt
362 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
363 ; RV32I-NEXT: addi sp, sp, 16
364 ; RV32I-NEXT: ret
365 ;
366 ; RV64I-LABEL: fcvt_lu_d:
367 ; RV64I: # %bb.0:
368 ; RV64I-NEXT: addi sp, sp, -16
369 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
370 ; RV64I-NEXT: call __fixunsdfdi@plt
371 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
372 ; RV64I-NEXT: addi sp, sp, 16
373 ; RV64I-NEXT: ret
374 %1 = call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %a, metadata !"fpexcept.strict") strictfp
375 ret i64 %1
376 }
377 declare i64 @llvm.experimental.constrained.fptoui.i64.f64(double, metadata)
379 define double @fcvt_d_l(i64 %a) nounwind strictfp {
380 ; RV32IFD-LABEL: fcvt_d_l:
381 ; RV32IFD: # %bb.0:
382 ; RV32IFD-NEXT: addi sp, sp, -16
383 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
384 ; RV32IFD-NEXT: call __floatdidf@plt
385 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
386 ; RV32IFD-NEXT: addi sp, sp, 16
387 ; RV32IFD-NEXT: ret
388 ;
389 ; RV64IFD-LABEL: fcvt_d_l:
390 ; RV64IFD: # %bb.0:
391 ; RV64IFD-NEXT: fcvt.d.l fa0, a0
392 ; RV64IFD-NEXT: ret
393 ;
394 ; RV32I-LABEL: fcvt_d_l:
395 ; RV32I: # %bb.0:
396 ; RV32I-NEXT: addi sp, sp, -16
397 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
398 ; RV32I-NEXT: call __floatdidf@plt
399 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
400 ; RV32I-NEXT: addi sp, sp, 16
401 ; RV32I-NEXT: ret
402 ;
403 ; RV64I-LABEL: fcvt_d_l:
404 ; RV64I: # %bb.0:
405 ; RV64I-NEXT: addi sp, sp, -16
406 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
407 ; RV64I-NEXT: call __floatdidf@plt
408 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
409 ; RV64I-NEXT: addi sp, sp, 16
410 ; RV64I-NEXT: ret
411 %1 = call double @llvm.experimental.constrained.sitofp.f64.i64(i64 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
412 ret double %1
413 }
414 declare double @llvm.experimental.constrained.sitofp.f64.i64(i64, metadata, metadata)
416 define double @fcvt_d_lu(i64 %a) nounwind strictfp {
417 ; RV32IFD-LABEL: fcvt_d_lu:
418 ; RV32IFD: # %bb.0:
419 ; RV32IFD-NEXT: addi sp, sp, -16
420 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
421 ; RV32IFD-NEXT: call __floatundidf@plt
422 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
423 ; RV32IFD-NEXT: addi sp, sp, 16
424 ; RV32IFD-NEXT: ret
425 ;
426 ; RV64IFD-LABEL: fcvt_d_lu:
427 ; RV64IFD: # %bb.0:
428 ; RV64IFD-NEXT: fcvt.d.lu fa0, a0
429 ; RV64IFD-NEXT: ret
430 ;
431 ; RV32I-LABEL: fcvt_d_lu:
432 ; RV32I: # %bb.0:
433 ; RV32I-NEXT: addi sp, sp, -16
434 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
435 ; RV32I-NEXT: call __floatundidf@plt
436 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
437 ; RV32I-NEXT: addi sp, sp, 16
438 ; RV32I-NEXT: ret
439 ;
440 ; RV64I-LABEL: fcvt_d_lu:
441 ; RV64I: # %bb.0:
442 ; RV64I-NEXT: addi sp, sp, -16
443 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
444 ; RV64I-NEXT: call __floatundidf@plt
445 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
446 ; RV64I-NEXT: addi sp, sp, 16
447 ; RV64I-NEXT: ret
448 %1 = call double @llvm.experimental.constrained.uitofp.f64.i64(i64 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
449 ret double %1
450 }
451 declare double @llvm.experimental.constrained.uitofp.f64.i64(i64, metadata, metadata)
453 define double @fcvt_d_w_i8(i8 signext %a) nounwind strictfp {
454 ; CHECKIFD-LABEL: fcvt_d_w_i8:
455 ; CHECKIFD: # %bb.0:
456 ; CHECKIFD-NEXT: fcvt.d.w fa0, a0
457 ; CHECKIFD-NEXT: ret
458 ;
459 ; RV32I-LABEL: fcvt_d_w_i8:
460 ; RV32I: # %bb.0:
461 ; RV32I-NEXT: addi sp, sp, -16
462 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
463 ; RV32I-NEXT: call __floatsidf@plt
464 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
465 ; RV32I-NEXT: addi sp, sp, 16
466 ; RV32I-NEXT: ret
467 ;
468 ; RV64I-LABEL: fcvt_d_w_i8:
469 ; RV64I: # %bb.0:
470 ; RV64I-NEXT: addi sp, sp, -16
471 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
472 ; RV64I-NEXT: call __floatsidf@plt
473 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
474 ; RV64I-NEXT: addi sp, sp, 16
475 ; RV64I-NEXT: ret
476 %1 = call double @llvm.experimental.constrained.sitofp.f64.i8(i8 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
477 ret double %1
478 }
479 declare double @llvm.experimental.constrained.sitofp.f64.i8(i8, metadata, metadata)
481 define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind strictfp {
482 ; CHECKIFD-LABEL: fcvt_d_wu_i8:
483 ; CHECKIFD: # %bb.0:
484 ; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
485 ; CHECKIFD-NEXT: ret
486 ;
487 ; RV32I-LABEL: fcvt_d_wu_i8:
488 ; RV32I: # %bb.0:
489 ; RV32I-NEXT: addi sp, sp, -16
490 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
491 ; RV32I-NEXT: call __floatunsidf@plt
492 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
493 ; RV32I-NEXT: addi sp, sp, 16
494 ; RV32I-NEXT: ret
495 ;
496 ; RV64I-LABEL: fcvt_d_wu_i8:
497 ; RV64I: # %bb.0:
498 ; RV64I-NEXT: addi sp, sp, -16
499 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
500 ; RV64I-NEXT: call __floatunsidf@plt
501 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
502 ; RV64I-NEXT: addi sp, sp, 16
503 ; RV64I-NEXT: ret
504 %1 = call double @llvm.experimental.constrained.uitofp.f64.i8(i8 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
505 ret double %1
506 }
507 declare double @llvm.experimental.constrained.uitofp.f64.i8(i8, metadata, metadata)
509 define double @fcvt_d_w_i16(i16 signext %a) nounwind strictfp {
510 ; CHECKIFD-LABEL: fcvt_d_w_i16:
511 ; CHECKIFD: # %bb.0:
512 ; CHECKIFD-NEXT: fcvt.d.w fa0, a0
513 ; CHECKIFD-NEXT: ret
514 ;
515 ; RV32I-LABEL: fcvt_d_w_i16:
516 ; RV32I: # %bb.0:
517 ; RV32I-NEXT: addi sp, sp, -16
518 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
519 ; RV32I-NEXT: call __floatsidf@plt
520 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
521 ; RV32I-NEXT: addi sp, sp, 16
522 ; RV32I-NEXT: ret
523 ;
524 ; RV64I-LABEL: fcvt_d_w_i16:
525 ; RV64I: # %bb.0:
526 ; RV64I-NEXT: addi sp, sp, -16
527 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
528 ; RV64I-NEXT: call __floatsidf@plt
529 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
530 ; RV64I-NEXT: addi sp, sp, 16
531 ; RV64I-NEXT: ret
532 %1 = call double @llvm.experimental.constrained.sitofp.f64.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
533 ret double %1
534 }
535 declare double @llvm.experimental.constrained.sitofp.f64.i16(i16, metadata, metadata)
537 define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind strictfp {
538 ; CHECKIFD-LABEL: fcvt_d_wu_i16:
539 ; CHECKIFD: # %bb.0:
540 ; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
541 ; CHECKIFD-NEXT: ret
542 ;
543 ; RV32I-LABEL: fcvt_d_wu_i16:
544 ; RV32I: # %bb.0:
545 ; RV32I-NEXT: addi sp, sp, -16
546 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
547 ; RV32I-NEXT: call __floatunsidf@plt
548 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
549 ; RV32I-NEXT: addi sp, sp, 16
550 ; RV32I-NEXT: ret
551 ;
552 ; RV64I-LABEL: fcvt_d_wu_i16:
553 ; RV64I: # %bb.0:
554 ; RV64I-NEXT: addi sp, sp, -16
555 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
556 ; RV64I-NEXT: call __floatunsidf@plt
557 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
558 ; RV64I-NEXT: addi sp, sp, 16
559 ; RV64I-NEXT: ret
560 %1 = call double @llvm.experimental.constrained.uitofp.f64.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
561 ret double %1
562 }
563 declare double @llvm.experimental.constrained.uitofp.f64.i16(i16, metadata, metadata)
565 ; Make sure we select W version of addi on RV64.
566 define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, double* %1) nounwind {
567 ; RV32IFD-LABEL: fcvt_d_w_demanded_bits:
568 ; RV32IFD: # %bb.0:
569 ; RV32IFD-NEXT: addi a0, a0, 1
570 ; RV32IFD-NEXT: fcvt.d.w ft0, a0
571 ; RV32IFD-NEXT: fsd ft0, 0(a1)
572 ; RV32IFD-NEXT: ret
573 ;
574 ; RV64IFD-LABEL: fcvt_d_w_demanded_bits:
575 ; RV64IFD: # %bb.0:
576 ; RV64IFD-NEXT: addiw a0, a0, 1
577 ; RV64IFD-NEXT: fcvt.d.w ft0, a0
578 ; RV64IFD-NEXT: fsd ft0, 0(a1)
579 ; RV64IFD-NEXT: ret
580 ;
581 ; RV32I-LABEL: fcvt_d_w_demanded_bits:
582 ; RV32I: # %bb.0:
583 ; RV32I-NEXT: addi sp, sp, -16
584 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
585 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
586 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
587 ; RV32I-NEXT: mv s0, a1
588 ; RV32I-NEXT: addi s1, a0, 1
589 ; RV32I-NEXT: mv a0, s1
590 ; RV32I-NEXT: call __floatsidf@plt
591 ; RV32I-NEXT: sw a1, 4(s0)
592 ; RV32I-NEXT: sw a0, 0(s0)
593 ; RV32I-NEXT: mv a0, s1
594 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
595 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
596 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
597 ; RV32I-NEXT: addi sp, sp, 16
598 ; RV32I-NEXT: ret
599 ;
600 ; RV64I-LABEL: fcvt_d_w_demanded_bits:
601 ; RV64I: # %bb.0:
602 ; RV64I-NEXT: addi sp, sp, -32
603 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
604 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
605 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
606 ; RV64I-NEXT: mv s0, a1
607 ; RV64I-NEXT: addiw s1, a0, 1
608 ; RV64I-NEXT: mv a0, s1
609 ; RV64I-NEXT: call __floatsidf@plt
610 ; RV64I-NEXT: sd a0, 0(s0)
611 ; RV64I-NEXT: mv a0, s1
612 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
613 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
614 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
615 ; RV64I-NEXT: addi sp, sp, 32
616 ; RV64I-NEXT: ret
617 %3 = add i32 %0, 1
618 %4 = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
619 store double %4, double* %1, align 8
620 ret i32 %3
621 }
623 ; Make sure we select W version of addi on RV64.
624 define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, double* %1) nounwind {
625 ; RV32IFD-LABEL: fcvt_d_wu_demanded_bits:
626 ; RV32IFD: # %bb.0:
627 ; RV32IFD-NEXT: addi a0, a0, 1
628 ; RV32IFD-NEXT: fcvt.d.wu ft0, a0
629 ; RV32IFD-NEXT: fsd ft0, 0(a1)
630 ; RV32IFD-NEXT: ret
631 ;
632 ; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:
633 ; RV64IFD: # %bb.0:
634 ; RV64IFD-NEXT: addiw a0, a0, 1
635 ; RV64IFD-NEXT: fcvt.d.wu ft0, a0
636 ; RV64IFD-NEXT: fsd ft0, 0(a1)
637 ; RV64IFD-NEXT: ret
638 ;
639 ; RV32I-LABEL: fcvt_d_wu_demanded_bits:
640 ; RV32I: # %bb.0:
641 ; RV32I-NEXT: addi sp, sp, -16
642 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
643 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
644 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
645 ; RV32I-NEXT: mv s0, a1
646 ; RV32I-NEXT: addi s1, a0, 1
647 ; RV32I-NEXT: mv a0, s1
648 ; RV32I-NEXT: call __floatunsidf@plt
649 ; RV32I-NEXT: sw a1, 4(s0)
650 ; RV32I-NEXT: sw a0, 0(s0)
651 ; RV32I-NEXT: mv a0, s1
652 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
653 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
654 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
655 ; RV32I-NEXT: addi sp, sp, 16
656 ; RV32I-NEXT: ret
657 ;
658 ; RV64I-LABEL: fcvt_d_wu_demanded_bits:
659 ; RV64I: # %bb.0:
660 ; RV64I-NEXT: addi sp, sp, -32
661 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
662 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
663 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
664 ; RV64I-NEXT: mv s0, a1
665 ; RV64I-NEXT: addiw s1, a0, 1
666 ; RV64I-NEXT: mv a0, s1
667 ; RV64I-NEXT: call __floatunsidf@plt
668 ; RV64I-NEXT: sd a0, 0(s0)
669 ; RV64I-NEXT: mv a0, s1
670 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
671 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
672 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
673 ; RV64I-NEXT: addi sp, sp, 32
674 ; RV64I-NEXT: ret
675 %3 = add i32 %0, 1
676 %4 = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
677 store double %4, double* %1, align 8
678 ret i32 %3
679 }