| blob | e43376e6eeaac48bb8021a7cf0a796d8d7437b1e |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
3 ; RUN: -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
5 ; RUN: -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
7 define dso_local double @fld(double *%a) nounwind {
8 ; CHECKIFD-LABEL: fld:
9 ; CHECKIFD: # %bb.0:
10 ; CHECKIFD-NEXT: fld ft0, 0(a0)
11 ; CHECKIFD-NEXT: fld ft1, 24(a0)
12 ; CHECKIFD-NEXT: fadd.d fa0, ft0, ft1
13 ; CHECKIFD-NEXT: ret
14 %1 = load double, double* %a
15 %2 = getelementptr double, double* %a, i32 3
16 %3 = load double, double* %2
17 ; Use both loaded values in an FP op to ensure an fld is used, even for the
18 ; soft float ABI
19 %4 = fadd double %1, %3
20 ret double %4
21 }
23 define dso_local void @fsd(double *%a, double %b, double %c) nounwind {
24 ; CHECKIFD-LABEL: fsd:
25 ; CHECKIFD: # %bb.0:
26 ; CHECKIFD-NEXT: fadd.d ft0, fa0, fa1
27 ; CHECKIFD-NEXT: fsd ft0, 0(a0)
28 ; CHECKIFD-NEXT: fsd ft0, 64(a0)
29 ; CHECKIFD-NEXT: ret
30 ; Use %b and %c in an FP op to ensure floating point registers are used, even
31 ; for the soft float ABI
32 %1 = fadd double %b, %c
33 store double %1, double* %a
34 %2 = getelementptr double, double* %a, i32 8
35 store double %1, double* %2
36 ret void
37 }
39 ; Check load and store to a global
40 @G = dso_local global double 0.0
42 define dso_local double @fld_fsd_global(double %a, double %b) nounwind {
43 ; CHECKIFD-LABEL: fld_fsd_global:
44 ; CHECKIFD: # %bb.0:
45 ; CHECKIFD-NEXT: fadd.d fa0, fa0, fa1
46 ; CHECKIFD-NEXT: lui a0, %hi(G)
47 ; CHECKIFD-NEXT: fld ft0, %lo(G)(a0)
48 ; CHECKIFD-NEXT: addi a1, a0, %lo(G)
49 ; CHECKIFD-NEXT: fsd fa0, %lo(G)(a0)
50 ; CHECKIFD-NEXT: fld ft0, 72(a1)
51 ; CHECKIFD-NEXT: fsd fa0, 72(a1)
52 ; CHECKIFD-NEXT: ret
53 ; Use %a and %b in an FP op to ensure floating point registers are used, even
54 ; for the soft float ABI
55 %1 = fadd double %a, %b
56 %2 = load volatile double, double* @G
57 store double %1, double* @G
58 %3 = getelementptr double, double* @G, i32 9
59 %4 = load volatile double, double* %3
60 store double %1, double* %3
61 ret double %1
62 }
64 ; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
65 define dso_local double @fld_fsd_constant(double %a) nounwind {
66 ; RV32IFD-LABEL: fld_fsd_constant:
67 ; RV32IFD: # %bb.0:
68 ; RV32IFD-NEXT: lui a0, 912092
69 ; RV32IFD-NEXT: fld ft0, -273(a0)
70 ; RV32IFD-NEXT: fadd.d fa0, fa0, ft0
71 ; RV32IFD-NEXT: fsd fa0, -273(a0)
72 ; RV32IFD-NEXT: ret
73 ;
74 ; RV64IFD-LABEL: fld_fsd_constant:
75 ; RV64IFD: # %bb.0:
76 ; RV64IFD-NEXT: lui a0, 228023
77 ; RV64IFD-NEXT: slli a0, a0, 2
78 ; RV64IFD-NEXT: fld ft0, -273(a0)
79 ; RV64IFD-NEXT: fadd.d fa0, fa0, ft0
80 ; RV64IFD-NEXT: fsd fa0, -273(a0)
81 ; RV64IFD-NEXT: ret
82 %1 = inttoptr i32 3735928559 to double*
83 %2 = load volatile double, double* %1
84 %3 = fadd double %a, %2
85 store double %3, double* %1
86 ret double %3
87 }
89 declare void @notdead(i8*)
91 define dso_local double @fld_stack(double %a) nounwind {
92 ; RV32IFD-LABEL: fld_stack:
93 ; RV32IFD: # %bb.0:
94 ; RV32IFD-NEXT: addi sp, sp, -32
95 ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
96 ; RV32IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
97 ; RV32IFD-NEXT: fmv.d fs0, fa0
98 ; RV32IFD-NEXT: addi a0, sp, 8
99 ; RV32IFD-NEXT: call notdead@plt
100 ; RV32IFD-NEXT: fld ft0, 8(sp)
101 ; RV32IFD-NEXT: fadd.d fa0, ft0, fs0
102 ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
103 ; RV32IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
104 ; RV32IFD-NEXT: addi sp, sp, 32
105 ; RV32IFD-NEXT: ret
106 ;
107 ; RV64IFD-LABEL: fld_stack:
108 ; RV64IFD: # %bb.0:
109 ; RV64IFD-NEXT: addi sp, sp, -32
110 ; RV64IFD-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
111 ; RV64IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
112 ; RV64IFD-NEXT: fmv.d fs0, fa0
113 ; RV64IFD-NEXT: addi a0, sp, 8
114 ; RV64IFD-NEXT: call notdead@plt
115 ; RV64IFD-NEXT: fld ft0, 8(sp)
116 ; RV64IFD-NEXT: fadd.d fa0, ft0, fs0
117 ; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
118 ; RV64IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
119 ; RV64IFD-NEXT: addi sp, sp, 32
120 ; RV64IFD-NEXT: ret
121 %1 = alloca double, align 8
122 %2 = bitcast double* %1 to i8*
123 call void @notdead(i8* %2)
124 %3 = load double, double* %1
125 %4 = fadd double %3, %a ; force load in to FPR64
126 ret double %4
127 }
129 define dso_local void @fsd_stack(double %a, double %b) nounwind {
130 ; RV32IFD-LABEL: fsd_stack:
131 ; RV32IFD: # %bb.0:
132 ; RV32IFD-NEXT: addi sp, sp, -16
133 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
134 ; RV32IFD-NEXT: fadd.d ft0, fa0, fa1
135 ; RV32IFD-NEXT: fsd ft0, 0(sp)
136 ; RV32IFD-NEXT: mv a0, sp
137 ; RV32IFD-NEXT: call notdead@plt
138 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
139 ; RV32IFD-NEXT: addi sp, sp, 16
140 ; RV32IFD-NEXT: ret
141 ;
142 ; RV64IFD-LABEL: fsd_stack:
143 ; RV64IFD: # %bb.0:
144 ; RV64IFD-NEXT: addi sp, sp, -16
145 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
146 ; RV64IFD-NEXT: fadd.d ft0, fa0, fa1
147 ; RV64IFD-NEXT: fsd ft0, 0(sp)
148 ; RV64IFD-NEXT: mv a0, sp
149 ; RV64IFD-NEXT: call notdead@plt
150 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
151 ; RV64IFD-NEXT: addi sp, sp, 16
152 ; RV64IFD-NEXT: ret
153 %1 = fadd double %a, %b ; force store from FPR64
154 %2 = alloca double, align 8
155 store double %1, double* %2
156 %3 = bitcast double* %2 to i8*
157 call void @notdead(i8* %3)
158 ret void
159 }
161 ; Test selection of store<ST4[%a], trunc to f32>, ..
162 define dso_local void @fsd_trunc(float* %a, double %b) nounwind noinline optnone {
163 ; CHECKIFD-LABEL: fsd_trunc:
164 ; CHECKIFD: # %bb.0:
165 ; CHECKIFD-NEXT: fcvt.s.d ft0, fa0
166 ; CHECKIFD-NEXT: fsw ft0, 0(a0)
167 ; CHECKIFD-NEXT: ret
168 %1 = fptrunc double %b to float
169 store float %1, float* %a, align 4
170 ret void
171 }