| blob | 7e2ed7a8bc3216cb13f9a98abe89bbd979947eee |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck %s --check-prefix=RV32I
4 ; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
5 ; RUN: | FileCheck %s --check-prefix=RV32ZBB
6 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
7 ; RUN: | FileCheck %s --check-prefix=RV32IBT
8 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
9 ; RUN: | FileCheck %s --check-prefix=RV64I
10 ; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
11 ; RUN: | FileCheck %s --check-prefix=RV64ZBB
12 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
13 ; RUN: | FileCheck %s --check-prefix=RV64IBT
15 declare i32 @llvm.abs.i32(i32, i1 immarg)
16 declare i64 @llvm.abs.i64(i64, i1 immarg)
18 define i32 @neg_abs32(i32 %x) {
19 ; RV32I-LABEL: neg_abs32:
20 ; RV32I: # %bb.0:
21 ; RV32I-NEXT: srai a1, a0, 31
22 ; RV32I-NEXT: xor a0, a0, a1
23 ; RV32I-NEXT: sub a0, a1, a0
24 ; RV32I-NEXT: ret
25 ;
26 ; RV32ZBB-LABEL: neg_abs32:
27 ; RV32ZBB: # %bb.0:
28 ; RV32ZBB-NEXT: neg a1, a0
29 ; RV32ZBB-NEXT: min a0, a0, a1
30 ; RV32ZBB-NEXT: ret
31 ;
32 ; RV32IBT-LABEL: neg_abs32:
33 ; RV32IBT: # %bb.0:
34 ; RV32IBT-NEXT: srai a1, a0, 31
35 ; RV32IBT-NEXT: xor a0, a0, a1
36 ; RV32IBT-NEXT: sub a0, a1, a0
37 ; RV32IBT-NEXT: ret
38 ;
39 ; RV64I-LABEL: neg_abs32:
40 ; RV64I: # %bb.0:
41 ; RV64I-NEXT: sraiw a1, a0, 31
42 ; RV64I-NEXT: xor a0, a0, a1
43 ; RV64I-NEXT: subw a0, a1, a0
44 ; RV64I-NEXT: ret
45 ;
46 ; RV64ZBB-LABEL: neg_abs32:
47 ; RV64ZBB: # %bb.0:
48 ; RV64ZBB-NEXT: sraiw a1, a0, 31
49 ; RV64ZBB-NEXT: xor a0, a0, a1
50 ; RV64ZBB-NEXT: subw a0, a1, a0
51 ; RV64ZBB-NEXT: ret
52 ;
53 ; RV64IBT-LABEL: neg_abs32:
54 ; RV64IBT: # %bb.0:
55 ; RV64IBT-NEXT: sraiw a1, a0, 31
56 ; RV64IBT-NEXT: xor a0, a0, a1
57 ; RV64IBT-NEXT: subw a0, a1, a0
58 ; RV64IBT-NEXT: ret
59 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
60 %neg = sub nsw i32 0, %abs
61 ret i32 %neg
62 }
64 define i32 @select_neg_abs32(i32 %x) {
65 ; RV32I-LABEL: select_neg_abs32:
66 ; RV32I: # %bb.0:
67 ; RV32I-NEXT: srai a1, a0, 31
68 ; RV32I-NEXT: xor a0, a0, a1
69 ; RV32I-NEXT: sub a0, a1, a0
70 ; RV32I-NEXT: ret
71 ;
72 ; RV32ZBB-LABEL: select_neg_abs32:
73 ; RV32ZBB: # %bb.0:
74 ; RV32ZBB-NEXT: neg a1, a0
75 ; RV32ZBB-NEXT: min a0, a0, a1
76 ; RV32ZBB-NEXT: ret
77 ;
78 ; RV32IBT-LABEL: select_neg_abs32:
79 ; RV32IBT: # %bb.0:
80 ; RV32IBT-NEXT: srai a1, a0, 31
81 ; RV32IBT-NEXT: xor a0, a0, a1
82 ; RV32IBT-NEXT: sub a0, a1, a0
83 ; RV32IBT-NEXT: ret
84 ;
85 ; RV64I-LABEL: select_neg_abs32:
86 ; RV64I: # %bb.0:
87 ; RV64I-NEXT: sraiw a1, a0, 31
88 ; RV64I-NEXT: xor a0, a0, a1
89 ; RV64I-NEXT: subw a0, a1, a0
90 ; RV64I-NEXT: ret
91 ;
92 ; RV64ZBB-LABEL: select_neg_abs32:
93 ; RV64ZBB: # %bb.0:
94 ; RV64ZBB-NEXT: sraiw a1, a0, 31
95 ; RV64ZBB-NEXT: xor a0, a0, a1
96 ; RV64ZBB-NEXT: subw a0, a1, a0
97 ; RV64ZBB-NEXT: ret
98 ;
99 ; RV64IBT-LABEL: select_neg_abs32:
100 ; RV64IBT: # %bb.0:
101 ; RV64IBT-NEXT: sraiw a1, a0, 31
102 ; RV64IBT-NEXT: xor a0, a0, a1
103 ; RV64IBT-NEXT: subw a0, a1, a0
104 ; RV64IBT-NEXT: ret
105 %1 = icmp slt i32 %x, 0
106 %2 = sub nsw i32 0, %x
107 %3 = select i1 %1, i32 %x, i32 %2
108 ret i32 %3
109 }
111 define i64 @neg_abs64(i64 %x) {
112 ; RV32I-LABEL: neg_abs64:
113 ; RV32I: # %bb.0:
114 ; RV32I-NEXT: srai a2, a1, 31
115 ; RV32I-NEXT: xor a0, a0, a2
116 ; RV32I-NEXT: sltu a3, a2, a0
117 ; RV32I-NEXT: xor a1, a1, a2
118 ; RV32I-NEXT: sub a1, a2, a1
119 ; RV32I-NEXT: sub a1, a1, a3
120 ; RV32I-NEXT: sub a0, a2, a0
121 ; RV32I-NEXT: ret
122 ;
123 ; RV32ZBB-LABEL: neg_abs64:
124 ; RV32ZBB: # %bb.0:
125 ; RV32ZBB-NEXT: srai a2, a1, 31
126 ; RV32ZBB-NEXT: xor a0, a0, a2
127 ; RV32ZBB-NEXT: sltu a3, a2, a0
128 ; RV32ZBB-NEXT: xor a1, a1, a2
129 ; RV32ZBB-NEXT: sub a1, a2, a1
130 ; RV32ZBB-NEXT: sub a1, a1, a3
131 ; RV32ZBB-NEXT: sub a0, a2, a0
132 ; RV32ZBB-NEXT: ret
133 ;
134 ; RV32IBT-LABEL: neg_abs64:
135 ; RV32IBT: # %bb.0:
136 ; RV32IBT-NEXT: srai a2, a1, 31
137 ; RV32IBT-NEXT: xor a0, a0, a2
138 ; RV32IBT-NEXT: sltu a3, a2, a0
139 ; RV32IBT-NEXT: xor a1, a1, a2
140 ; RV32IBT-NEXT: sub a1, a2, a1
141 ; RV32IBT-NEXT: sub a1, a1, a3
142 ; RV32IBT-NEXT: sub a0, a2, a0
143 ; RV32IBT-NEXT: ret
144 ;
145 ; RV64I-LABEL: neg_abs64:
146 ; RV64I: # %bb.0:
147 ; RV64I-NEXT: srai a1, a0, 63
148 ; RV64I-NEXT: xor a0, a0, a1
149 ; RV64I-NEXT: sub a0, a1, a0
150 ; RV64I-NEXT: ret
151 ;
152 ; RV64ZBB-LABEL: neg_abs64:
153 ; RV64ZBB: # %bb.0:
154 ; RV64ZBB-NEXT: neg a1, a0
155 ; RV64ZBB-NEXT: min a0, a0, a1
156 ; RV64ZBB-NEXT: ret
157 ;
158 ; RV64IBT-LABEL: neg_abs64:
159 ; RV64IBT: # %bb.0:
160 ; RV64IBT-NEXT: srai a1, a0, 63
161 ; RV64IBT-NEXT: xor a0, a0, a1
162 ; RV64IBT-NEXT: sub a0, a1, a0
163 ; RV64IBT-NEXT: ret
164 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
165 %neg = sub nsw i64 0, %abs
166 ret i64 %neg
167 }
169 define i64 @select_neg_abs64(i64 %x) {
170 ; RV32I-LABEL: select_neg_abs64:
171 ; RV32I: # %bb.0:
172 ; RV32I-NEXT: srai a2, a1, 31
173 ; RV32I-NEXT: xor a0, a0, a2
174 ; RV32I-NEXT: sltu a3, a2, a0
175 ; RV32I-NEXT: xor a1, a1, a2
176 ; RV32I-NEXT: sub a1, a2, a1
177 ; RV32I-NEXT: sub a1, a1, a3
178 ; RV32I-NEXT: sub a0, a2, a0
179 ; RV32I-NEXT: ret
180 ;
181 ; RV32ZBB-LABEL: select_neg_abs64:
182 ; RV32ZBB: # %bb.0:
183 ; RV32ZBB-NEXT: srai a2, a1, 31
184 ; RV32ZBB-NEXT: xor a0, a0, a2
185 ; RV32ZBB-NEXT: sltu a3, a2, a0
186 ; RV32ZBB-NEXT: xor a1, a1, a2
187 ; RV32ZBB-NEXT: sub a1, a2, a1
188 ; RV32ZBB-NEXT: sub a1, a1, a3
189 ; RV32ZBB-NEXT: sub a0, a2, a0
190 ; RV32ZBB-NEXT: ret
191 ;
192 ; RV32IBT-LABEL: select_neg_abs64:
193 ; RV32IBT: # %bb.0:
194 ; RV32IBT-NEXT: srai a2, a1, 31
195 ; RV32IBT-NEXT: xor a0, a0, a2
196 ; RV32IBT-NEXT: sltu a3, a2, a0
197 ; RV32IBT-NEXT: xor a1, a1, a2
198 ; RV32IBT-NEXT: sub a1, a2, a1
199 ; RV32IBT-NEXT: sub a1, a1, a3
200 ; RV32IBT-NEXT: sub a0, a2, a0
201 ; RV32IBT-NEXT: ret
202 ;
203 ; RV64I-LABEL: select_neg_abs64:
204 ; RV64I: # %bb.0:
205 ; RV64I-NEXT: srai a1, a0, 63
206 ; RV64I-NEXT: xor a0, a0, a1
207 ; RV64I-NEXT: sub a0, a1, a0
208 ; RV64I-NEXT: ret
209 ;
210 ; RV64ZBB-LABEL: select_neg_abs64:
211 ; RV64ZBB: # %bb.0:
212 ; RV64ZBB-NEXT: neg a1, a0
213 ; RV64ZBB-NEXT: min a0, a0, a1
214 ; RV64ZBB-NEXT: ret
215 ;
216 ; RV64IBT-LABEL: select_neg_abs64:
217 ; RV64IBT: # %bb.0:
218 ; RV64IBT-NEXT: srai a1, a0, 63
219 ; RV64IBT-NEXT: xor a0, a0, a1
220 ; RV64IBT-NEXT: sub a0, a1, a0
221 ; RV64IBT-NEXT: ret
222 %1 = icmp slt i64 %x, 0
223 %2 = sub nsw i64 0, %x
224 %3 = select i1 %1, i64 %x, i64 %2
225 ret i64 %3
226 }
228 define i32 @neg_abs32_multiuse(i32 %x, i32* %y) {
229 ; RV32I-LABEL: neg_abs32_multiuse:
230 ; RV32I: # %bb.0:
231 ; RV32I-NEXT: srai a2, a0, 31
232 ; RV32I-NEXT: xor a0, a0, a2
233 ; RV32I-NEXT: sub a2, a0, a2
234 ; RV32I-NEXT: neg a0, a2
235 ; RV32I-NEXT: sw a2, 0(a1)
236 ; RV32I-NEXT: ret
237 ;
238 ; RV32ZBB-LABEL: neg_abs32_multiuse:
239 ; RV32ZBB: # %bb.0:
240 ; RV32ZBB-NEXT: neg a2, a0
241 ; RV32ZBB-NEXT: max a2, a0, a2
242 ; RV32ZBB-NEXT: neg a0, a2
243 ; RV32ZBB-NEXT: sw a2, 0(a1)
244 ; RV32ZBB-NEXT: ret
245 ;
246 ; RV32IBT-LABEL: neg_abs32_multiuse:
247 ; RV32IBT: # %bb.0:
248 ; RV32IBT-NEXT: srai a2, a0, 31
249 ; RV32IBT-NEXT: xor a0, a0, a2
250 ; RV32IBT-NEXT: sub a2, a0, a2
251 ; RV32IBT-NEXT: neg a0, a2
252 ; RV32IBT-NEXT: sw a2, 0(a1)
253 ; RV32IBT-NEXT: ret
254 ;
255 ; RV64I-LABEL: neg_abs32_multiuse:
256 ; RV64I: # %bb.0:
257 ; RV64I-NEXT: sraiw a2, a0, 31
258 ; RV64I-NEXT: xor a0, a0, a2
259 ; RV64I-NEXT: subw a2, a0, a2
260 ; RV64I-NEXT: negw a0, a2
261 ; RV64I-NEXT: sw a2, 0(a1)
262 ; RV64I-NEXT: ret
263 ;
264 ; RV64ZBB-LABEL: neg_abs32_multiuse:
265 ; RV64ZBB: # %bb.0:
266 ; RV64ZBB-NEXT: sext.w a0, a0
267 ; RV64ZBB-NEXT: neg a2, a0
268 ; RV64ZBB-NEXT: max a2, a0, a2
269 ; RV64ZBB-NEXT: negw a0, a2
270 ; RV64ZBB-NEXT: sw a2, 0(a1)
271 ; RV64ZBB-NEXT: ret
272 ;
273 ; RV64IBT-LABEL: neg_abs32_multiuse:
274 ; RV64IBT: # %bb.0:
275 ; RV64IBT-NEXT: sraiw a2, a0, 31
276 ; RV64IBT-NEXT: xor a0, a0, a2
277 ; RV64IBT-NEXT: subw a2, a0, a2
278 ; RV64IBT-NEXT: negw a0, a2
279 ; RV64IBT-NEXT: sw a2, 0(a1)
280 ; RV64IBT-NEXT: ret
281 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
282 store i32 %abs, i32* %y
283 %neg = sub nsw i32 0, %abs
284 ret i32 %neg
285 }
287 define i64 @neg_abs64_multiuse(i64 %x, i64* %y) {
288 ; RV32I-LABEL: neg_abs64_multiuse:
289 ; RV32I: # %bb.0:
290 ; RV32I-NEXT: bgez a1, .LBB5_2
291 ; RV32I-NEXT: # %bb.1:
292 ; RV32I-NEXT: snez a3, a0
293 ; RV32I-NEXT: add a1, a1, a3
294 ; RV32I-NEXT: neg a1, a1
295 ; RV32I-NEXT: neg a0, a0
296 ; RV32I-NEXT: .LBB5_2:
297 ; RV32I-NEXT: sw a0, 0(a2)
298 ; RV32I-NEXT: snez a3, a0
299 ; RV32I-NEXT: add a3, a1, a3
300 ; RV32I-NEXT: neg a3, a3
301 ; RV32I-NEXT: neg a0, a0
302 ; RV32I-NEXT: sw a1, 4(a2)
303 ; RV32I-NEXT: mv a1, a3
304 ; RV32I-NEXT: ret
305 ;
306 ; RV32ZBB-LABEL: neg_abs64_multiuse:
307 ; RV32ZBB: # %bb.0:
308 ; RV32ZBB-NEXT: bgez a1, .LBB5_2
309 ; RV32ZBB-NEXT: # %bb.1:
310 ; RV32ZBB-NEXT: snez a3, a0
311 ; RV32ZBB-NEXT: add a1, a1, a3
312 ; RV32ZBB-NEXT: neg a1, a1
313 ; RV32ZBB-NEXT: neg a0, a0
314 ; RV32ZBB-NEXT: .LBB5_2:
315 ; RV32ZBB-NEXT: sw a0, 0(a2)
316 ; RV32ZBB-NEXT: snez a3, a0
317 ; RV32ZBB-NEXT: add a3, a1, a3
318 ; RV32ZBB-NEXT: neg a3, a3
319 ; RV32ZBB-NEXT: neg a0, a0
320 ; RV32ZBB-NEXT: sw a1, 4(a2)
321 ; RV32ZBB-NEXT: mv a1, a3
322 ; RV32ZBB-NEXT: ret
323 ;
324 ; RV32IBT-LABEL: neg_abs64_multiuse:
325 ; RV32IBT: # %bb.0:
326 ; RV32IBT-NEXT: snez a3, a0
327 ; RV32IBT-NEXT: add a3, a1, a3
328 ; RV32IBT-NEXT: neg a3, a3
329 ; RV32IBT-NEXT: slti a4, a1, 0
330 ; RV32IBT-NEXT: cmov a3, a4, a3, a1
331 ; RV32IBT-NEXT: neg a1, a0
332 ; RV32IBT-NEXT: cmov a0, a4, a1, a0
333 ; RV32IBT-NEXT: sw a0, 0(a2)
334 ; RV32IBT-NEXT: snez a1, a0
335 ; RV32IBT-NEXT: add a1, a3, a1
336 ; RV32IBT-NEXT: neg a1, a1
337 ; RV32IBT-NEXT: neg a0, a0
338 ; RV32IBT-NEXT: sw a3, 4(a2)
339 ; RV32IBT-NEXT: ret
340 ;
341 ; RV64I-LABEL: neg_abs64_multiuse:
342 ; RV64I: # %bb.0:
343 ; RV64I-NEXT: srai a2, a0, 63
344 ; RV64I-NEXT: xor a0, a0, a2
345 ; RV64I-NEXT: sub a2, a0, a2
346 ; RV64I-NEXT: neg a0, a2
347 ; RV64I-NEXT: sd a2, 0(a1)
348 ; RV64I-NEXT: ret
349 ;
350 ; RV64ZBB-LABEL: neg_abs64_multiuse:
351 ; RV64ZBB: # %bb.0:
352 ; RV64ZBB-NEXT: neg a2, a0
353 ; RV64ZBB-NEXT: max a2, a0, a2
354 ; RV64ZBB-NEXT: neg a0, a2
355 ; RV64ZBB-NEXT: sd a2, 0(a1)
356 ; RV64ZBB-NEXT: ret
357 ;
358 ; RV64IBT-LABEL: neg_abs64_multiuse:
359 ; RV64IBT: # %bb.0:
360 ; RV64IBT-NEXT: srai a2, a0, 63
361 ; RV64IBT-NEXT: xor a0, a0, a2
362 ; RV64IBT-NEXT: sub a2, a0, a2
363 ; RV64IBT-NEXT: neg a0, a2
364 ; RV64IBT-NEXT: sd a2, 0(a1)
365 ; RV64IBT-NEXT: ret
366 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
367 store i64 %abs, i64* %y
368 %neg = sub nsw i64 0, %abs
369 ret i64 %neg
370 }