| blob | 04572679aebcf23c885ae64f68fee70a01457d30 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv64 -mattr=+f,+m,+zfh,+experimental-zvfh \
3 ; RUN: -riscv-enable-subreg-liveness=false < %s | FileCheck %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+f,+m,+zfh,+experimental-zvfh < %s \
5 ; RUN: -riscv-enable-subreg-liveness=true| FileCheck %s --check-prefix=SUBREGLIVENESS
7 ; This testcase failed to compile after
8 ; c46aab01c002b7a04135b8b7f1f52d8c9ae23a58, which was reverted.
10 ; FIXME: The failure does not reproduce with -stop-before=greedy
11 ; output MIR with -start-before=greedy
13 define void @last_chance_recoloring_failure() {
14 ; CHECK-LABEL: last_chance_recoloring_failure:
15 ; CHECK: # %bb.0: # %entry
16 ; CHECK-NEXT: addi sp, sp, -32
17 ; CHECK-NEXT: .cfi_def_cfa_offset 32
18 ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
19 ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
20 ; CHECK-NEXT: .cfi_offset ra, -8
21 ; CHECK-NEXT: .cfi_offset s0, -16
22 ; CHECK-NEXT: csrr a0, vlenb
23 ; CHECK-NEXT: li a1, 24
24 ; CHECK-NEXT: mul a0, a0, a1
25 ; CHECK-NEXT: sub sp, sp, a0
26 ; CHECK-NEXT: li a0, 55
27 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
28 ; CHECK-NEXT: vloxseg2ei32.v v8, (a0), v8
29 ; CHECK-NEXT: csrr a0, vlenb
30 ; CHECK-NEXT: slli a0, a0, 3
31 ; CHECK-NEXT: add a0, sp, a0
32 ; CHECK-NEXT: addi a0, a0, 16
33 ; CHECK-NEXT: csrr a1, vlenb
34 ; CHECK-NEXT: slli a1, a1, 2
35 ; CHECK-NEXT: vs4r.v v8, (a0) # Unknown-size Folded Spill
36 ; CHECK-NEXT: add a0, a0, a1
37 ; CHECK-NEXT: vs4r.v v12, (a0) # Unknown-size Folded Spill
38 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
39 ; CHECK-NEXT: vmclr.m v0
40 ; CHECK-NEXT: li s0, 36
41 ; CHECK-NEXT: vsetvli zero, s0, e16, m4, tu, mu
42 ; CHECK-NEXT: vfwadd.vv v8, v8, v8, v0.t
43 ; CHECK-NEXT: csrr a0, vlenb
44 ; CHECK-NEXT: slli a0, a0, 4
45 ; CHECK-NEXT: add a0, sp, a0
46 ; CHECK-NEXT: addi a0, a0, 16
47 ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
48 ; CHECK-NEXT: call func@plt
49 ; CHECK-NEXT: li a0, 32
50 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
51 ; CHECK-NEXT: vrgather.vv v4, v8, v8, v0.t
52 ; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, mu
53 ; CHECK-NEXT: csrr a1, vlenb
54 ; CHECK-NEXT: slli a1, a1, 3
55 ; CHECK-NEXT: add a1, sp, a1
56 ; CHECK-NEXT: addi a1, a1, 16
57 ; CHECK-NEXT: csrr a2, vlenb
58 ; CHECK-NEXT: slli a2, a2, 2
59 ; CHECK-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload
60 ; CHECK-NEXT: add a1, a1, a2
61 ; CHECK-NEXT: vl4r.v v28, (a1) # Unknown-size Folded Reload
62 ; CHECK-NEXT: csrr a1, vlenb
63 ; CHECK-NEXT: slli a1, a1, 4
64 ; CHECK-NEXT: add a1, sp, a1
65 ; CHECK-NEXT: addi a1, a1, 16
66 ; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
67 ; CHECK-NEXT: vfwsub.wv v16, v8, v24
68 ; CHECK-NEXT: addi a1, sp, 16
69 ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
70 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
71 ; CHECK-NEXT: vssubu.vv v4, v4, v8, v0.t
72 ; CHECK-NEXT: vsetvli zero, s0, e32, m8, tu, mu
73 ; CHECK-NEXT: csrr a0, vlenb
74 ; CHECK-NEXT: slli a0, a0, 4
75 ; CHECK-NEXT: add a0, sp, a0
76 ; CHECK-NEXT: addi a0, a0, 16
77 ; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
78 ; CHECK-NEXT: addi a0, sp, 16
79 ; CHECK-NEXT: vl8re8.v v8, (a0) # Unknown-size Folded Reload
80 ; CHECK-NEXT: vfdiv.vv v8, v16, v8, v0.t
81 ; CHECK-NEXT: vse32.v v8, (a0)
82 ; CHECK-NEXT: csrr a0, vlenb
83 ; CHECK-NEXT: li a1, 24
84 ; CHECK-NEXT: mul a0, a0, a1
85 ; CHECK-NEXT: add sp, sp, a0
86 ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
87 ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
88 ; CHECK-NEXT: addi sp, sp, 32
89 ; CHECK-NEXT: ret
90 ;
91 ; SUBREGLIVENESS-LABEL: last_chance_recoloring_failure:
92 ; SUBREGLIVENESS: # %bb.0: # %entry
93 ; SUBREGLIVENESS-NEXT: addi sp, sp, -32
94 ; SUBREGLIVENESS-NEXT: .cfi_def_cfa_offset 32
95 ; SUBREGLIVENESS-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
96 ; SUBREGLIVENESS-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
97 ; SUBREGLIVENESS-NEXT: .cfi_offset ra, -8
98 ; SUBREGLIVENESS-NEXT: .cfi_offset s0, -16
99 ; SUBREGLIVENESS-NEXT: csrr a0, vlenb
100 ; SUBREGLIVENESS-NEXT: slli a0, a0, 4
101 ; SUBREGLIVENESS-NEXT: sub sp, sp, a0
102 ; SUBREGLIVENESS-NEXT: li a0, 55
103 ; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, ta, mu
104 ; SUBREGLIVENESS-NEXT: vloxseg2ei32.v v8, (a0), v8
105 ; SUBREGLIVENESS-NEXT: csrr a0, vlenb
106 ; SUBREGLIVENESS-NEXT: slli a0, a0, 3
107 ; SUBREGLIVENESS-NEXT: add a0, sp, a0
108 ; SUBREGLIVENESS-NEXT: addi a0, a0, 16
109 ; SUBREGLIVENESS-NEXT: csrr a1, vlenb
110 ; SUBREGLIVENESS-NEXT: slli a1, a1, 2
111 ; SUBREGLIVENESS-NEXT: vs4r.v v8, (a0) # Unknown-size Folded Spill
112 ; SUBREGLIVENESS-NEXT: add a0, a0, a1
113 ; SUBREGLIVENESS-NEXT: vs4r.v v12, (a0) # Unknown-size Folded Spill
114 ; SUBREGLIVENESS-NEXT: vsetvli a0, zero, e8, m2, ta, mu
115 ; SUBREGLIVENESS-NEXT: vmclr.m v0
116 ; SUBREGLIVENESS-NEXT: li s0, 36
117 ; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, tu, mu
118 ; SUBREGLIVENESS-NEXT: vfwadd.vv v8, v8, v8, v0.t
119 ; SUBREGLIVENESS-NEXT: addi a0, sp, 16
120 ; SUBREGLIVENESS-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
121 ; SUBREGLIVENESS-NEXT: call func@plt
122 ; SUBREGLIVENESS-NEXT: li a0, 32
123 ; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, tu, mu
124 ; SUBREGLIVENESS-NEXT: vrgather.vv v16, v8, v8, v0.t
125 ; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, mu
126 ; SUBREGLIVENESS-NEXT: csrr a1, vlenb
127 ; SUBREGLIVENESS-NEXT: slli a1, a1, 3
128 ; SUBREGLIVENESS-NEXT: add a1, sp, a1
129 ; SUBREGLIVENESS-NEXT: addi a1, a1, 16
130 ; SUBREGLIVENESS-NEXT: csrr a2, vlenb
131 ; SUBREGLIVENESS-NEXT: slli a2, a2, 2
132 ; SUBREGLIVENESS-NEXT: vl4r.v v20, (a1) # Unknown-size Folded Reload
133 ; SUBREGLIVENESS-NEXT: add a1, a1, a2
134 ; SUBREGLIVENESS-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload
135 ; SUBREGLIVENESS-NEXT: addi a1, sp, 16
136 ; SUBREGLIVENESS-NEXT: vl8re8.v v24, (a1) # Unknown-size Folded Reload
137 ; SUBREGLIVENESS-NEXT: vfwsub.wv v8, v24, v20
138 ; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, tu, mu
139 ; SUBREGLIVENESS-NEXT: vssubu.vv v16, v16, v8, v0.t
140 ; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e32, m8, tu, mu
141 ; SUBREGLIVENESS-NEXT: vfdiv.vv v8, v24, v8, v0.t
142 ; SUBREGLIVENESS-NEXT: vse32.v v8, (a0)
143 ; SUBREGLIVENESS-NEXT: csrr a0, vlenb
144 ; SUBREGLIVENESS-NEXT: slli a0, a0, 4
145 ; SUBREGLIVENESS-NEXT: add sp, sp, a0
146 ; SUBREGLIVENESS-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
147 ; SUBREGLIVENESS-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
148 ; SUBREGLIVENESS-NEXT: addi sp, sp, 32
149 ; SUBREGLIVENESS-NEXT: ret
150 entry:
151 %i = call { <vscale x 16 x half>, <vscale x 16 x half>} @llvm.riscv.vloxseg2.nxv16f16.nxv16i32.i64( <vscale x 16 x half> undef, <vscale x 16 x half> undef, half* nonnull poison, <vscale x 16 x i32> poison, i64 55)
152 %i1 = extractvalue { <vscale x 16 x half>, <vscale x 16 x half> } %i, 0
153 %i2 = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> poison, <vscale x 16 x half> poison, <vscale x 16 x i1> zeroinitializer, i64 36, i64 0)
154 call void @func()
155 %i3 = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> poison, <vscale x 16 x i16> poison, <vscale x 16 x i1> poison, i64 32, i64 0)
156 %i4 = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %i2, <vscale x 16 x half> %i1, i64 36)
157 %i5 = call <vscale x 16 x i16> @llvm.riscv.vssubu.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> %i3, <vscale x 16 x i16> %i3, <vscale x 16 x i16> poison, <vscale x 16 x i1> poison, i64 32, i64 0)
158 %i6 = call <vscale x 16 x float> @llvm.riscv.vfdiv.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> %i4, <vscale x 16 x float> %i2, <vscale x 16 x float> poison, <vscale x 16 x i1> poison, i64 36, i64 0)
159 call void @llvm.riscv.vse.nxv16f32.i64(<vscale x 16 x float> %i6, <vscale x 16 x float>* nonnull poison, i64 36)
160 ret void
161 }
163 declare void @func()
164 declare { <vscale x 16 x half>, <vscale x 16 x half>} @llvm.riscv.vloxseg2.nxv16f16.nxv16i32.i64( <vscale x 16 x half>, <vscale x 16 x half>, half* nocapture, <vscale x 16 x i32>, i64)
165 declare <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64, i64 immarg)
166 declare <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i1>, i64, i64 immarg)
167 declare <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x half>, i64)
168 declare <vscale x 16 x i16> @llvm.riscv.vssubu.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i1>, i64, i64 immarg)
169 declare <vscale x 16 x float> @llvm.riscv.vfdiv.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg)
170 declare void @llvm.riscv.vse.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>* nocapture, i64) #3