| blob | 47c904108126ec4c0c7bc42d9cf4d9e067e032c6 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
3 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
4 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbNOZbt
5 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbNOZbt
6 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt
7 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt
9 declare i4 @llvm.sadd.sat.i4(i4, i4)
10 declare i8 @llvm.sadd.sat.i8(i8, i8)
11 declare i16 @llvm.sadd.sat.i16(i16, i16)
12 declare i32 @llvm.sadd.sat.i32(i32, i32)
13 declare i64 @llvm.sadd.sat.i64(i64, i64)
15 define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
16 ; RV32I-LABEL: func32:
17 ; RV32I: # %bb.0:
18 ; RV32I-NEXT: mv a3, a0
19 ; RV32I-NEXT: mul a1, a1, a2
20 ; RV32I-NEXT: add a0, a0, a1
21 ; RV32I-NEXT: slt a2, a0, a3
22 ; RV32I-NEXT: slti a1, a1, 0
23 ; RV32I-NEXT: beq a1, a2, .LBB0_2
24 ; RV32I-NEXT: # %bb.1:
25 ; RV32I-NEXT: srai a0, a0, 31
26 ; RV32I-NEXT: lui a1, 524288
27 ; RV32I-NEXT: xor a0, a0, a1
28 ; RV32I-NEXT: .LBB0_2:
29 ; RV32I-NEXT: ret
30 ;
31 ; RV64I-LABEL: func32:
32 ; RV64I: # %bb.0:
33 ; RV64I-NEXT: sext.w a0, a0
34 ; RV64I-NEXT: mulw a1, a1, a2
35 ; RV64I-NEXT: add a0, a0, a1
36 ; RV64I-NEXT: lui a1, 524288
37 ; RV64I-NEXT: addiw a2, a1, -1
38 ; RV64I-NEXT: bge a0, a2, .LBB0_3
39 ; RV64I-NEXT: # %bb.1:
40 ; RV64I-NEXT: bge a1, a0, .LBB0_4
41 ; RV64I-NEXT: .LBB0_2:
42 ; RV64I-NEXT: ret
43 ; RV64I-NEXT: .LBB0_3:
44 ; RV64I-NEXT: mv a0, a2
45 ; RV64I-NEXT: blt a1, a0, .LBB0_2
46 ; RV64I-NEXT: .LBB0_4:
47 ; RV64I-NEXT: lui a0, 524288
48 ; RV64I-NEXT: ret
49 ;
50 ; RV32IZbbNOZbt-LABEL: func32:
51 ; RV32IZbbNOZbt: # %bb.0:
52 ; RV32IZbbNOZbt-NEXT: mv a3, a0
53 ; RV32IZbbNOZbt-NEXT: mul a1, a1, a2
54 ; RV32IZbbNOZbt-NEXT: add a0, a0, a1
55 ; RV32IZbbNOZbt-NEXT: slt a2, a0, a3
56 ; RV32IZbbNOZbt-NEXT: slti a1, a1, 0
57 ; RV32IZbbNOZbt-NEXT: beq a1, a2, .LBB0_2
58 ; RV32IZbbNOZbt-NEXT: # %bb.1:
59 ; RV32IZbbNOZbt-NEXT: srai a0, a0, 31
60 ; RV32IZbbNOZbt-NEXT: lui a1, 524288
61 ; RV32IZbbNOZbt-NEXT: xor a0, a0, a1
62 ; RV32IZbbNOZbt-NEXT: .LBB0_2:
63 ; RV32IZbbNOZbt-NEXT: ret
64 ;
65 ; RV64IZbb-LABEL: func32:
66 ; RV64IZbb: # %bb.0:
67 ; RV64IZbb-NEXT: sext.w a0, a0
68 ; RV64IZbb-NEXT: mulw a1, a1, a2
69 ; RV64IZbb-NEXT: add a0, a0, a1
70 ; RV64IZbb-NEXT: lui a1, 524288
71 ; RV64IZbb-NEXT: addiw a2, a1, -1
72 ; RV64IZbb-NEXT: min a0, a0, a2
73 ; RV64IZbb-NEXT: max a0, a0, a1
74 ; RV64IZbb-NEXT: ret
75 ;
76 ; RV32IZbbZbt-LABEL: func32:
77 ; RV32IZbbZbt: # %bb.0:
78 ; RV32IZbbZbt-NEXT: mul a1, a1, a2
79 ; RV32IZbbZbt-NEXT: add a2, a0, a1
80 ; RV32IZbbZbt-NEXT: slt a0, a2, a0
81 ; RV32IZbbZbt-NEXT: slti a1, a1, 0
82 ; RV32IZbbZbt-NEXT: xor a0, a1, a0
83 ; RV32IZbbZbt-NEXT: srai a1, a2, 31
84 ; RV32IZbbZbt-NEXT: lui a3, 524288
85 ; RV32IZbbZbt-NEXT: xor a1, a1, a3
86 ; RV32IZbbZbt-NEXT: cmov a0, a0, a1, a2
87 ; RV32IZbbZbt-NEXT: ret
88 %a = mul i32 %y, %z
89 %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)
90 ret i32 %tmp
91 }
93 define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
94 ; RV32I-LABEL: func64:
95 ; RV32I: # %bb.0:
96 ; RV32I-NEXT: mv a2, a1
97 ; RV32I-NEXT: mv a1, a0
98 ; RV32I-NEXT: add a3, a2, a5
99 ; RV32I-NEXT: add a0, a0, a4
100 ; RV32I-NEXT: sltu a1, a0, a1
101 ; RV32I-NEXT: add a1, a3, a1
102 ; RV32I-NEXT: xor a3, a2, a1
103 ; RV32I-NEXT: xor a2, a2, a5
104 ; RV32I-NEXT: not a2, a2
105 ; RV32I-NEXT: and a2, a2, a3
106 ; RV32I-NEXT: bgez a2, .LBB1_2
107 ; RV32I-NEXT: # %bb.1:
108 ; RV32I-NEXT: srai a0, a1, 31
109 ; RV32I-NEXT: lui a1, 524288
110 ; RV32I-NEXT: xor a1, a0, a1
111 ; RV32I-NEXT: .LBB1_2:
112 ; RV32I-NEXT: ret
113 ;
114 ; RV64I-LABEL: func64:
115 ; RV64I: # %bb.0:
116 ; RV64I-NEXT: mv a1, a0
117 ; RV64I-NEXT: add a0, a0, a2
118 ; RV64I-NEXT: slt a1, a0, a1
119 ; RV64I-NEXT: slti a2, a2, 0
120 ; RV64I-NEXT: beq a2, a1, .LBB1_2
121 ; RV64I-NEXT: # %bb.1:
122 ; RV64I-NEXT: srai a0, a0, 63
123 ; RV64I-NEXT: li a1, -1
124 ; RV64I-NEXT: slli a1, a1, 63
125 ; RV64I-NEXT: xor a0, a0, a1
126 ; RV64I-NEXT: .LBB1_2:
127 ; RV64I-NEXT: ret
128 ;
129 ; RV32IZbbNOZbt-LABEL: func64:
130 ; RV32IZbbNOZbt: # %bb.0:
131 ; RV32IZbbNOZbt-NEXT: mv a2, a1
132 ; RV32IZbbNOZbt-NEXT: mv a1, a0
133 ; RV32IZbbNOZbt-NEXT: add a3, a2, a5
134 ; RV32IZbbNOZbt-NEXT: add a0, a0, a4
135 ; RV32IZbbNOZbt-NEXT: sltu a1, a0, a1
136 ; RV32IZbbNOZbt-NEXT: add a1, a3, a1
137 ; RV32IZbbNOZbt-NEXT: xor a3, a2, a1
138 ; RV32IZbbNOZbt-NEXT: xor a2, a2, a5
139 ; RV32IZbbNOZbt-NEXT: andn a2, a3, a2
140 ; RV32IZbbNOZbt-NEXT: bgez a2, .LBB1_2
141 ; RV32IZbbNOZbt-NEXT: # %bb.1:
142 ; RV32IZbbNOZbt-NEXT: srai a0, a1, 31
143 ; RV32IZbbNOZbt-NEXT: lui a1, 524288
144 ; RV32IZbbNOZbt-NEXT: xor a1, a0, a1
145 ; RV32IZbbNOZbt-NEXT: .LBB1_2:
146 ; RV32IZbbNOZbt-NEXT: ret
147 ;
148 ; RV64IZbbNOZbt-LABEL: func64:
149 ; RV64IZbbNOZbt: # %bb.0:
150 ; RV64IZbbNOZbt-NEXT: mv a1, a0
151 ; RV64IZbbNOZbt-NEXT: add a0, a0, a2
152 ; RV64IZbbNOZbt-NEXT: slt a1, a0, a1
153 ; RV64IZbbNOZbt-NEXT: slti a2, a2, 0
154 ; RV64IZbbNOZbt-NEXT: beq a2, a1, .LBB1_2
155 ; RV64IZbbNOZbt-NEXT: # %bb.1:
156 ; RV64IZbbNOZbt-NEXT: srai a0, a0, 63
157 ; RV64IZbbNOZbt-NEXT: li a1, -1
158 ; RV64IZbbNOZbt-NEXT: slli a1, a1, 63
159 ; RV64IZbbNOZbt-NEXT: xor a0, a0, a1
160 ; RV64IZbbNOZbt-NEXT: .LBB1_2:
161 ; RV64IZbbNOZbt-NEXT: ret
162 ;
163 ; RV32IZbbZbt-LABEL: func64:
164 ; RV32IZbbZbt: # %bb.0:
165 ; RV32IZbbZbt-NEXT: add a2, a1, a5
166 ; RV32IZbbZbt-NEXT: add a3, a0, a4
167 ; RV32IZbbZbt-NEXT: sltu a0, a3, a0
168 ; RV32IZbbZbt-NEXT: add a0, a2, a0
169 ; RV32IZbbZbt-NEXT: srai a2, a0, 31
170 ; RV32IZbbZbt-NEXT: lui a4, 524288
171 ; RV32IZbbZbt-NEXT: xor a4, a2, a4
172 ; RV32IZbbZbt-NEXT: xor a6, a1, a0
173 ; RV32IZbbZbt-NEXT: xor a1, a1, a5
174 ; RV32IZbbZbt-NEXT: andn a1, a6, a1
175 ; RV32IZbbZbt-NEXT: slti a5, a1, 0
176 ; RV32IZbbZbt-NEXT: cmov a1, a5, a4, a0
177 ; RV32IZbbZbt-NEXT: cmov a0, a5, a2, a3
178 ; RV32IZbbZbt-NEXT: ret
179 ;
180 ; RV64IZbbZbt-LABEL: func64:
181 ; RV64IZbbZbt: # %bb.0:
182 ; RV64IZbbZbt-NEXT: add a1, a0, a2
183 ; RV64IZbbZbt-NEXT: slt a0, a1, a0
184 ; RV64IZbbZbt-NEXT: slti a2, a2, 0
185 ; RV64IZbbZbt-NEXT: xor a0, a2, a0
186 ; RV64IZbbZbt-NEXT: srai a2, a1, 63
187 ; RV64IZbbZbt-NEXT: li a3, -1
188 ; RV64IZbbZbt-NEXT: slli a3, a3, 63
189 ; RV64IZbbZbt-NEXT: xor a2, a2, a3
190 ; RV64IZbbZbt-NEXT: cmov a0, a0, a2, a1
191 ; RV64IZbbZbt-NEXT: ret
192 %a = mul i64 %y, %z
193 %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
194 ret i64 %tmp
195 }
197 define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
198 ; RV32I-LABEL: func16:
199 ; RV32I: # %bb.0:
200 ; RV32I-NEXT: slli a0, a0, 16
201 ; RV32I-NEXT: srai a0, a0, 16
202 ; RV32I-NEXT: mul a1, a1, a2
203 ; RV32I-NEXT: slli a1, a1, 16
204 ; RV32I-NEXT: srai a1, a1, 16
205 ; RV32I-NEXT: add a0, a0, a1
206 ; RV32I-NEXT: lui a1, 8
207 ; RV32I-NEXT: addi a1, a1, -1
208 ; RV32I-NEXT: bge a0, a1, .LBB2_3
209 ; RV32I-NEXT: # %bb.1:
210 ; RV32I-NEXT: lui a1, 1048568
211 ; RV32I-NEXT: bge a1, a0, .LBB2_4
212 ; RV32I-NEXT: .LBB2_2:
213 ; RV32I-NEXT: ret
214 ; RV32I-NEXT: .LBB2_3:
215 ; RV32I-NEXT: mv a0, a1
216 ; RV32I-NEXT: lui a1, 1048568
217 ; RV32I-NEXT: blt a1, a0, .LBB2_2
218 ; RV32I-NEXT: .LBB2_4:
219 ; RV32I-NEXT: lui a0, 1048568
220 ; RV32I-NEXT: ret
221 ;
222 ; RV64I-LABEL: func16:
223 ; RV64I: # %bb.0:
224 ; RV64I-NEXT: slli a0, a0, 48
225 ; RV64I-NEXT: srai a0, a0, 48
226 ; RV64I-NEXT: mulw a1, a1, a2
227 ; RV64I-NEXT: slli a1, a1, 48
228 ; RV64I-NEXT: srai a1, a1, 48
229 ; RV64I-NEXT: add a0, a0, a1
230 ; RV64I-NEXT: lui a1, 8
231 ; RV64I-NEXT: addiw a1, a1, -1
232 ; RV64I-NEXT: bge a0, a1, .LBB2_3
233 ; RV64I-NEXT: # %bb.1:
234 ; RV64I-NEXT: lui a1, 1048568
235 ; RV64I-NEXT: bge a1, a0, .LBB2_4
236 ; RV64I-NEXT: .LBB2_2:
237 ; RV64I-NEXT: ret
238 ; RV64I-NEXT: .LBB2_3:
239 ; RV64I-NEXT: mv a0, a1
240 ; RV64I-NEXT: lui a1, 1048568
241 ; RV64I-NEXT: blt a1, a0, .LBB2_2
242 ; RV64I-NEXT: .LBB2_4:
243 ; RV64I-NEXT: lui a0, 1048568
244 ; RV64I-NEXT: ret
245 ;
246 ; RV32IZbb-LABEL: func16:
247 ; RV32IZbb: # %bb.0:
248 ; RV32IZbb-NEXT: sext.h a0, a0
249 ; RV32IZbb-NEXT: mul a1, a1, a2
250 ; RV32IZbb-NEXT: sext.h a1, a1
251 ; RV32IZbb-NEXT: add a0, a0, a1
252 ; RV32IZbb-NEXT: lui a1, 8
253 ; RV32IZbb-NEXT: addi a1, a1, -1
254 ; RV32IZbb-NEXT: min a0, a0, a1
255 ; RV32IZbb-NEXT: lui a1, 1048568
256 ; RV32IZbb-NEXT: max a0, a0, a1
257 ; RV32IZbb-NEXT: ret
258 ;
259 ; RV64IZbb-LABEL: func16:
260 ; RV64IZbb: # %bb.0:
261 ; RV64IZbb-NEXT: sext.h a0, a0
262 ; RV64IZbb-NEXT: mulw a1, a1, a2
263 ; RV64IZbb-NEXT: sext.h a1, a1
264 ; RV64IZbb-NEXT: add a0, a0, a1
265 ; RV64IZbb-NEXT: lui a1, 8
266 ; RV64IZbb-NEXT: addiw a1, a1, -1
267 ; RV64IZbb-NEXT: min a0, a0, a1
268 ; RV64IZbb-NEXT: lui a1, 1048568
269 ; RV64IZbb-NEXT: max a0, a0, a1
270 ; RV64IZbb-NEXT: ret
271 %a = mul i16 %y, %z
272 %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %a)
273 ret i16 %tmp
274 }
276 define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
277 ; RV32I-LABEL: func8:
278 ; RV32I: # %bb.0:
279 ; RV32I-NEXT: slli a0, a0, 24
280 ; RV32I-NEXT: srai a0, a0, 24
281 ; RV32I-NEXT: mul a1, a1, a2
282 ; RV32I-NEXT: slli a1, a1, 24
283 ; RV32I-NEXT: srai a1, a1, 24
284 ; RV32I-NEXT: add a0, a0, a1
285 ; RV32I-NEXT: li a1, 127
286 ; RV32I-NEXT: bge a0, a1, .LBB3_3
287 ; RV32I-NEXT: # %bb.1:
288 ; RV32I-NEXT: li a1, -128
289 ; RV32I-NEXT: bge a1, a0, .LBB3_4
290 ; RV32I-NEXT: .LBB3_2:
291 ; RV32I-NEXT: ret
292 ; RV32I-NEXT: .LBB3_3:
293 ; RV32I-NEXT: li a0, 127
294 ; RV32I-NEXT: li a1, -128
295 ; RV32I-NEXT: blt a1, a0, .LBB3_2
296 ; RV32I-NEXT: .LBB3_4:
297 ; RV32I-NEXT: li a0, -128
298 ; RV32I-NEXT: ret
299 ;
300 ; RV64I-LABEL: func8:
301 ; RV64I: # %bb.0:
302 ; RV64I-NEXT: slli a0, a0, 56
303 ; RV64I-NEXT: srai a0, a0, 56
304 ; RV64I-NEXT: mulw a1, a1, a2
305 ; RV64I-NEXT: slli a1, a1, 56
306 ; RV64I-NEXT: srai a1, a1, 56
307 ; RV64I-NEXT: add a0, a0, a1
308 ; RV64I-NEXT: li a1, 127
309 ; RV64I-NEXT: bge a0, a1, .LBB3_3
310 ; RV64I-NEXT: # %bb.1:
311 ; RV64I-NEXT: li a1, -128
312 ; RV64I-NEXT: bge a1, a0, .LBB3_4
313 ; RV64I-NEXT: .LBB3_2:
314 ; RV64I-NEXT: ret
315 ; RV64I-NEXT: .LBB3_3:
316 ; RV64I-NEXT: li a0, 127
317 ; RV64I-NEXT: li a1, -128
318 ; RV64I-NEXT: blt a1, a0, .LBB3_2
319 ; RV64I-NEXT: .LBB3_4:
320 ; RV64I-NEXT: li a0, -128
321 ; RV64I-NEXT: ret
322 ;
323 ; RV32IZbb-LABEL: func8:
324 ; RV32IZbb: # %bb.0:
325 ; RV32IZbb-NEXT: sext.b a0, a0
326 ; RV32IZbb-NEXT: mul a1, a1, a2
327 ; RV32IZbb-NEXT: sext.b a1, a1
328 ; RV32IZbb-NEXT: add a0, a0, a1
329 ; RV32IZbb-NEXT: li a1, 127
330 ; RV32IZbb-NEXT: min a0, a0, a1
331 ; RV32IZbb-NEXT: li a1, -128
332 ; RV32IZbb-NEXT: max a0, a0, a1
333 ; RV32IZbb-NEXT: ret
334 ;
335 ; RV64IZbb-LABEL: func8:
336 ; RV64IZbb: # %bb.0:
337 ; RV64IZbb-NEXT: sext.b a0, a0
338 ; RV64IZbb-NEXT: mulw a1, a1, a2
339 ; RV64IZbb-NEXT: sext.b a1, a1
340 ; RV64IZbb-NEXT: add a0, a0, a1
341 ; RV64IZbb-NEXT: li a1, 127
342 ; RV64IZbb-NEXT: min a0, a0, a1
343 ; RV64IZbb-NEXT: li a1, -128
344 ; RV64IZbb-NEXT: max a0, a0, a1
345 ; RV64IZbb-NEXT: ret
346 %a = mul i8 %y, %z
347 %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %a)
348 ret i8 %tmp
349 }
351 define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
352 ; RV32I-LABEL: func4:
353 ; RV32I: # %bb.0:
354 ; RV32I-NEXT: slli a0, a0, 28
355 ; RV32I-NEXT: srai a0, a0, 28
356 ; RV32I-NEXT: mul a1, a1, a2
357 ; RV32I-NEXT: slli a1, a1, 28
358 ; RV32I-NEXT: srai a1, a1, 28
359 ; RV32I-NEXT: add a0, a0, a1
360 ; RV32I-NEXT: li a1, 7
361 ; RV32I-NEXT: bge a0, a1, .LBB4_3
362 ; RV32I-NEXT: # %bb.1:
363 ; RV32I-NEXT: li a1, -8
364 ; RV32I-NEXT: bge a1, a0, .LBB4_4
365 ; RV32I-NEXT: .LBB4_2:
366 ; RV32I-NEXT: ret
367 ; RV32I-NEXT: .LBB4_3:
368 ; RV32I-NEXT: li a0, 7
369 ; RV32I-NEXT: li a1, -8
370 ; RV32I-NEXT: blt a1, a0, .LBB4_2
371 ; RV32I-NEXT: .LBB4_4:
372 ; RV32I-NEXT: li a0, -8
373 ; RV32I-NEXT: ret
374 ;
375 ; RV64I-LABEL: func4:
376 ; RV64I: # %bb.0:
377 ; RV64I-NEXT: slli a0, a0, 60
378 ; RV64I-NEXT: srai a0, a0, 60
379 ; RV64I-NEXT: mulw a1, a1, a2
380 ; RV64I-NEXT: slli a1, a1, 60
381 ; RV64I-NEXT: srai a1, a1, 60
382 ; RV64I-NEXT: add a0, a0, a1
383 ; RV64I-NEXT: li a1, 7
384 ; RV64I-NEXT: bge a0, a1, .LBB4_3
385 ; RV64I-NEXT: # %bb.1:
386 ; RV64I-NEXT: li a1, -8
387 ; RV64I-NEXT: bge a1, a0, .LBB4_4
388 ; RV64I-NEXT: .LBB4_2:
389 ; RV64I-NEXT: ret
390 ; RV64I-NEXT: .LBB4_3:
391 ; RV64I-NEXT: li a0, 7
392 ; RV64I-NEXT: li a1, -8
393 ; RV64I-NEXT: blt a1, a0, .LBB4_2
394 ; RV64I-NEXT: .LBB4_4:
395 ; RV64I-NEXT: li a0, -8
396 ; RV64I-NEXT: ret
397 ;
398 ; RV32IZbb-LABEL: func4:
399 ; RV32IZbb: # %bb.0:
400 ; RV32IZbb-NEXT: slli a0, a0, 28
401 ; RV32IZbb-NEXT: srai a0, a0, 28
402 ; RV32IZbb-NEXT: mul a1, a1, a2
403 ; RV32IZbb-NEXT: slli a1, a1, 28
404 ; RV32IZbb-NEXT: srai a1, a1, 28
405 ; RV32IZbb-NEXT: add a0, a0, a1
406 ; RV32IZbb-NEXT: li a1, 7
407 ; RV32IZbb-NEXT: min a0, a0, a1
408 ; RV32IZbb-NEXT: li a1, -8
409 ; RV32IZbb-NEXT: max a0, a0, a1
410 ; RV32IZbb-NEXT: ret
411 ;
412 ; RV64IZbb-LABEL: func4:
413 ; RV64IZbb: # %bb.0:
414 ; RV64IZbb-NEXT: slli a0, a0, 60
415 ; RV64IZbb-NEXT: srai a0, a0, 60
416 ; RV64IZbb-NEXT: mulw a1, a1, a2
417 ; RV64IZbb-NEXT: slli a1, a1, 60
418 ; RV64IZbb-NEXT: srai a1, a1, 60
419 ; RV64IZbb-NEXT: add a0, a0, a1
420 ; RV64IZbb-NEXT: li a1, 7
421 ; RV64IZbb-NEXT: min a0, a0, a1
422 ; RV64IZbb-NEXT: li a1, -8
423 ; RV64IZbb-NEXT: max a0, a0, a1
424 ; RV64IZbb-NEXT: ret
425 %a = mul i4 %y, %z
426 %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %a)
427 ret i4 %tmp
428 }