| blob | 3d5e8529ef35c5f8cc4de8e4d7a22b3f525624b4 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck %s -check-prefix=RV32I
4 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5 ; RUN: | FileCheck %s -check-prefix=RV64I
7 ; Basic shift support is tested as part of ALU.ll. This file ensures that
8 ; shifts which may not be supported natively are lowered properly.
10 declare i64 @llvm.fshr.i64(i64, i64, i64)
11 declare i128 @llvm.fshr.i128(i128, i128, i128)
13 define i64 @lshr64(i64 %a, i64 %b) nounwind {
14 ; RV32I-LABEL: lshr64:
15 ; RV32I: # %bb.0:
16 ; RV32I-NEXT: addi a3, a2, -32
17 ; RV32I-NEXT: bltz a3, .LBB0_2
18 ; RV32I-NEXT: # %bb.1:
19 ; RV32I-NEXT: srl a0, a1, a3
20 ; RV32I-NEXT: li a1, 0
21 ; RV32I-NEXT: ret
22 ; RV32I-NEXT: .LBB0_2:
23 ; RV32I-NEXT: srl a0, a0, a2
24 ; RV32I-NEXT: xori a3, a2, 31
25 ; RV32I-NEXT: slli a4, a1, 1
26 ; RV32I-NEXT: sll a3, a4, a3
27 ; RV32I-NEXT: or a0, a0, a3
28 ; RV32I-NEXT: srl a1, a1, a2
29 ; RV32I-NEXT: ret
30 ;
31 ; RV64I-LABEL: lshr64:
32 ; RV64I: # %bb.0:
33 ; RV64I-NEXT: srl a0, a0, a1
34 ; RV64I-NEXT: ret
35 %1 = lshr i64 %a, %b
36 ret i64 %1
37 }
39 define i64 @lshr64_minsize(i64 %a, i64 %b) minsize nounwind {
40 ; RV32I-LABEL: lshr64_minsize:
41 ; RV32I: # %bb.0:
42 ; RV32I-NEXT: addi sp, sp, -16
43 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
44 ; RV32I-NEXT: call __lshrdi3@plt
45 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
46 ; RV32I-NEXT: addi sp, sp, 16
47 ; RV32I-NEXT: ret
48 ;
49 ; RV64I-LABEL: lshr64_minsize:
50 ; RV64I: # %bb.0:
51 ; RV64I-NEXT: srl a0, a0, a1
52 ; RV64I-NEXT: ret
53 %1 = lshr i64 %a, %b
54 ret i64 %1
55 }
57 define i64 @ashr64(i64 %a, i64 %b) nounwind {
58 ; RV32I-LABEL: ashr64:
59 ; RV32I: # %bb.0:
60 ; RV32I-NEXT: addi a3, a2, -32
61 ; RV32I-NEXT: bltz a3, .LBB2_2
62 ; RV32I-NEXT: # %bb.1:
63 ; RV32I-NEXT: sra a0, a1, a3
64 ; RV32I-NEXT: srai a1, a1, 31
65 ; RV32I-NEXT: ret
66 ; RV32I-NEXT: .LBB2_2:
67 ; RV32I-NEXT: srl a0, a0, a2
68 ; RV32I-NEXT: xori a3, a2, 31
69 ; RV32I-NEXT: slli a4, a1, 1
70 ; RV32I-NEXT: sll a3, a4, a3
71 ; RV32I-NEXT: or a0, a0, a3
72 ; RV32I-NEXT: sra a1, a1, a2
73 ; RV32I-NEXT: ret
74 ;
75 ; RV64I-LABEL: ashr64:
76 ; RV64I: # %bb.0:
77 ; RV64I-NEXT: sra a0, a0, a1
78 ; RV64I-NEXT: ret
79 %1 = ashr i64 %a, %b
80 ret i64 %1
81 }
83 define i64 @ashr64_minsize(i64 %a, i64 %b) minsize nounwind {
84 ; RV32I-LABEL: ashr64_minsize:
85 ; RV32I: # %bb.0:
86 ; RV32I-NEXT: addi sp, sp, -16
87 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
88 ; RV32I-NEXT: call __ashrdi3@plt
89 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
90 ; RV32I-NEXT: addi sp, sp, 16
91 ; RV32I-NEXT: ret
92 ;
93 ; RV64I-LABEL: ashr64_minsize:
94 ; RV64I: # %bb.0:
95 ; RV64I-NEXT: sra a0, a0, a1
96 ; RV64I-NEXT: ret
97 %1 = ashr i64 %a, %b
98 ret i64 %1
99 }
101 define i64 @shl64(i64 %a, i64 %b) nounwind {
102 ; RV32I-LABEL: shl64:
103 ; RV32I: # %bb.0:
104 ; RV32I-NEXT: addi a3, a2, -32
105 ; RV32I-NEXT: bltz a3, .LBB4_2
106 ; RV32I-NEXT: # %bb.1:
107 ; RV32I-NEXT: sll a1, a0, a3
108 ; RV32I-NEXT: li a0, 0
109 ; RV32I-NEXT: ret
110 ; RV32I-NEXT: .LBB4_2:
111 ; RV32I-NEXT: sll a1, a1, a2
112 ; RV32I-NEXT: xori a3, a2, 31
113 ; RV32I-NEXT: srli a4, a0, 1
114 ; RV32I-NEXT: srl a3, a4, a3
115 ; RV32I-NEXT: or a1, a1, a3
116 ; RV32I-NEXT: sll a0, a0, a2
117 ; RV32I-NEXT: ret
118 ;
119 ; RV64I-LABEL: shl64:
120 ; RV64I: # %bb.0:
121 ; RV64I-NEXT: sll a0, a0, a1
122 ; RV64I-NEXT: ret
123 %1 = shl i64 %a, %b
124 ret i64 %1
125 }
127 define i64 @shl64_minsize(i64 %a, i64 %b) minsize nounwind {
128 ; RV32I-LABEL: shl64_minsize:
129 ; RV32I: # %bb.0:
130 ; RV32I-NEXT: addi sp, sp, -16
131 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
132 ; RV32I-NEXT: call __ashldi3@plt
133 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
134 ; RV32I-NEXT: addi sp, sp, 16
135 ; RV32I-NEXT: ret
136 ;
137 ; RV64I-LABEL: shl64_minsize:
138 ; RV64I: # %bb.0:
139 ; RV64I-NEXT: sll a0, a0, a1
140 ; RV64I-NEXT: ret
141 %1 = shl i64 %a, %b
142 ret i64 %1
143 }
145 define i128 @lshr128(i128 %a, i128 %b) nounwind {
146 ; RV32I-LABEL: lshr128:
147 ; RV32I: # %bb.0:
148 ; RV32I-NEXT: lw a2, 0(a2)
149 ; RV32I-NEXT: lw a5, 8(a1)
150 ; RV32I-NEXT: lw a4, 12(a1)
151 ; RV32I-NEXT: neg a6, a2
152 ; RV32I-NEXT: li a3, 64
153 ; RV32I-NEXT: li a7, 32
154 ; RV32I-NEXT: sub t1, a7, a2
155 ; RV32I-NEXT: sll t0, a5, a6
156 ; RV32I-NEXT: bltz t1, .LBB6_2
157 ; RV32I-NEXT: # %bb.1:
158 ; RV32I-NEXT: mv t2, t0
159 ; RV32I-NEXT: j .LBB6_3
160 ; RV32I-NEXT: .LBB6_2:
161 ; RV32I-NEXT: sll a6, a4, a6
162 ; RV32I-NEXT: sub a7, a3, a2
163 ; RV32I-NEXT: xori a7, a7, 31
164 ; RV32I-NEXT: srli t2, a5, 1
165 ; RV32I-NEXT: srl a7, t2, a7
166 ; RV32I-NEXT: or t2, a6, a7
167 ; RV32I-NEXT: .LBB6_3:
168 ; RV32I-NEXT: lw t5, 4(a1)
169 ; RV32I-NEXT: addi a6, a2, -32
170 ; RV32I-NEXT: bgez a6, .LBB6_5
171 ; RV32I-NEXT: # %bb.4:
172 ; RV32I-NEXT: srl a7, t5, a2
173 ; RV32I-NEXT: or t2, t2, a7
174 ; RV32I-NEXT: .LBB6_5:
175 ; RV32I-NEXT: addi t4, a2, -96
176 ; RV32I-NEXT: addi t3, a2, -64
177 ; RV32I-NEXT: bltz t4, .LBB6_7
178 ; RV32I-NEXT: # %bb.6:
179 ; RV32I-NEXT: li a7, 0
180 ; RV32I-NEXT: bgeu a2, a3, .LBB6_8
181 ; RV32I-NEXT: j .LBB6_9
182 ; RV32I-NEXT: .LBB6_7:
183 ; RV32I-NEXT: srl a7, a4, t3
184 ; RV32I-NEXT: bltu a2, a3, .LBB6_9
185 ; RV32I-NEXT: .LBB6_8:
186 ; RV32I-NEXT: mv t2, a7
187 ; RV32I-NEXT: .LBB6_9:
188 ; RV32I-NEXT: mv a7, t5
189 ; RV32I-NEXT: beqz a2, .LBB6_11
190 ; RV32I-NEXT: # %bb.10:
191 ; RV32I-NEXT: mv a7, t2
192 ; RV32I-NEXT: .LBB6_11:
193 ; RV32I-NEXT: lw a1, 0(a1)
194 ; RV32I-NEXT: xori t2, a2, 31
195 ; RV32I-NEXT: bltz a6, .LBB6_13
196 ; RV32I-NEXT: # %bb.12:
197 ; RV32I-NEXT: srl t5, t5, a6
198 ; RV32I-NEXT: bltz t1, .LBB6_14
199 ; RV32I-NEXT: j .LBB6_15
200 ; RV32I-NEXT: .LBB6_13:
201 ; RV32I-NEXT: srl t6, a1, a2
202 ; RV32I-NEXT: slli t5, t5, 1
203 ; RV32I-NEXT: sll t5, t5, t2
204 ; RV32I-NEXT: or t5, t6, t5
205 ; RV32I-NEXT: bgez t1, .LBB6_15
206 ; RV32I-NEXT: .LBB6_14:
207 ; RV32I-NEXT: or t5, t5, t0
208 ; RV32I-NEXT: .LBB6_15:
209 ; RV32I-NEXT: slli t0, a4, 1
210 ; RV32I-NEXT: bltz t4, .LBB6_17
211 ; RV32I-NEXT: # %bb.16:
212 ; RV32I-NEXT: srl t1, a4, t4
213 ; RV32I-NEXT: bgeu a2, a3, .LBB6_18
214 ; RV32I-NEXT: j .LBB6_19
215 ; RV32I-NEXT: .LBB6_17:
216 ; RV32I-NEXT: srl t1, a5, t3
217 ; RV32I-NEXT: xori t3, t3, 31
218 ; RV32I-NEXT: sll t3, t0, t3
219 ; RV32I-NEXT: or t1, t1, t3
220 ; RV32I-NEXT: bltu a2, a3, .LBB6_19
221 ; RV32I-NEXT: .LBB6_18:
222 ; RV32I-NEXT: mv t5, t1
223 ; RV32I-NEXT: .LBB6_19:
224 ; RV32I-NEXT: bnez a2, .LBB6_22
225 ; RV32I-NEXT: # %bb.20:
226 ; RV32I-NEXT: bltz a6, .LBB6_23
227 ; RV32I-NEXT: .LBB6_21:
228 ; RV32I-NEXT: srl a5, a4, a6
229 ; RV32I-NEXT: bgeu a2, a3, .LBB6_24
230 ; RV32I-NEXT: j .LBB6_25
231 ; RV32I-NEXT: .LBB6_22:
232 ; RV32I-NEXT: mv a1, t5
233 ; RV32I-NEXT: bgez a6, .LBB6_21
234 ; RV32I-NEXT: .LBB6_23:
235 ; RV32I-NEXT: srl a5, a5, a2
236 ; RV32I-NEXT: sll t0, t0, t2
237 ; RV32I-NEXT: or a5, a5, t0
238 ; RV32I-NEXT: bltu a2, a3, .LBB6_25
239 ; RV32I-NEXT: .LBB6_24:
240 ; RV32I-NEXT: li a5, 0
241 ; RV32I-NEXT: .LBB6_25:
242 ; RV32I-NEXT: bltz a6, .LBB6_27
243 ; RV32I-NEXT: # %bb.26:
244 ; RV32I-NEXT: li a4, 0
245 ; RV32I-NEXT: bgeu a2, a3, .LBB6_28
246 ; RV32I-NEXT: j .LBB6_29
247 ; RV32I-NEXT: .LBB6_27:
248 ; RV32I-NEXT: srl a4, a4, a2
249 ; RV32I-NEXT: bltu a2, a3, .LBB6_29
250 ; RV32I-NEXT: .LBB6_28:
251 ; RV32I-NEXT: li a4, 0
252 ; RV32I-NEXT: .LBB6_29:
253 ; RV32I-NEXT: sw a4, 12(a0)
254 ; RV32I-NEXT: sw a5, 8(a0)
255 ; RV32I-NEXT: sw a1, 0(a0)
256 ; RV32I-NEXT: sw a7, 4(a0)
257 ; RV32I-NEXT: ret
258 ;
259 ; RV64I-LABEL: lshr128:
260 ; RV64I: # %bb.0:
261 ; RV64I-NEXT: addi a3, a2, -64
262 ; RV64I-NEXT: bltz a3, .LBB6_2
263 ; RV64I-NEXT: # %bb.1:
264 ; RV64I-NEXT: srl a0, a1, a3
265 ; RV64I-NEXT: li a1, 0
266 ; RV64I-NEXT: ret
267 ; RV64I-NEXT: .LBB6_2:
268 ; RV64I-NEXT: srl a0, a0, a2
269 ; RV64I-NEXT: xori a3, a2, 63
270 ; RV64I-NEXT: slli a4, a1, 1
271 ; RV64I-NEXT: sll a3, a4, a3
272 ; RV64I-NEXT: or a0, a0, a3
273 ; RV64I-NEXT: srl a1, a1, a2
274 ; RV64I-NEXT: ret
275 %1 = lshr i128 %a, %b
276 ret i128 %1
277 }
279 define i128 @ashr128(i128 %a, i128 %b) nounwind {
280 ; RV32I-LABEL: ashr128:
281 ; RV32I: # %bb.0:
282 ; RV32I-NEXT: addi sp, sp, -16
283 ; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
284 ; RV32I-NEXT: lw a2, 0(a2)
285 ; RV32I-NEXT: lw a5, 8(a1)
286 ; RV32I-NEXT: lw a4, 12(a1)
287 ; RV32I-NEXT: neg a6, a2
288 ; RV32I-NEXT: li a3, 64
289 ; RV32I-NEXT: li a7, 32
290 ; RV32I-NEXT: sub t2, a7, a2
291 ; RV32I-NEXT: sll t1, a5, a6
292 ; RV32I-NEXT: bltz t2, .LBB7_2
293 ; RV32I-NEXT: # %bb.1:
294 ; RV32I-NEXT: mv t4, t1
295 ; RV32I-NEXT: j .LBB7_3
296 ; RV32I-NEXT: .LBB7_2:
297 ; RV32I-NEXT: sll a6, a4, a6
298 ; RV32I-NEXT: sub a7, a3, a2
299 ; RV32I-NEXT: xori a7, a7, 31
300 ; RV32I-NEXT: srli t0, a5, 1
301 ; RV32I-NEXT: srl a7, t0, a7
302 ; RV32I-NEXT: or t4, a6, a7
303 ; RV32I-NEXT: .LBB7_3:
304 ; RV32I-NEXT: lw t6, 4(a1)
305 ; RV32I-NEXT: addi a6, a2, -32
306 ; RV32I-NEXT: bgez a6, .LBB7_5
307 ; RV32I-NEXT: # %bb.4:
308 ; RV32I-NEXT: srl a7, t6, a2
309 ; RV32I-NEXT: or t4, t4, a7
310 ; RV32I-NEXT: .LBB7_5:
311 ; RV32I-NEXT: addi t3, a2, -64
312 ; RV32I-NEXT: addi t5, a2, -96
313 ; RV32I-NEXT: srai a7, a4, 31
314 ; RV32I-NEXT: bltz t5, .LBB7_7
315 ; RV32I-NEXT: # %bb.6:
316 ; RV32I-NEXT: mv t0, a7
317 ; RV32I-NEXT: bgeu a2, a3, .LBB7_8
318 ; RV32I-NEXT: j .LBB7_9
319 ; RV32I-NEXT: .LBB7_7:
320 ; RV32I-NEXT: sra t0, a4, t3
321 ; RV32I-NEXT: bltu a2, a3, .LBB7_9
322 ; RV32I-NEXT: .LBB7_8:
323 ; RV32I-NEXT: mv t4, t0
324 ; RV32I-NEXT: .LBB7_9:
325 ; RV32I-NEXT: mv t0, t6
326 ; RV32I-NEXT: beqz a2, .LBB7_11
327 ; RV32I-NEXT: # %bb.10:
328 ; RV32I-NEXT: mv t0, t4
329 ; RV32I-NEXT: .LBB7_11:
330 ; RV32I-NEXT: lw a1, 0(a1)
331 ; RV32I-NEXT: xori t4, a2, 31
332 ; RV32I-NEXT: bltz a6, .LBB7_13
333 ; RV32I-NEXT: # %bb.12:
334 ; RV32I-NEXT: srl t6, t6, a6
335 ; RV32I-NEXT: bltz t2, .LBB7_14
336 ; RV32I-NEXT: j .LBB7_15
337 ; RV32I-NEXT: .LBB7_13:
338 ; RV32I-NEXT: srl s0, a1, a2
339 ; RV32I-NEXT: slli t6, t6, 1
340 ; RV32I-NEXT: sll t6, t6, t4
341 ; RV32I-NEXT: or t6, s0, t6
342 ; RV32I-NEXT: bgez t2, .LBB7_15
343 ; RV32I-NEXT: .LBB7_14:
344 ; RV32I-NEXT: or t6, t6, t1
345 ; RV32I-NEXT: .LBB7_15:
346 ; RV32I-NEXT: slli t1, a4, 1
347 ; RV32I-NEXT: bltz t5, .LBB7_17
348 ; RV32I-NEXT: # %bb.16:
349 ; RV32I-NEXT: sra t2, a4, t5
350 ; RV32I-NEXT: bgeu a2, a3, .LBB7_18
351 ; RV32I-NEXT: j .LBB7_19
352 ; RV32I-NEXT: .LBB7_17:
353 ; RV32I-NEXT: srl t2, a5, t3
354 ; RV32I-NEXT: xori t3, t3, 31
355 ; RV32I-NEXT: sll t3, t1, t3
356 ; RV32I-NEXT: or t2, t2, t3
357 ; RV32I-NEXT: bltu a2, a3, .LBB7_19
358 ; RV32I-NEXT: .LBB7_18:
359 ; RV32I-NEXT: mv t6, t2
360 ; RV32I-NEXT: .LBB7_19:
361 ; RV32I-NEXT: bnez a2, .LBB7_22
362 ; RV32I-NEXT: # %bb.20:
363 ; RV32I-NEXT: bltz a6, .LBB7_23
364 ; RV32I-NEXT: .LBB7_21:
365 ; RV32I-NEXT: sra a5, a4, a6
366 ; RV32I-NEXT: bgeu a2, a3, .LBB7_24
367 ; RV32I-NEXT: j .LBB7_25
368 ; RV32I-NEXT: .LBB7_22:
369 ; RV32I-NEXT: mv a1, t6
370 ; RV32I-NEXT: bgez a6, .LBB7_21
371 ; RV32I-NEXT: .LBB7_23:
372 ; RV32I-NEXT: srl a5, a5, a2
373 ; RV32I-NEXT: sll t1, t1, t4
374 ; RV32I-NEXT: or a5, a5, t1
375 ; RV32I-NEXT: bltu a2, a3, .LBB7_25
376 ; RV32I-NEXT: .LBB7_24:
377 ; RV32I-NEXT: mv a5, a7
378 ; RV32I-NEXT: .LBB7_25:
379 ; RV32I-NEXT: bltz a6, .LBB7_27
380 ; RV32I-NEXT: # %bb.26:
381 ; RV32I-NEXT: mv a4, a7
382 ; RV32I-NEXT: bgeu a2, a3, .LBB7_28
383 ; RV32I-NEXT: j .LBB7_29
384 ; RV32I-NEXT: .LBB7_27:
385 ; RV32I-NEXT: sra a4, a4, a2
386 ; RV32I-NEXT: bltu a2, a3, .LBB7_29
387 ; RV32I-NEXT: .LBB7_28:
388 ; RV32I-NEXT: mv a4, a7
389 ; RV32I-NEXT: .LBB7_29:
390 ; RV32I-NEXT: sw a4, 12(a0)
391 ; RV32I-NEXT: sw a5, 8(a0)
392 ; RV32I-NEXT: sw a1, 0(a0)
393 ; RV32I-NEXT: sw t0, 4(a0)
394 ; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
395 ; RV32I-NEXT: addi sp, sp, 16
396 ; RV32I-NEXT: ret
397 ;
398 ; RV64I-LABEL: ashr128:
399 ; RV64I: # %bb.0:
400 ; RV64I-NEXT: addi a3, a2, -64
401 ; RV64I-NEXT: bltz a3, .LBB7_2
402 ; RV64I-NEXT: # %bb.1:
403 ; RV64I-NEXT: sra a0, a1, a3
404 ; RV64I-NEXT: srai a1, a1, 63
405 ; RV64I-NEXT: ret
406 ; RV64I-NEXT: .LBB7_2:
407 ; RV64I-NEXT: srl a0, a0, a2
408 ; RV64I-NEXT: xori a3, a2, 63
409 ; RV64I-NEXT: slli a4, a1, 1
410 ; RV64I-NEXT: sll a3, a4, a3
411 ; RV64I-NEXT: or a0, a0, a3
412 ; RV64I-NEXT: sra a1, a1, a2
413 ; RV64I-NEXT: ret
414 %1 = ashr i128 %a, %b
415 ret i128 %1
416 }
418 define i128 @shl128(i128 %a, i128 %b) nounwind {
419 ; RV32I-LABEL: shl128:
420 ; RV32I: # %bb.0:
421 ; RV32I-NEXT: lw a2, 0(a2)
422 ; RV32I-NEXT: lw a5, 4(a1)
423 ; RV32I-NEXT: lw a4, 0(a1)
424 ; RV32I-NEXT: neg a6, a2
425 ; RV32I-NEXT: li a3, 64
426 ; RV32I-NEXT: li a7, 32
427 ; RV32I-NEXT: sub t1, a7, a2
428 ; RV32I-NEXT: srl t0, a5, a6
429 ; RV32I-NEXT: bltz t1, .LBB8_2
430 ; RV32I-NEXT: # %bb.1:
431 ; RV32I-NEXT: mv t2, t0
432 ; RV32I-NEXT: j .LBB8_3
433 ; RV32I-NEXT: .LBB8_2:
434 ; RV32I-NEXT: srl a6, a4, a6
435 ; RV32I-NEXT: sub a7, a3, a2
436 ; RV32I-NEXT: xori a7, a7, 31
437 ; RV32I-NEXT: slli t2, a5, 1
438 ; RV32I-NEXT: sll a7, t2, a7
439 ; RV32I-NEXT: or t2, a6, a7
440 ; RV32I-NEXT: .LBB8_3:
441 ; RV32I-NEXT: lw t5, 8(a1)
442 ; RV32I-NEXT: addi a6, a2, -32
443 ; RV32I-NEXT: bgez a6, .LBB8_5
444 ; RV32I-NEXT: # %bb.4:
445 ; RV32I-NEXT: sll a7, t5, a2
446 ; RV32I-NEXT: or t2, t2, a7
447 ; RV32I-NEXT: .LBB8_5:
448 ; RV32I-NEXT: addi t4, a2, -96
449 ; RV32I-NEXT: addi t3, a2, -64
450 ; RV32I-NEXT: bltz t4, .LBB8_7
451 ; RV32I-NEXT: # %bb.6:
452 ; RV32I-NEXT: li a7, 0
453 ; RV32I-NEXT: bgeu a2, a3, .LBB8_8
454 ; RV32I-NEXT: j .LBB8_9
455 ; RV32I-NEXT: .LBB8_7:
456 ; RV32I-NEXT: sll a7, a4, t3
457 ; RV32I-NEXT: bltu a2, a3, .LBB8_9
458 ; RV32I-NEXT: .LBB8_8:
459 ; RV32I-NEXT: mv t2, a7
460 ; RV32I-NEXT: .LBB8_9:
461 ; RV32I-NEXT: mv a7, t5
462 ; RV32I-NEXT: beqz a2, .LBB8_11
463 ; RV32I-NEXT: # %bb.10:
464 ; RV32I-NEXT: mv a7, t2
465 ; RV32I-NEXT: .LBB8_11:
466 ; RV32I-NEXT: lw a1, 12(a1)
467 ; RV32I-NEXT: xori t2, a2, 31
468 ; RV32I-NEXT: bltz a6, .LBB8_13
469 ; RV32I-NEXT: # %bb.12:
470 ; RV32I-NEXT: sll t5, t5, a6
471 ; RV32I-NEXT: bltz t1, .LBB8_14
472 ; RV32I-NEXT: j .LBB8_15
473 ; RV32I-NEXT: .LBB8_13:
474 ; RV32I-NEXT: sll t6, a1, a2
475 ; RV32I-NEXT: srli t5, t5, 1
476 ; RV32I-NEXT: srl t5, t5, t2
477 ; RV32I-NEXT: or t5, t6, t5
478 ; RV32I-NEXT: bgez t1, .LBB8_15
479 ; RV32I-NEXT: .LBB8_14:
480 ; RV32I-NEXT: or t5, t5, t0
481 ; RV32I-NEXT: .LBB8_15:
482 ; RV32I-NEXT: srli t0, a4, 1
483 ; RV32I-NEXT: bltz t4, .LBB8_17
484 ; RV32I-NEXT: # %bb.16:
485 ; RV32I-NEXT: sll t1, a4, t4
486 ; RV32I-NEXT: bgeu a2, a3, .LBB8_18
487 ; RV32I-NEXT: j .LBB8_19
488 ; RV32I-NEXT: .LBB8_17:
489 ; RV32I-NEXT: sll t1, a5, t3
490 ; RV32I-NEXT: xori t3, t3, 31
491 ; RV32I-NEXT: srl t3, t0, t3
492 ; RV32I-NEXT: or t1, t1, t3
493 ; RV32I-NEXT: bltu a2, a3, .LBB8_19
494 ; RV32I-NEXT: .LBB8_18:
495 ; RV32I-NEXT: mv t5, t1
496 ; RV32I-NEXT: .LBB8_19:
497 ; RV32I-NEXT: bnez a2, .LBB8_22
498 ; RV32I-NEXT: # %bb.20:
499 ; RV32I-NEXT: bltz a6, .LBB8_23
500 ; RV32I-NEXT: .LBB8_21:
501 ; RV32I-NEXT: sll a5, a4, a6
502 ; RV32I-NEXT: bgeu a2, a3, .LBB8_24
503 ; RV32I-NEXT: j .LBB8_25
504 ; RV32I-NEXT: .LBB8_22:
505 ; RV32I-NEXT: mv a1, t5
506 ; RV32I-NEXT: bgez a6, .LBB8_21
507 ; RV32I-NEXT: .LBB8_23:
508 ; RV32I-NEXT: sll a5, a5, a2
509 ; RV32I-NEXT: srl t0, t0, t2
510 ; RV32I-NEXT: or a5, a5, t0
511 ; RV32I-NEXT: bltu a2, a3, .LBB8_25
512 ; RV32I-NEXT: .LBB8_24:
513 ; RV32I-NEXT: li a5, 0
514 ; RV32I-NEXT: .LBB8_25:
515 ; RV32I-NEXT: bltz a6, .LBB8_27
516 ; RV32I-NEXT: # %bb.26:
517 ; RV32I-NEXT: li a4, 0
518 ; RV32I-NEXT: bgeu a2, a3, .LBB8_28
519 ; RV32I-NEXT: j .LBB8_29
520 ; RV32I-NEXT: .LBB8_27:
521 ; RV32I-NEXT: sll a4, a4, a2
522 ; RV32I-NEXT: bltu a2, a3, .LBB8_29
523 ; RV32I-NEXT: .LBB8_28:
524 ; RV32I-NEXT: li a4, 0
525 ; RV32I-NEXT: .LBB8_29:
526 ; RV32I-NEXT: sw a4, 0(a0)
527 ; RV32I-NEXT: sw a5, 4(a0)
528 ; RV32I-NEXT: sw a1, 12(a0)
529 ; RV32I-NEXT: sw a7, 8(a0)
530 ; RV32I-NEXT: ret
531 ;
532 ; RV64I-LABEL: shl128:
533 ; RV64I: # %bb.0:
534 ; RV64I-NEXT: addi a3, a2, -64
535 ; RV64I-NEXT: bltz a3, .LBB8_2
536 ; RV64I-NEXT: # %bb.1:
537 ; RV64I-NEXT: sll a1, a0, a3
538 ; RV64I-NEXT: li a0, 0
539 ; RV64I-NEXT: ret
540 ; RV64I-NEXT: .LBB8_2:
541 ; RV64I-NEXT: sll a1, a1, a2
542 ; RV64I-NEXT: xori a3, a2, 63
543 ; RV64I-NEXT: srli a4, a0, 1
544 ; RV64I-NEXT: srl a3, a4, a3
545 ; RV64I-NEXT: or a1, a1, a3
546 ; RV64I-NEXT: sll a0, a0, a2
547 ; RV64I-NEXT: ret
548 %1 = shl i128 %a, %b
549 ret i128 %1
550 }
552 define i64 @fshr64_minsize(i64 %a, i64 %b) minsize nounwind {
553 ; RV32I-LABEL: fshr64_minsize:
554 ; RV32I: # %bb.0:
555 ; RV32I-NEXT: andi a4, a2, 32
556 ; RV32I-NEXT: mv a3, a0
557 ; RV32I-NEXT: beqz a4, .LBB9_2
558 ; RV32I-NEXT: # %bb.1:
559 ; RV32I-NEXT: mv a3, a1
560 ; RV32I-NEXT: .LBB9_2:
561 ; RV32I-NEXT: srl a5, a3, a2
562 ; RV32I-NEXT: beqz a4, .LBB9_4
563 ; RV32I-NEXT: # %bb.3:
564 ; RV32I-NEXT: mv a1, a0
565 ; RV32I-NEXT: .LBB9_4:
566 ; RV32I-NEXT: slli a0, a1, 1
567 ; RV32I-NEXT: not a4, a2
568 ; RV32I-NEXT: sll a0, a0, a4
569 ; RV32I-NEXT: or a0, a0, a5
570 ; RV32I-NEXT: srl a1, a1, a2
571 ; RV32I-NEXT: slli a2, a3, 1
572 ; RV32I-NEXT: sll a2, a2, a4
573 ; RV32I-NEXT: or a1, a2, a1
574 ; RV32I-NEXT: ret
575 ;
576 ; RV64I-LABEL: fshr64_minsize:
577 ; RV64I: # %bb.0:
578 ; RV64I-NEXT: srl a2, a0, a1
579 ; RV64I-NEXT: neg a1, a1
580 ; RV64I-NEXT: sll a0, a0, a1
581 ; RV64I-NEXT: or a0, a2, a0
582 ; RV64I-NEXT: ret
583 %res = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b)
584 ret i64 %res
585 }
587 define i128 @fshr128_minsize(i128 %a, i128 %b) minsize nounwind {
588 ; RV32I-LABEL: fshr128_minsize:
589 ; RV32I: # %bb.0:
590 ; RV32I-NEXT: lw a3, 8(a1)
591 ; RV32I-NEXT: lw t2, 0(a1)
592 ; RV32I-NEXT: lw a2, 0(a2)
593 ; RV32I-NEXT: lw a7, 4(a1)
594 ; RV32I-NEXT: lw a1, 12(a1)
595 ; RV32I-NEXT: andi t1, a2, 64
596 ; RV32I-NEXT: mv t0, a7
597 ; RV32I-NEXT: mv a4, t2
598 ; RV32I-NEXT: beqz t1, .LBB10_2
599 ; RV32I-NEXT: # %bb.1:
600 ; RV32I-NEXT: mv t0, a1
601 ; RV32I-NEXT: mv a4, a3
602 ; RV32I-NEXT: .LBB10_2:
603 ; RV32I-NEXT: andi a6, a2, 32
604 ; RV32I-NEXT: mv a5, a4
605 ; RV32I-NEXT: bnez a6, .LBB10_13
606 ; RV32I-NEXT: # %bb.3:
607 ; RV32I-NEXT: bnez t1, .LBB10_14
608 ; RV32I-NEXT: .LBB10_4:
609 ; RV32I-NEXT: beqz a6, .LBB10_6
610 ; RV32I-NEXT: .LBB10_5:
611 ; RV32I-NEXT: mv t0, a3
612 ; RV32I-NEXT: .LBB10_6:
613 ; RV32I-NEXT: slli t3, t0, 1
614 ; RV32I-NEXT: not t2, a2
615 ; RV32I-NEXT: beqz t1, .LBB10_8
616 ; RV32I-NEXT: # %bb.7:
617 ; RV32I-NEXT: mv a1, a7
618 ; RV32I-NEXT: .LBB10_8:
619 ; RV32I-NEXT: srl a7, a5, a2
620 ; RV32I-NEXT: sll t1, t3, t2
621 ; RV32I-NEXT: srl t0, t0, a2
622 ; RV32I-NEXT: beqz a6, .LBB10_10
623 ; RV32I-NEXT: # %bb.9:
624 ; RV32I-NEXT: mv a3, a1
625 ; RV32I-NEXT: .LBB10_10:
626 ; RV32I-NEXT: or a7, t1, a7
627 ; RV32I-NEXT: slli t1, a3, 1
628 ; RV32I-NEXT: sll t1, t1, t2
629 ; RV32I-NEXT: or t0, t1, t0
630 ; RV32I-NEXT: srl a3, a3, a2
631 ; RV32I-NEXT: beqz a6, .LBB10_12
632 ; RV32I-NEXT: # %bb.11:
633 ; RV32I-NEXT: mv a1, a4
634 ; RV32I-NEXT: .LBB10_12:
635 ; RV32I-NEXT: slli a4, a1, 1
636 ; RV32I-NEXT: sll a4, a4, t2
637 ; RV32I-NEXT: or a3, a4, a3
638 ; RV32I-NEXT: srl a1, a1, a2
639 ; RV32I-NEXT: slli a2, a5, 1
640 ; RV32I-NEXT: sll a2, a2, t2
641 ; RV32I-NEXT: or a1, a2, a1
642 ; RV32I-NEXT: sw a1, 12(a0)
643 ; RV32I-NEXT: sw a3, 8(a0)
644 ; RV32I-NEXT: sw t0, 4(a0)
645 ; RV32I-NEXT: sw a7, 0(a0)
646 ; RV32I-NEXT: ret
647 ; RV32I-NEXT: .LBB10_13:
648 ; RV32I-NEXT: mv a5, t0
649 ; RV32I-NEXT: beqz t1, .LBB10_4
650 ; RV32I-NEXT: .LBB10_14:
651 ; RV32I-NEXT: mv a3, t2
652 ; RV32I-NEXT: bnez a6, .LBB10_5
653 ; RV32I-NEXT: j .LBB10_6
654 ;
655 ; RV64I-LABEL: fshr128_minsize:
656 ; RV64I: # %bb.0:
657 ; RV64I-NEXT: andi a4, a2, 64
658 ; RV64I-NEXT: mv a3, a0
659 ; RV64I-NEXT: beqz a4, .LBB10_2
660 ; RV64I-NEXT: # %bb.1:
661 ; RV64I-NEXT: mv a3, a1
662 ; RV64I-NEXT: .LBB10_2:
663 ; RV64I-NEXT: srl a5, a3, a2
664 ; RV64I-NEXT: beqz a4, .LBB10_4
665 ; RV64I-NEXT: # %bb.3:
666 ; RV64I-NEXT: mv a1, a0
667 ; RV64I-NEXT: .LBB10_4:
668 ; RV64I-NEXT: slli a0, a1, 1
669 ; RV64I-NEXT: not a4, a2
670 ; RV64I-NEXT: sll a0, a0, a4
671 ; RV64I-NEXT: or a0, a0, a5
672 ; RV64I-NEXT: srl a1, a1, a2
673 ; RV64I-NEXT: slli a2, a3, 1
674 ; RV64I-NEXT: sll a2, a2, a4
675 ; RV64I-NEXT: or a1, a2, a1
676 ; RV64I-NEXT: ret
677 %res = tail call i128 @llvm.fshr.i128(i128 %a, i128 %a, i128 %b)
678 ret i128 %res
679 }