1 //===-- M68kInstrAtomics.td - Atomics Instructions ---------*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 foreach size = [8, 16, 32] in {
10 def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_ARI:$ptr),
11 (!cast<MxInst>("MOV"#size#"dj") !cast<MxMemOp>("MxARI"#size):$ptr)>;
13 def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_ARI:$ptr),
14 (!cast<MxInst>("MOV"#size#"jd") !cast<MxMemOp>("MxARI"#size):$ptr,
15 !cast<MxRegOp>("MxDRD"#size):$val)>;
18 let Predicates = [AtLeastM68020] in {
19 class MxCASOp<bits<2> size_encoding, MxType type>
20 : MxInst<(outs type.ROp:$out),
21 (ins type.ROp:$dc, type.ROp:$du, !cast<MxMemOp>("MxARI"#type.Size):$mem),
22 "cas."#type.Prefix#" $dc, $du, $mem"> {
24 (descend 0b00001, size_encoding, 0b011, MxEncAddrMode_j<"mem">.EA),
25 (descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3))
27 let Constraints = "$out = $dc";
32 def CAS8 : MxCASOp<0x1, MxType8d>;
33 def CAS16 : MxCASOp<0x2, MxType16d>;
34 def CAS32 : MxCASOp<0x3, MxType32d>;
37 foreach size = [8, 16, 32] in {
38 def : Pat<(!cast<SDPatternOperator>("atomic_cmp_swap_"#size) MxCP_ARI:$ptr,
39 !cast<MxRegOp>("MxDRD"#size):$cmp,
40 !cast<MxRegOp>("MxDRD"#size):$new),
41 (!cast<MxInst>("CAS"#size) !cast<MxRegOp>("MxDRD"#size):$cmp,
42 !cast<MxRegOp>("MxDRD"#size):$new,
43 !cast<MxMemOp>("MxARI"#size):$ptr)>;
45 } // let Predicates = [AtLeastM68020]