llvm/lib/CodeGen/MachineRegisterInfo.cpp

   1 //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // Implementation of the MachineRegisterInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "llvm/CodeGen/MachineRegisterInfo.h"
  14 #include "llvm/ADT/iterator_range.h"
  15 #include "llvm/CodeGen/MachineBasicBlock.h"
  16 #include "llvm/CodeGen/MachineFunction.h"
  17 #include "llvm/CodeGen/MachineInstr.h"
  18 #include "llvm/CodeGen/MachineInstrBuilder.h"
  19 #include "llvm/CodeGen/MachineOperand.h"
  20 #include "llvm/CodeGen/TargetInstrInfo.h"
  21 #include "llvm/CodeGen/TargetRegisterInfo.h"
  22 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  23 #include "llvm/Config/llvm-config.h"
  24 #include "llvm/IR/Attributes.h"
  25 #include "llvm/IR/DebugLoc.h"
  26 #include "llvm/IR/Function.h"
  27 #include "llvm/MC/MCRegisterInfo.h"
  28 #include "llvm/Support/Casting.h"
  29 #include "llvm/Support/CommandLine.h"
  30 #include "llvm/Support/Compiler.h"
  31 #include "llvm/Support/ErrorHandling.h"
  32 #include "llvm/Support/raw_ostream.h"
  33 #include <cassert>
  34
  35 using namespace llvm;
  36
  37 static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
  38   cl::init(true), cl::desc("Enable subregister liveness tracking."));
  39
  40 // Pin the vtable to this file.
  41 void MachineRegisterInfo::Delegate::anchor() {}
  42
  43 MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
  44     : MF(MF),
  45       TracksSubRegLiveness(EnableSubRegLiveness.getNumOccurrences()
  46                                ? EnableSubRegLiveness
  47                                : MF->getSubtarget().enableSubRegLiveness()) {
  48   unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
  49   VRegInfo.reserve(256);
  50   RegAllocHints.reserve(256);
  51   UsedPhysRegMask.resize(NumRegs);
  52   PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
  53   TheDelegates.clear();
  54 }
  55
  56 /// setRegClass - Set the register class of the specified virtual register.
  57 ///
  58 void
  59 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) {
  60   assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
  61   VRegInfo[Reg].first = RC;
  62 }
  63
  64 void MachineRegisterInfo::setRegBank(Register Reg,
  65                                      const RegisterBank &RegBank) {
  66   VRegInfo[Reg].first = &RegBank;
  67 }
  68
  69 static const TargetRegisterClass *
  70 constrainRegClass(MachineRegisterInfo &MRI, Register Reg,
  71                   const TargetRegisterClass *OldRC,
  72                   const TargetRegisterClass *RC, unsigned MinNumRegs) {
  73   if (OldRC == RC)
  74     return RC;
  75   const TargetRegisterClass *NewRC =
  76       MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
  77   if (!NewRC || NewRC == OldRC)
  78     return NewRC;
  79   if (NewRC->getNumRegs() < MinNumRegs)
  80     return nullptr;
  81   MRI.setRegClass(Reg, NewRC);
  82   return NewRC;
  83 }
  84
  85 const TargetRegisterClass *MachineRegisterInfo::constrainRegClass(
  86     Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) {
  87   if (Reg.isPhysical())
  88     return nullptr;
  89   return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
  90 }
  91
  92 bool
  93 MachineRegisterInfo::constrainRegAttrs(Register Reg,
  94                                        Register ConstrainingReg,
  95                                        unsigned MinNumRegs) {
  96   const LLT RegTy = getType(Reg);
  97   const LLT ConstrainingRegTy = getType(ConstrainingReg);
  98   if (RegTy.isValid() && ConstrainingRegTy.isValid() &&
  99       RegTy != ConstrainingRegTy)
 100     return false;
 101   const auto &ConstrainingRegCB = getRegClassOrRegBank(ConstrainingReg);
 102   if (!ConstrainingRegCB.isNull()) {
 103     const auto &RegCB = getRegClassOrRegBank(Reg);
 104     if (RegCB.isNull())
 105       setRegClassOrRegBank(Reg, ConstrainingRegCB);
 106     else if (isa<const TargetRegisterClass *>(RegCB) !=
 107              isa<const TargetRegisterClass *>(ConstrainingRegCB))
 108       return false;
 109     else if (isa<const TargetRegisterClass *>(RegCB)) {
 110       if (!::constrainRegClass(
 111               *this, Reg, cast<const TargetRegisterClass *>(RegCB),
 112               cast<const TargetRegisterClass *>(ConstrainingRegCB), MinNumRegs))
 113         return false;
 114     } else if (RegCB != ConstrainingRegCB)
 115       return false;
 116   }
 117   if (ConstrainingRegTy.isValid())
 118     setType(Reg, ConstrainingRegTy);
 119   return true;
 120 }
 121
 122 bool
 123 MachineRegisterInfo::recomputeRegClass(Register Reg) {
 124   const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
 125   const TargetRegisterClass *OldRC = getRegClass(Reg);
 126   const TargetRegisterClass *NewRC =
 127       getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC, *MF);
 128
 129   // Stop early if there is no room to grow.
 130   if (NewRC == OldRC)
 131     return false;
 132
 133   // Accumulate constraints from all uses.
 134   for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
 135     // Apply the effect of the given operand to NewRC.
 136     MachineInstr *MI = MO.getParent();
 137     unsigned OpNo = &MO - &MI->getOperand(0);
 138     NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
 139                                             getTargetRegisterInfo());
 140     if (!NewRC || NewRC == OldRC)
 141       return false;
 142   }
 143   setRegClass(Reg, NewRC);
 144   return true;
 145 }
 146
 147 Register MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) {
 148   Register Reg = Register::index2VirtReg(getNumVirtRegs());
 149   VRegInfo.grow(Reg);
 150   RegAllocHints.grow(Reg);
 151   insertVRegByName(Name, Reg);
 152   return Reg;
 153 }
 154
 155 /// createVirtualRegister - Create and return a new virtual register in the
 156 /// function with the specified register class.
 157 ///
 158 Register
 159 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass,
 160                                            StringRef Name) {
 161   assert(RegClass && "Cannot create register without RegClass!");
 162   assert(RegClass->isAllocatable() &&
 163          "Virtual register RegClass must be allocatable.");
 164
 165   // New virtual register number.
 166   Register Reg = createIncompleteVirtualRegister(Name);
 167   VRegInfo[Reg].first = RegClass;
 168   noteNewVirtualRegister(Reg);
 169   return Reg;
 170 }
 171
 172 Register MachineRegisterInfo::createVirtualRegister(VRegAttrs RegAttr,
 173                                                     StringRef Name) {
 174   Register Reg = createIncompleteVirtualRegister(Name);
 175   VRegInfo[Reg].first = RegAttr.RCOrRB;
 176   setType(Reg, RegAttr.Ty);
 177   noteNewVirtualRegister(Reg);
 178   return Reg;
 179 }
 180
 181 Register MachineRegisterInfo::cloneVirtualRegister(Register VReg,
 182                                                    StringRef Name) {
 183   Register Reg = createIncompleteVirtualRegister(Name);
 184   VRegInfo[Reg].first = VRegInfo[VReg].first;
 185   setType(Reg, getType(VReg));
 186   noteCloneVirtualRegister(Reg, VReg);
 187   return Reg;
 188 }
 189
 190 void MachineRegisterInfo::setType(Register VReg, LLT Ty) {
 191   VRegToType.grow(VReg);
 192   VRegToType[VReg] = Ty;
 193 }
 194
 195 Register
 196 MachineRegisterInfo::createGenericVirtualRegister(LLT Ty, StringRef Name) {
 197   // New virtual register number.
 198   Register Reg = createIncompleteVirtualRegister(Name);
 199   // FIXME: Should we use a dummy register class?
 200   VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
 201   setType(Reg, Ty);
 202   noteNewVirtualRegister(Reg);
 203   return Reg;
 204 }
 205
 206 void MachineRegisterInfo::clearVirtRegTypes() { VRegToType.clear(); }
 207
 208 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
 209 void MachineRegisterInfo::clearVirtRegs() {
 210 #ifndef NDEBUG
 211   for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
 212     Register Reg = Register::index2VirtReg(i);
 213     if (!VRegInfo[Reg].second)
 214       continue;
 215     verifyUseList(Reg);
 216     errs() << "Remaining virtual register "
 217            << printReg(Reg, getTargetRegisterInfo()) << "...\n";
 218     for (MachineInstr &MI : reg_instructions(Reg))
 219       errs() << "...in instruction: " << MI << "\n";
 220     std::abort();
 221   }
 222 #endif
 223   VRegInfo.clear();
 224   for (auto &I : LiveIns)
 225     I.second = 0;
 226 }
 227
 228 void MachineRegisterInfo::verifyUseList(Register Reg) const {
 229 #ifndef NDEBUG
 230   bool Valid = true;
 231   for (MachineOperand &M : reg_operands(Reg)) {
 232     MachineOperand *MO = &M;
 233     MachineInstr *MI = MO->getParent();
 234     if (!MI) {
 235       errs() << printReg(Reg, getTargetRegisterInfo())
 236              << " use list MachineOperand " << MO
 237              << " has no parent instruction.\n";
 238       Valid = false;
 239       continue;
 240     }
 241     MachineOperand *MO0 = &MI->getOperand(0);
 242     unsigned NumOps = MI->getNumOperands();
 243     if (!(MO >= MO0 && MO < MO0+NumOps)) {
 244       errs() << printReg(Reg, getTargetRegisterInfo())
 245              << " use list MachineOperand " << MO
 246              << " doesn't belong to parent MI: " << *MI;
 247       Valid = false;
 248     }
 249     if (!MO->isReg()) {
 250       errs() << printReg(Reg, getTargetRegisterInfo())
 251              << " MachineOperand " << MO << ": " << *MO
 252              << " is not a register\n";
 253       Valid = false;
 254     }
 255     if (MO->getReg() != Reg) {
 256       errs() << printReg(Reg, getTargetRegisterInfo())
 257              << " use-list MachineOperand " << MO << ": "
 258              << *MO << " is the wrong register\n";
 259       Valid = false;
 260     }
 261   }
 262   assert(Valid && "Invalid use list");
 263 #endif
 264 }
 265
 266 void MachineRegisterInfo::verifyUseLists() const {
 267 #ifndef NDEBUG
 268   for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
 269     verifyUseList(Register::index2VirtReg(i));
 270   for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
 271     verifyUseList(i);
 272 #endif
 273 }
 274
 275 /// Add MO to the linked list of operands for its register.
 276 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
 277   assert(!MO->isOnRegUseList() && "Already on list");
 278   MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
 279   MachineOperand *const Head = HeadRef;
 280
 281   // Head points to the first list element.
 282   // Next is NULL on the last list element.
 283   // Prev pointers are circular, so Head->Prev == Last.
 284
 285   // Head is NULL for an empty list.
 286   if (!Head) {
 287     MO->Contents.Reg.Prev = MO;
 288     MO->Contents.Reg.Next = nullptr;
 289     HeadRef = MO;
 290     return;
 291   }
 292   assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
 293
 294   // Insert MO between Last and Head in the circular Prev chain.
 295   MachineOperand *Last = Head->Contents.Reg.Prev;
 296   assert(Last && "Inconsistent use list");
 297   assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
 298   Head->Contents.Reg.Prev = MO;
 299   MO->Contents.Reg.Prev = Last;
 300
 301   // Def operands always precede uses. This allows def_iterator to stop early.
 302   // Insert def operands at the front, and use operands at the back.
 303   if (MO->isDef()) {
 304     // Insert def at the front.
 305     MO->Contents.Reg.Next = Head;
 306     HeadRef = MO;
 307   } else {
 308     // Insert use at the end.
 309     MO->Contents.Reg.Next = nullptr;
 310     Last->Contents.Reg.Next = MO;
 311   }
 312 }
 313
 314 /// Remove MO from its use-def list.
 315 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
 316   assert(MO->isOnRegUseList() && "Operand not on use list");
 317   MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
 318   MachineOperand *const Head = HeadRef;
 319   assert(Head && "List already empty");
 320
 321   // Unlink this from the doubly linked list of operands.
 322   MachineOperand *Next = MO->Contents.Reg.Next;
 323   MachineOperand *Prev = MO->Contents.Reg.Prev;
 324
 325   // Prev links are circular, next link is NULL instead of looping back to Head.
 326   if (MO == Head)
 327     HeadRef = Next;
 328   else
 329     Prev->Contents.Reg.Next = Next;
 330
 331   (Next ? Next : Head)->Contents.Reg.Prev = Prev;
 332
 333   MO->Contents.Reg.Prev = nullptr;
 334   MO->Contents.Reg.Next = nullptr;
 335 }
 336
 337 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
 338 ///
 339 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
 340 /// operands that won't be destroyed, which is OK because the MO destructor is
 341 /// trivial anyway).
 342 ///
 343 /// The Src and Dst ranges may overlap.
 344 void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
 345                                        MachineOperand *Src,
 346                                        unsigned NumOps) {
 347   assert(Src != Dst && NumOps && "Noop moveOperands");
 348
 349   // Copy backwards if Dst is within the Src range.
 350   int Stride = 1;
 351   if (Dst >= Src && Dst < Src + NumOps) {
 352     Stride = -1;
 353     Dst += NumOps - 1;
 354     Src += NumOps - 1;
 355   }
 356
 357   // Copy one operand at a time.
 358   do {
 359     new (Dst) MachineOperand(*Src);
 360
 361     // Dst takes Src's place in the use-def chain.
 362     if (Src->isReg()) {
 363       MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
 364       MachineOperand *Prev = Src->Contents.Reg.Prev;
 365       MachineOperand *Next = Src->Contents.Reg.Next;
 366       assert(Head && "List empty, but operand is chained");
 367       assert(Prev && "Operand was not on use-def list");
 368
 369       // Prev links are circular, next link is NULL instead of looping back to
 370       // Head.
 371       if (Src == Head)
 372         Head = Dst;
 373       else
 374         Prev->Contents.Reg.Next = Dst;
 375
 376       // Update Prev pointer. This also works when Src was pointing to itself
 377       // in a 1-element list. In that case Head == Dst.
 378       (Next ? Next : Head)->Contents.Reg.Prev = Dst;
 379     }
 380
 381     Dst += Stride;
 382     Src += Stride;
 383   } while (--NumOps);
 384 }
 385
 386 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
 387 /// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
 388 /// except that it also changes any definitions of the register as well.
 389 /// If ToReg is a physical register we apply the sub register to obtain the
 390 /// final/proper physical register.
 391 void MachineRegisterInfo::replaceRegWith(Register FromReg, Register ToReg) {
 392   assert(FromReg != ToReg && "Cannot replace a reg with itself");
 393
 394   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 395
 396   // TODO: This could be more efficient by bulk changing the operands.
 397   for (MachineOperand &O : llvm::make_early_inc_range(reg_operands(FromReg))) {
 398     if (ToReg.isPhysical()) {
 399       O.substPhysReg(ToReg, *TRI);
 400     } else {
 401       O.setReg(ToReg);
 402     }
 403   }
 404 }
 405
 406 /// getVRegDef - Return the machine instr that defines the specified virtual
 407 /// register or null if none is found.  This assumes that the code is in SSA
 408 /// form, so there should only be one definition.
 409 MachineInstr *MachineRegisterInfo::getVRegDef(Register Reg) const {
 410   // Since we are in SSA form, we can use the first definition.
 411   def_instr_iterator I = def_instr_begin(Reg);
 412   assert((I.atEnd() || std::next(I) == def_instr_end()) &&
 413          "getVRegDef assumes a single definition or no definition");
 414   return !I.atEnd() ? &*I : nullptr;
 415 }
 416
 417 /// getUniqueVRegDef - Return the unique machine instr that defines the
 418 /// specified virtual register or null if none is found.  If there are
 419 /// multiple definitions or no definition, return null.
 420 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(Register Reg) const {
 421   if (def_empty(Reg)) return nullptr;
 422   def_instr_iterator I = def_instr_begin(Reg);
 423   if (std::next(I) != def_instr_end())
 424     return nullptr;
 425   return &*I;
 426 }
 427
 428 bool MachineRegisterInfo::hasOneNonDBGUse(Register RegNo) const {
 429   return hasSingleElement(use_nodbg_operands(RegNo));
 430 }
 431
 432 bool MachineRegisterInfo::hasOneNonDBGUser(Register RegNo) const {
 433   return hasSingleElement(use_nodbg_instructions(RegNo));
 434 }
 435
 436 bool MachineRegisterInfo::hasAtMostUserInstrs(Register Reg,
 437                                               unsigned MaxUsers) const {
 438   return hasNItemsOrLess(use_instr_nodbg_begin(Reg), use_instr_nodbg_end(),
 439                          MaxUsers);
 440 }
 441
 442 /// clearKillFlags - Iterate over all the uses of the given register and
 443 /// clear the kill flag from the MachineOperand. This function is used by
 444 /// optimization passes which extend register lifetimes and need only
 445 /// preserve conservative kill flag information.
 446 void MachineRegisterInfo::clearKillFlags(Register Reg) const {
 447   for (MachineOperand &MO : use_operands(Reg))
 448     MO.setIsKill(false);
 449 }
 450
 451 bool MachineRegisterInfo::isLiveIn(Register Reg) const {
 452   for (const std::pair<MCRegister, Register> &LI : liveins())
 453     if ((Register)LI.first == Reg || LI.second == Reg)
 454       return true;
 455   return false;
 456 }
 457
 458 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
 459 /// corresponding live-in physical register.
 460 MCRegister MachineRegisterInfo::getLiveInPhysReg(Register VReg) const {
 461   for (const std::pair<MCRegister, Register> &LI : liveins())
 462     if (LI.second == VReg)
 463       return LI.first;
 464   return MCRegister();
 465 }
 466
 467 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
 468 /// corresponding live-in physical register.
 469 Register MachineRegisterInfo::getLiveInVirtReg(MCRegister PReg) const {
 470   for (const std::pair<MCRegister, Register> &LI : liveins())
 471     if (LI.first == PReg)
 472       return LI.second;
 473   return Register();
 474 }
 475
 476 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
 477 /// into the given entry block.
 478 void
 479 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
 480                                       const TargetRegisterInfo &TRI,
 481                                       const TargetInstrInfo &TII) {
 482   // Emit the copies into the top of the block.
 483   for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
 484     if (LiveIns[i].second) {
 485       if (use_nodbg_empty(LiveIns[i].second)) {
 486         // The livein has no non-dbg uses. Drop it.
 487         //
 488         // It would be preferable to have isel avoid creating live-in
 489         // records for unused arguments in the first place, but it's
 490         // complicated by the debug info code for arguments.
 491         LiveIns.erase(LiveIns.begin() + i);
 492         --i; --e;
 493       } else {
 494         // Emit a copy.
 495         BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
 496                 TII.get(TargetOpcode::COPY), LiveIns[i].second)
 497           .addReg(LiveIns[i].first);
 498
 499         // Add the register to the entry block live-in set.
 500         EntryMBB->addLiveIn(LiveIns[i].first);
 501       }
 502     } else {
 503       // Add the register to the entry block live-in set.
 504       EntryMBB->addLiveIn(LiveIns[i].first);
 505     }
 506 }
 507
 508 LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(Register Reg) const {
 509   // Lane masks are only defined for vregs.
 510   assert(Reg.isVirtual());
 511   const TargetRegisterClass &TRC = *getRegClass(Reg);
 512   return TRC.getLaneMask();
 513 }
 514
 515 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 516 LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(Register Reg) const {
 517   for (MachineInstr &I : use_instructions(Reg))
 518     I.dump();
 519 }
 520 #endif
 521
 522 void MachineRegisterInfo::freezeReservedRegs() {
 523   ReservedRegs = getTargetRegisterInfo()->getReservedRegs(*MF);
 524   assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
 525          "Invalid ReservedRegs vector from target");
 526 }
 527
 528 bool MachineRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
 529   assert(Register::isPhysicalRegister(PhysReg));
 530
 531   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 532   if (TRI->isConstantPhysReg(PhysReg))
 533     return true;
 534
 535   // Check if any overlapping register is modified, or allocatable so it may be
 536   // used later.
 537   for (MCRegAliasIterator AI(PhysReg, TRI, true);
 538        AI.isValid(); ++AI)
 539     if (!def_empty(*AI) || isAllocatable(*AI))
 540       return false;
 541   return true;
 542 }
 543
 544 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
 545 /// specified register as undefined which causes the DBG_VALUE to be
 546 /// deleted during LiveDebugVariables analysis.
 547 void MachineRegisterInfo::markUsesInDebugValueAsUndef(Register Reg) const {
 548   // Mark any DBG_VALUE* that uses Reg as undef (but don't delete it.)
 549   // We use make_early_inc_range because setReg invalidates the iterator.
 550   for (MachineInstr &UseMI : llvm::make_early_inc_range(use_instructions(Reg))) {
 551     if (UseMI.isDebugValue() && UseMI.hasDebugOperandForReg(Reg))
 552       UseMI.setDebugValueUndef();
 553   }
 554 }
 555
 556 static const Function *getCalledFunction(const MachineInstr &MI) {
 557   for (const MachineOperand &MO : MI.operands()) {
 558     if (!MO.isGlobal())
 559       continue;
 560     const Function *Func = dyn_cast<Function>(MO.getGlobal());
 561     if (Func != nullptr)
 562       return Func;
 563   }
 564   return nullptr;
 565 }
 566
 567 static bool isNoReturnDef(const MachineOperand &MO) {
 568   // Anything which is not a noreturn function is a real def.
 569   const MachineInstr &MI = *MO.getParent();
 570   if (!MI.isCall())
 571     return false;
 572   const MachineBasicBlock &MBB = *MI.getParent();
 573   if (!MBB.succ_empty())
 574     return false;
 575   const MachineFunction &MF = *MBB.getParent();
 576   // We need to keep correct unwind information even if the function will
 577   // not return, since the runtime may need it.
 578   if (MF.getFunction().hasFnAttribute(Attribute::UWTable))
 579     return false;
 580   const Function *Called = getCalledFunction(MI);
 581   return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
 582            !Called->hasFnAttribute(Attribute::NoUnwind));
 583 }
 584
 585 bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg,
 586                                             bool SkipNoReturnDef) const {
 587   if (UsedPhysRegMask.test(PhysReg))
 588     return true;
 589   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 590   for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
 591     for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
 592       if (!SkipNoReturnDef && isNoReturnDef(MO))
 593         continue;
 594       return true;
 595     }
 596   }
 597   return false;
 598 }
 599
 600 bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg,
 601                                         bool SkipRegMaskTest) const {
 602   if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg))
 603     return true;
 604   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 605   for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
 606        ++AliasReg) {
 607     if (!reg_nodbg_empty(*AliasReg))
 608       return true;
 609   }
 610   return false;
 611 }
 612
 613 void MachineRegisterInfo::disableCalleeSavedRegister(MCRegister Reg) {
 614
 615   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 616   assert(Reg && (Reg < TRI->getNumRegs()) &&
 617          "Trying to disable an invalid register");
 618
 619   if (!IsUpdatedCSRsInitialized) {
 620     const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
 621     for (const MCPhysReg *I = CSR; *I; ++I)
 622       UpdatedCSRs.push_back(*I);
 623
 624     // Zero value represents the end of the register list
 625     // (no more registers should be pushed).
 626     UpdatedCSRs.push_back(0);
 627
 628     IsUpdatedCSRsInitialized = true;
 629   }
 630
 631   // Remove the register (and its aliases from the list).
 632   for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
 633     llvm::erase(UpdatedCSRs, *AI);
 634 }
 635
 636 const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const {
 637   if (IsUpdatedCSRsInitialized)
 638     return UpdatedCSRs.data();
 639
 640   return getTargetRegisterInfo()->getCalleeSavedRegs(MF);
 641 }
 642
 643 void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) {
 644   if (IsUpdatedCSRsInitialized)
 645     UpdatedCSRs.clear();
 646
 647   append_range(UpdatedCSRs, CSRs);
 648
 649   // Zero value represents the end of the register list
 650   // (no more registers should be pushed).
 651   UpdatedCSRs.push_back(0);
 652   IsUpdatedCSRsInitialized = true;
 653 }
 654
 655 bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
 656   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 657   for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
 658     if (all_of(TRI->superregs_inclusive(*Root),
 659                [&](MCPhysReg Super) { return isReserved(Super); }))
 660       return true;
 661   }
 662   return false;
 663 }