llvm/lib/CodeGen/TargetSchedule.cpp

   1 //===- llvm/Target/TargetSchedule.cpp - Sched Machine Model ---------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements a wrapper around MCSchedModel that allows the interface
  10 // to benefit from information currently only available in TargetInstrInfo.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/CodeGen/TargetSchedule.h"
  15 #include "llvm/CodeGen/MachineFunction.h"
  16 #include "llvm/CodeGen/MachineInstr.h"
  17 #include "llvm/CodeGen/MachineOperand.h"
  18 #include "llvm/CodeGen/TargetInstrInfo.h"
  19 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  20 #include "llvm/MC/MCInstrDesc.h"
  21 #include "llvm/MC/MCInstrItineraries.h"
  22 #include "llvm/MC/MCSchedule.h"
  23 #include "llvm/Support/CommandLine.h"
  24 #include "llvm/Support/ErrorHandling.h"
  25 #include "llvm/Support/raw_ostream.h"
  26 #include <algorithm>
  27 #include <cassert>
  28 #include <cstdint>
  29 #include <numeric>
  30
  31 using namespace llvm;
  32
  33 static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
  34   cl::desc("Use TargetSchedModel for latency lookup"));
  35
  36 static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
  37   cl::desc("Use InstrItineraryData for latency lookup"));
  38
  39 static cl::opt<bool> ForceEnableIntervals(
  40     "sched-model-force-enable-intervals", cl::Hidden, cl::init(false),
  41     cl::desc("Force the use of resource intervals in the schedule model"));
  42
  43 bool TargetSchedModel::hasInstrSchedModel() const {
  44   return EnableSchedModel && SchedModel.hasInstrSchedModel();
  45 }
  46
  47 bool TargetSchedModel::hasInstrItineraries() const {
  48   return EnableSchedItins && !InstrItins.isEmpty();
  49 }
  50
  51 void TargetSchedModel::init(const TargetSubtargetInfo *TSInfo) {
  52   STI = TSInfo;
  53   SchedModel = TSInfo->getSchedModel();
  54   TII = TSInfo->getInstrInfo();
  55   STI->initInstrItins(InstrItins);
  56
  57   unsigned NumRes = SchedModel.getNumProcResourceKinds();
  58   ResourceFactors.resize(NumRes);
  59   ResourceLCM = SchedModel.IssueWidth;
  60   for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
  61     unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
  62     if (NumUnits > 0)
  63       ResourceLCM = std::lcm(ResourceLCM, NumUnits);
  64   }
  65   MicroOpFactor = ResourceLCM / SchedModel.IssueWidth;
  66   for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
  67     unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
  68     ResourceFactors[Idx] = NumUnits ? (ResourceLCM / NumUnits) : 0;
  69   }
  70 }
  71
  72 /// Returns true only if instruction is specified as single issue.
  73 bool TargetSchedModel::mustBeginGroup(const MachineInstr *MI,
  74                                      const MCSchedClassDesc *SC) const {
  75   if (hasInstrSchedModel()) {
  76     if (!SC)
  77       SC = resolveSchedClass(MI);
  78     if (SC->isValid())
  79       return SC->BeginGroup;
  80   }
  81   return false;
  82 }
  83
  84 bool TargetSchedModel::mustEndGroup(const MachineInstr *MI,
  85                                      const MCSchedClassDesc *SC) const {
  86   if (hasInstrSchedModel()) {
  87     if (!SC)
  88       SC = resolveSchedClass(MI);
  89     if (SC->isValid())
  90       return SC->EndGroup;
  91   }
  92   return false;
  93 }
  94
  95 unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI,
  96                                           const MCSchedClassDesc *SC) const {
  97   if (hasInstrItineraries()) {
  98     int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
  99     return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, *MI);
 100   }
 101   if (hasInstrSchedModel()) {
 102     if (!SC)
 103       SC = resolveSchedClass(MI);
 104     if (SC->isValid())
 105       return SC->NumMicroOps;
 106   }
 107   return MI->isTransient() ? 0 : 1;
 108 }
 109
 110 // The machine model may explicitly specify an invalid latency, which
 111 // effectively means infinite latency. Since users of the TargetSchedule API
 112 // don't know how to handle this, we convert it to a very large latency that is
 113 // easy to distinguish when debugging the DAG but won't induce overflow.
 114 static unsigned capLatency(int Cycles) {
 115   return Cycles >= 0 ? Cycles : 1000;
 116 }
 117
 118 /// Return the MCSchedClassDesc for this instruction. Some SchedClasses require
 119 /// evaluation of predicates that depend on instruction operands or flags.
 120 const MCSchedClassDesc *TargetSchedModel::
 121 resolveSchedClass(const MachineInstr *MI) const {
 122   // Get the definition's scheduling class descriptor from this machine model.
 123   unsigned SchedClass = MI->getDesc().getSchedClass();
 124   const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
 125   if (!SCDesc->isValid())
 126     return SCDesc;
 127
 128 #ifndef NDEBUG
 129   unsigned NIter = 0;
 130 #endif
 131   while (SCDesc->isVariant()) {
 132     assert(++NIter < 6 && "Variants are nested deeper than the magic number");
 133
 134     SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
 135     SCDesc = SchedModel.getSchedClassDesc(SchedClass);
 136   }
 137   return SCDesc;
 138 }
 139
 140 /// Find the def index of this operand. This index maps to the machine model and
 141 /// is independent of use operands. Def operands may be reordered with uses or
 142 /// merged with uses without affecting the def index (e.g. before/after
 143 /// regalloc). However, an instruction's def operands must never be reordered
 144 /// with respect to each other.
 145 static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
 146   unsigned DefIdx = 0;
 147   for (unsigned i = 0; i != DefOperIdx; ++i) {
 148     const MachineOperand &MO = MI->getOperand(i);
 149     if (MO.isReg() && MO.isDef())
 150       ++DefIdx;
 151   }
 152   return DefIdx;
 153 }
 154
 155 /// Find the use index of this operand. This is independent of the instruction's
 156 /// def operands.
 157 ///
 158 /// Note that uses are not determined by the operand's isUse property, which
 159 /// is simply the inverse of isDef. Here we consider any readsReg operand to be
 160 /// a "use". The machine model allows an operand to be both a Def and Use.
 161 static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) {
 162   unsigned UseIdx = 0;
 163   for (unsigned i = 0; i != UseOperIdx; ++i) {
 164     const MachineOperand &MO = MI->getOperand(i);
 165     if (MO.isReg() && MO.readsReg() && !MO.isDef())
 166       ++UseIdx;
 167   }
 168   return UseIdx;
 169 }
 170
 171 // Top-level API for clients that know the operand indices. This doesn't need to
 172 // return std::optional<unsigned>, as it always returns a valid latency.
 173 unsigned TargetSchedModel::computeOperandLatency(
 174   const MachineInstr *DefMI, unsigned DefOperIdx,
 175   const MachineInstr *UseMI, unsigned UseOperIdx) const {
 176
 177   const unsigned InstrLatency = computeInstrLatency(DefMI);
 178   const unsigned DefaultDefLatency = TII->defaultDefLatency(SchedModel, *DefMI);
 179
 180   if (!hasInstrSchedModel() && !hasInstrItineraries())
 181     return DefaultDefLatency;
 182
 183   if (hasInstrItineraries()) {
 184     std::optional<unsigned> OperLatency;
 185     if (UseMI) {
 186       OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx,
 187                                            *UseMI, UseOperIdx);
 188     }
 189     else {
 190       unsigned DefClass = DefMI->getDesc().getSchedClass();
 191       OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
 192     }
 193
 194     // Expected latency is the max of InstrLatency and DefaultDefLatency, if we
 195     // didn't find an operand latency.
 196     return OperLatency ? *OperLatency
 197                        : std::max(InstrLatency, DefaultDefLatency);
 198   }
 199
 200   // hasInstrSchedModel()
 201   const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
 202   unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
 203   if (DefIdx < SCDesc->NumWriteLatencyEntries) {
 204     // Lookup the definition's write latency in SubtargetInfo.
 205     const MCWriteLatencyEntry *WLEntry =
 206       STI->getWriteLatencyEntry(SCDesc, DefIdx);
 207     unsigned WriteID = WLEntry->WriteResourceID;
 208     unsigned Latency = capLatency(WLEntry->Cycles);
 209     if (!UseMI)
 210       return Latency;
 211
 212     // Lookup the use's latency adjustment in SubtargetInfo.
 213     const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
 214     if (UseDesc->NumReadAdvanceEntries == 0)
 215       return Latency;
 216     unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
 217     int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
 218     if (Advance > 0 && (unsigned)Advance > Latency) // unsigned wrap
 219       return 0;
 220     return Latency - Advance;
 221   }
 222   // If DefIdx does not exist in the model (e.g. implicit defs), then return
 223   // unit latency (defaultDefLatency may be too conservative).
 224 #ifndef NDEBUG
 225   if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit() &&
 226       !DefMI->getDesc().operands()[DefOperIdx].isOptionalDef() &&
 227       SchedModel.isComplete()) {
 228     errs() << "DefIdx " << DefIdx << " exceeds machine model writes for "
 229            << *DefMI << " (Try with MCSchedModel.CompleteModel set to false)";
 230     llvm_unreachable("incomplete machine model");
 231   }
 232 #endif
 233   // FIXME: Automatically giving all implicit defs defaultDefLatency is
 234   // undesirable. We should only do it for defs that are known to the MC
 235   // desc like flags. Truly implicit defs should get 1 cycle latency.
 236   return DefMI->isTransient() ? 0 : DefaultDefLatency;
 237 }
 238
 239 unsigned
 240 TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const {
 241   return capLatency(MCSchedModel::computeInstrLatency(*STI, SCDesc));
 242 }
 243
 244 unsigned TargetSchedModel::computeInstrLatency(unsigned Opcode) const {
 245   assert(hasInstrSchedModel() && "Only call this function with a SchedModel");
 246   unsigned SCIdx = TII->get(Opcode).getSchedClass();
 247   return capLatency(SchedModel.computeInstrLatency(*STI, SCIdx));
 248 }
 249
 250 unsigned TargetSchedModel::computeInstrLatency(const MCInst &Inst) const {
 251   if (hasInstrSchedModel())
 252     return capLatency(SchedModel.computeInstrLatency(*STI, *TII, Inst));
 253   return computeInstrLatency(Inst.getOpcode());
 254 }
 255
 256 unsigned
 257 TargetSchedModel::computeInstrLatency(const MachineInstr *MI,
 258                                       bool UseDefaultDefLatency) const {
 259   // For the itinerary model, fall back to the old subtarget hook.
 260   // Allow subtargets to compute Bundle latencies outside the machine model.
 261   if (hasInstrItineraries() || MI->isBundle() ||
 262       (!hasInstrSchedModel() && !UseDefaultDefLatency))
 263     return TII->getInstrLatency(&InstrItins, *MI);
 264
 265   if (hasInstrSchedModel()) {
 266     const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
 267     if (SCDesc->isValid())
 268       return computeInstrLatency(*SCDesc);
 269   }
 270   return TII->defaultDefLatency(SchedModel, *MI);
 271 }
 272
 273 unsigned TargetSchedModel::
 274 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
 275                      const MachineInstr *DepMI) const {
 276   if (!SchedModel.isOutOfOrder())
 277     return 1;
 278
 279   // Out-of-order processor can dispatch WAW dependencies in the same cycle.
 280
 281   // Treat predication as a data dependency for out-of-order cpus. In-order
 282   // cpus do not need to treat predicated writes specially.
 283   //
 284   // TODO: The following hack exists because predication passes do not
 285   // correctly append imp-use operands, and readsReg() strangely returns false
 286   // for predicated defs.
 287   Register Reg = DefMI->getOperand(DefOperIdx).getReg();
 288   const MachineFunction &MF = *DefMI->getMF();
 289   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
 290   if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
 291     return computeInstrLatency(DefMI);
 292
 293   // If we have a per operand scheduling model, check if this def is writing
 294   // an unbuffered resource. If so, it treated like an in-order cpu.
 295   if (hasInstrSchedModel()) {
 296     const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
 297     if (SCDesc->isValid()) {
 298       for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
 299              *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) {
 300         if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->BufferSize)
 301           return 1;
 302       }
 303     }
 304   }
 305   return 0;
 306 }
 307
 308 double
 309 TargetSchedModel::computeReciprocalThroughput(const MachineInstr *MI) const {
 310   if (hasInstrItineraries()) {
 311     unsigned SchedClass = MI->getDesc().getSchedClass();
 312     return MCSchedModel::getReciprocalThroughput(SchedClass,
 313                                                  *getInstrItineraries());
 314   }
 315
 316   if (hasInstrSchedModel())
 317     return MCSchedModel::getReciprocalThroughput(*STI, *resolveSchedClass(MI));
 318
 319   return 0.0;
 320 }
 321
 322 double
 323 TargetSchedModel::computeReciprocalThroughput(unsigned Opcode) const {
 324   unsigned SchedClass = TII->get(Opcode).getSchedClass();
 325   if (hasInstrItineraries())
 326     return MCSchedModel::getReciprocalThroughput(SchedClass,
 327                                                  *getInstrItineraries());
 328   if (hasInstrSchedModel()) {
 329     const MCSchedClassDesc &SCDesc = *SchedModel.getSchedClassDesc(SchedClass);
 330     if (SCDesc.isValid() && !SCDesc.isVariant())
 331       return MCSchedModel::getReciprocalThroughput(*STI, SCDesc);
 332   }
 333
 334   return 0.0;
 335 }
 336
 337 double
 338 TargetSchedModel::computeReciprocalThroughput(const MCInst &MI) const {
 339   if (hasInstrSchedModel())
 340     return SchedModel.getReciprocalThroughput(*STI, *TII, MI);
 341   return computeReciprocalThroughput(MI.getOpcode());
 342 }
 343
 344 bool TargetSchedModel::enableIntervals() const {
 345   if (ForceEnableIntervals)
 346     return true;
 347
 348   return SchedModel.EnableIntervals;
 349 }