Revert " [LoongArch][ISel] Check the number of sign bits in `PatGprGpr_32` (#107432)"
[llvm-project.git] / llvm / lib / Target / AMDGPU / AMDGPUCallLowering.h
bloba6e801f2a547b532b9ede4daf5d9afab275bdffe
1 //===- lib/Target/AMDGPU/AMDGPUCallLowering.h - Call lowering -*- C++ -*---===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file describes how to lower LLVM calls to machine code calls.
11 ///
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUCALLLOWERING_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUCALLLOWERING_H
17 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
19 namespace llvm {
21 class AMDGPUTargetLowering;
22 class GCNSubtarget;
23 class MachineInstrBuilder;
24 class SIMachineFunctionInfo;
26 class AMDGPUCallLowering final : public CallLowering {
27 void lowerParameterPtr(Register DstReg, MachineIRBuilder &B,
28 uint64_t Offset) const;
30 void lowerParameter(MachineIRBuilder &B, ArgInfo &AI, uint64_t Offset,
31 Align Alignment) const;
33 bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv,
34 SmallVectorImpl<BaseArgInfo> &Outs,
35 bool IsVarArg) const override;
37 bool lowerReturnVal(MachineIRBuilder &B, const Value *Val,
38 ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
40 public:
41 AMDGPUCallLowering(const AMDGPUTargetLowering &TLI);
43 bool lowerReturn(MachineIRBuilder &B, const Value *Val,
44 ArrayRef<Register> VRegs,
45 FunctionLoweringInfo &FLI) const override;
47 bool lowerFormalArgumentsKernel(MachineIRBuilder &B, const Function &F,
48 ArrayRef<ArrayRef<Register>> VRegs) const;
50 bool lowerFormalArguments(MachineIRBuilder &B, const Function &F,
51 ArrayRef<ArrayRef<Register>> VRegs,
52 FunctionLoweringInfo &FLI) const override;
54 bool passSpecialInputs(MachineIRBuilder &MIRBuilder,
55 CCState &CCInfo,
56 SmallVectorImpl<std::pair<MCRegister, Register>> &ArgRegs,
57 CallLoweringInfo &Info) const;
59 bool
60 doCallerAndCalleePassArgsTheSameWay(CallLoweringInfo &Info,
61 MachineFunction &MF,
62 SmallVectorImpl<ArgInfo> &InArgs) const;
64 bool
65 areCalleeOutgoingArgsTailCallable(CallLoweringInfo &Info, MachineFunction &MF,
66 SmallVectorImpl<ArgInfo> &OutArgs) const;
68 /// Returns true if the call can be lowered as a tail call.
69 bool
70 isEligibleForTailCallOptimization(MachineIRBuilder &MIRBuilder,
71 CallLoweringInfo &Info,
72 SmallVectorImpl<ArgInfo> &InArgs,
73 SmallVectorImpl<ArgInfo> &OutArgs) const;
75 void handleImplicitCallArguments(
76 MachineIRBuilder &MIRBuilder, MachineInstrBuilder &CallInst,
77 const GCNSubtarget &ST, const SIMachineFunctionInfo &MFI,
78 CallingConv::ID CalleeCC,
79 ArrayRef<std::pair<MCRegister, Register>> ImplicitArgRegs) const;
81 bool lowerTailCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
82 SmallVectorImpl<ArgInfo> &OutArgs) const;
83 bool lowerChainCall(MachineIRBuilder &MIRBuilder,
84 CallLoweringInfo &Info) const;
85 bool lowerCall(MachineIRBuilder &MIRBuilder,
86 CallLoweringInfo &Info) const override;
88 static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
89 static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
91 } // End of namespace llvm;
92 #endif