llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h

   1 //===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 /// The AMDGPU TargetMachine interface definition for hw codegen targets.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
  15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
  16
  17 #include "GCNSubtarget.h"
  18 #include "llvm/CodeGen/TargetPassConfig.h"
  19 #include "llvm/Target/TargetMachine.h"
  20 #include <optional>
  21 #include <utility>
  22
  23 namespace llvm {
  24
  25 //===----------------------------------------------------------------------===//
  26 // AMDGPU Target Machine (R600+)
  27 //===----------------------------------------------------------------------===//
  28
  29 class AMDGPUTargetMachine : public LLVMTargetMachine {
  30 protected:
  31   std::unique_ptr<TargetLoweringObjectFile> TLOF;
  32
  33   StringRef getGPUName(const Function &F) const;
  34   StringRef getFeatureString(const Function &F) const;
  35
  36 public:
  37   static bool EnableLateStructurizeCFG;
  38   static bool EnableFunctionCalls;
  39   static bool EnableLowerModuleLDS;
  40   static bool DisableStructurizer;
  41
  42   AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
  43                       StringRef FS, const TargetOptions &Options,
  44                       std::optional<Reloc::Model> RM,
  45                       std::optional<CodeModel::Model> CM, CodeGenOptLevel OL);
  46   ~AMDGPUTargetMachine() override;
  47
  48   const TargetSubtargetInfo *getSubtargetImpl() const;
  49   const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override = 0;
  50
  51   TargetLoweringObjectFile *getObjFileLowering() const override {
  52     return TLOF.get();
  53   }
  54
  55   Error buildCodeGenPipeline(ModulePassManager &MPM, raw_pwrite_stream &Out,
  56                              raw_pwrite_stream *DwoOut,
  57                              CodeGenFileType FileType,
  58                              const CGPassBuilderOption &Opts,
  59                              PassInstrumentationCallbacks *PIC) override;
  60
  61   void registerPassBuilderCallbacks(PassBuilder &PB) override;
  62   void registerDefaultAliasAnalyses(AAManager &) override;
  63
  64   /// Get the integer value of a null pointer in the given address space.
  65   static int64_t getNullPointerValue(unsigned AddrSpace);
  66
  67   bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
  68
  69   unsigned getAssumedAddrSpace(const Value *V) const override;
  70
  71   std::pair<const Value *, unsigned>
  72   getPredicatedAddrSpace(const Value *V) const override;
  73
  74   unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override;
  75
  76   bool splitModule(Module &M, unsigned NumParts,
  77                    function_ref<void(std::unique_ptr<Module> MPart)>
  78                        ModuleCallback) override;
  79 };
  80
  81 //===----------------------------------------------------------------------===//
  82 // GCN Target Machine (SI+)
  83 //===----------------------------------------------------------------------===//
  84
  85 class GCNTargetMachine final : public AMDGPUTargetMachine {
  86 private:
  87   mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap;
  88
  89 public:
  90   GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
  91                    StringRef FS, const TargetOptions &Options,
  92                    std::optional<Reloc::Model> RM,
  93                    std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
  94                    bool JIT);
  95
  96   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
  97
  98   const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override;
  99
 100   TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
 101
 102   bool useIPRA() const override {
 103     return true;
 104   }
 105
 106   void registerMachineRegisterInfoCallback(MachineFunction &MF) const override;
 107
 108   MachineFunctionInfo *
 109   createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
 110                             const TargetSubtargetInfo *STI) const override;
 111
 112   yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
 113   yaml::MachineFunctionInfo *
 114   convertFuncInfoToYAML(const MachineFunction &MF) const override;
 115   bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
 116                                 PerFunctionMIParsingState &PFS,
 117                                 SMDiagnostic &Error,
 118                                 SMRange &SourceRange) const override;
 119 };
 120
 121 //===----------------------------------------------------------------------===//
 122 // AMDGPU Pass Setup
 123 //===----------------------------------------------------------------------===//
 124
 125 class AMDGPUPassConfig : public TargetPassConfig {
 126 public:
 127   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM);
 128
 129   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
 130     return getTM<AMDGPUTargetMachine>();
 131   }
 132
 133   ScheduleDAGInstrs *
 134   createMachineScheduler(MachineSchedContext *C) const override;
 135
 136   void addEarlyCSEOrGVNPass();
 137   void addStraightLineScalarOptimizationPasses();
 138   void addIRPasses() override;
 139   void addCodeGenPrepare() override;
 140   bool addPreISel() override;
 141   bool addInstSelector() override;
 142   bool addGCPasses() override;
 143
 144   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
 145
 146   /// Check if a pass is enabled given \p Opt option. The option always
 147   /// overrides defaults if explicitly used. Otherwise its default will
 148   /// be used given that a pass shall work at an optimization \p Level
 149   /// minimum.
 150   bool isPassEnabled(const cl::opt<bool> &Opt,
 151                      CodeGenOptLevel Level = CodeGenOptLevel::Default) const {
 152     if (Opt.getNumOccurrences())
 153       return Opt;
 154     if (TM->getOptLevel() < Level)
 155       return false;
 156     return Opt;
 157   }
 158 };
 159
 160 } // end namespace llvm
 161
 162 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H