1 //===-- AVRInstrInfo.td - AVR Instruction defs -------------*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the AVR instructions in TableGen format.
11 //===----------------------------------------------------------------------===//
13 include "AVRInstrFormats.td"
15 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
19 def SDT_AVRCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
20 def SDT_AVRCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
21 def SDT_AVRCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
22 def SDT_AVRWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
24 : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
25 def SDT_AVRCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDT_AVRTst : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
29 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
31 //===----------------------------------------------------------------------===//
32 // AVR Specific Node Definitions
33 //===----------------------------------------------------------------------===//
35 def AVRretglue : SDNode<"AVRISD::RET_GLUE", SDTNone,
36 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
37 def AVRretiglue : SDNode<"AVRISD::RETI_GLUE", SDTNone,
38 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
40 def AVRcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AVRCallSeqStart,
41 [SDNPHasChain, SDNPOutGlue]>;
42 def AVRcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AVRCallSeqEnd,
43 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
45 def AVRcall : SDNode<"AVRISD::CALL", SDT_AVRCall,
46 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>;
48 def AVRWrapper : SDNode<"AVRISD::WRAPPER", SDT_AVRWrapper>;
51 : SDNode<"AVRISD::BRCOND", SDT_AVRBrcond, [SDNPHasChain, SDNPInGlue]>;
52 def AVRcmp : SDNode<"AVRISD::CMP", SDT_AVRCmp, [SDNPOutGlue]>;
53 def AVRcmpc : SDNode<"AVRISD::CMPC", SDT_AVRCmp, [SDNPInGlue, SDNPOutGlue]>;
54 def AVRtst : SDNode<"AVRISD::TST", SDT_AVRTst, [SDNPOutGlue]>;
55 def AVRselectcc : SDNode<"AVRISD::SELECT_CC", SDT_AVRSelectCC, [SDNPInGlue]>;
58 def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>;
59 def AVRlsr : SDNode<"AVRISD::LSR", SDTIntUnaryOp>;
60 def AVRrol : SDNode<"AVRISD::ROL", SDTIntUnaryOp>;
61 def AVRror : SDNode<"AVRISD::ROR", SDTIntUnaryOp>;
62 def AVRasr : SDNode<"AVRISD::ASR", SDTIntUnaryOp>;
63 def AVRlslhi : SDNode<"AVRISD::LSLHI", SDTIntUnaryOp>;
64 def AVRlsrlo : SDNode<"AVRISD::LSRLO", SDTIntUnaryOp>;
65 def AVRasrlo : SDNode<"AVRISD::ASRLO", SDTIntUnaryOp>;
66 def AVRlslbn : SDNode<"AVRISD::LSLBN", SDTIntBinOp>;
67 def AVRlsrbn : SDNode<"AVRISD::LSRBN", SDTIntBinOp>;
68 def AVRasrbn : SDNode<"AVRISD::ASRBN", SDTIntBinOp>;
69 def AVRlslwn : SDNode<"AVRISD::LSLWN", SDTIntBinOp>;
70 def AVRlsrwn : SDNode<"AVRISD::LSRWN", SDTIntBinOp>;
71 def AVRasrwn : SDNode<"AVRISD::ASRWN", SDTIntBinOp>;
72 def AVRlslw : SDNode<"AVRISD::LSLW", SDTIntShiftDOp>;
73 def AVRlsrw : SDNode<"AVRISD::LSRW", SDTIntShiftDOp>;
74 def AVRasrw : SDNode<"AVRISD::ASRW", SDTIntShiftDOp>;
76 // Pseudo shift nodes for non-constant shift amounts.
77 def AVRlslLoop : SDNode<"AVRISD::LSLLOOP", SDTIntShiftOp>;
78 def AVRlsrLoop : SDNode<"AVRISD::LSRLOOP", SDTIntShiftOp>;
79 def AVRrolLoop : SDNode<"AVRISD::ROLLOOP", SDTIntShiftOp>;
80 def AVRrorLoop : SDNode<"AVRISD::RORLOOP", SDTIntShiftOp>;
81 def AVRasrLoop : SDNode<"AVRISD::ASRLOOP", SDTIntShiftOp>;
84 def AVRSwap : SDNode<"AVRISD::SWAP", SDTIntUnaryOp>;
86 //===----------------------------------------------------------------------===//
87 // AVR Operands, Complex Patterns and Transformations Definitions.
88 //===----------------------------------------------------------------------===//
90 def imm8_neg_XFORM : SDNodeXForm<imm, [{
91 return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i8);
94 def imm16_neg_XFORM : SDNodeXForm<imm, [{
95 return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i16);
98 def imm0_63_neg : PatLeaf<(imm), [{
99 int64_t val = -N->getSExtValue();
100 return val >= 0 && val < 64;
101 }], imm16_neg_XFORM>;
103 def uimm6 : PatLeaf<(imm), [{ return isUInt<6>(N->getZExtValue()); }]>;
105 // imm_com8_XFORM - Return the complement of a imm_com8 value
106 def imm_com8_XFORM : SDNodeXForm<imm, [{
107 return CurDAG->getTargetConstant(
108 ~((uint8_t) N->getZExtValue()), SDLoc(N), MVT::i8);
111 // imm_com8 - Match an immediate that is a complement
112 // of a 8-bit immediate.
113 // Note: this pattern doesn't require an encoder method and such, as it's
114 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
115 // is handled by the destination instructions, which use imm_com8.
116 def imm_com8_asmoperand : AsmOperandClass { let Name = "ImmCom8"; }
117 def imm_com8 : Operand<i8> { let ParserMatchClass = imm_com8_asmoperand; }
119 def ioaddr_XFORM : SDNodeXForm<imm, [{
120 uint8_t offset = Subtarget->getIORegisterOffset();
121 return CurDAG->getTargetConstant(
122 uint8_t(N->getZExtValue()) - offset, SDLoc(N), MVT::i8);
125 def iobitpos8_XFORM : SDNodeXForm<imm, [{
126 return CurDAG->getTargetConstant(
127 Log2_32(uint8_t(N->getZExtValue())), SDLoc(N), MVT::i8);
130 def iobitposn8_XFORM : SDNodeXForm<imm, [{
131 return CurDAG->getTargetConstant(
132 Log2_32(uint8_t(~N->getZExtValue())), SDLoc(N), MVT::i8);
135 def ioaddr8 : PatLeaf<(imm), [{
136 uint8_t offset = Subtarget->getIORegisterOffset();
137 uint64_t val = N->getZExtValue() - offset;
141 def lowioaddr8 : PatLeaf<(imm), [{
142 uint8_t offset = Subtarget->getIORegisterOffset();
143 uint64_t val = N->getZExtValue() - offset;
147 def ioaddr16 : PatLeaf<(imm), [{
148 uint8_t offset = Subtarget->getIORegisterOffset();
149 uint64_t val = N->getZExtValue() - offset;
153 def iobitpos8 : PatLeaf<(imm), [{
154 return isPowerOf2_32(uint8_t(N->getZExtValue()));
155 }], iobitpos8_XFORM>;
157 def iobitposn8 : PatLeaf<(imm), [{
158 return isPowerOf2_32(uint8_t(~N->getZExtValue()));
159 }], iobitposn8_XFORM>;
161 def MemriAsmOperand : AsmOperandClass {
163 let ParserMethod = "parseMemriOperand";
166 /// Address operand for `reg+imm` used by STD and LDD.
167 def memri : Operand<iPTR> {
168 let MIOperandInfo = (ops PTRDISPREGS, i16imm);
170 let PrintMethod = "printMemri";
171 let EncoderMethod = "encodeMemri";
172 let DecoderMethod = "decodeMemri";
174 let ParserMatchClass = MemriAsmOperand;
177 // Address operand for `SP+imm` used by STD{W}SPQRr
178 def memspi : Operand<iPTR> {
179 let MIOperandInfo = (ops GPRSP, i16imm);
180 let PrintMethod = "printMemspi";
183 def relbrtarget_7 : Operand<OtherVT> {
184 let PrintMethod = "printPCRelImm";
185 let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_7_pcrel>";
188 def brtarget_13 : Operand<OtherVT> {
189 let PrintMethod = "printPCRelImm";
190 let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>";
193 def rcalltarget_13 : Operand<i16> {
194 let PrintMethod = "printPCRelImm";
195 let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>";
198 // The target of a 22 or 16-bit call/jmp instruction.
199 def call_target : Operand<iPTR> {
200 let EncoderMethod = "encodeCallTarget";
201 let DecoderMethod = "decodeCallTarget";
204 // A 16-bit address (which can lead to an R_AVR_16 relocation).
205 def imm16 : Operand<i16> { let EncoderMethod = "encodeImm<AVR::fixup_16, 2>"; }
207 // A 7-bit address (which can lead to an R_AVR_LDS_STS_16 relocation).
208 def imm7tiny : Operand<i16> {
209 let EncoderMethod = "encodeImm<AVR::fixup_lds_sts_16, 0>";
212 /// A 6-bit immediate used in the ADIW/SBIW instructions.
213 def imm_arith6 : Operand<i16> {
214 let EncoderMethod = "encodeImm<AVR::fixup_6_adiw, 0>";
217 /// An 8-bit immediate inside an instruction with the same format
218 /// as the `LDI` instruction (the `FRdK` format).
219 def imm_ldi8 : Operand<i8> {
220 let EncoderMethod = "encodeImm<AVR::fixup_ldi, 0>";
223 /// A 5-bit port number used in SBIC and friends (the `FIOBIT` format).
224 def imm_port5 : Operand<i8> {
225 let EncoderMethod = "encodeImm<AVR::fixup_port5, 0>";
228 /// A 6-bit port number used in the `IN` instruction and friends (the
230 def imm_port6 : Operand<i8> {
231 let EncoderMethod = "encodeImm<AVR::fixup_port6, 0>";
234 // Addressing mode pattern reg+imm6
235 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], [SDNPWantRoot]>;
237 // AsmOperand class for a pointer register.
238 // Used with the LD/ST family of instructions.
239 // See FSTLD in AVRInstrFormats.td
240 def PtrRegAsmOperand : AsmOperandClass { let Name = "Reg"; }
242 // A special operand type for the LD/ST instructions.
243 // It converts the pointer register number into a two-bit field used in the
245 def LDSTPtrReg : Operand<i16> {
246 let MIOperandInfo = (ops PTRREGS);
247 let EncoderMethod = "encodeLDSTPtrReg";
249 let ParserMatchClass = PtrRegAsmOperand;
252 // A special operand type for the LDD/STD instructions.
253 // It behaves identically to the LD/ST version, except restricts
254 // the pointer registers to Y and Z.
255 def LDDSTDPtrReg : Operand<i16> {
256 let MIOperandInfo = (ops PTRDISPREGS);
257 let EncoderMethod = "encodeLDSTPtrReg";
259 let ParserMatchClass = PtrRegAsmOperand;
262 //===----------------------------------------------------------------------===//
263 // AVR predicates for subtarget features
264 //===----------------------------------------------------------------------===//
266 def HasSRAM : Predicate<"Subtarget->hasSRAM()">,
267 AssemblerPredicate<(all_of FeatureSRAM)>;
269 def HasJMPCALL : Predicate<"Subtarget->hasJMPCALL()">,
270 AssemblerPredicate<(all_of FeatureJMPCALL)>;
272 def HasIJMPCALL : Predicate<"Subtarget->hasIJMPCALL()">,
273 AssemblerPredicate<(all_of FeatureIJMPCALL)>;
275 def HasEIJMPCALL : Predicate<"Subtarget->hasEIJMPCALL()">,
276 AssemblerPredicate<(all_of FeatureEIJMPCALL)>;
278 def HasADDSUBIW : Predicate<"Subtarget->hasADDSUBIW()">,
279 AssemblerPredicate<(all_of FeatureADDSUBIW)>;
281 def HasSmallStack : Predicate<"Subtarget->HasSmallStack()">,
282 AssemblerPredicate<(all_of FeatureSmallStack)>;
284 def HasMOVW : Predicate<"Subtarget->hasMOVW()">,
285 AssemblerPredicate<(all_of FeatureMOVW)>;
287 def HasLPM : Predicate<"Subtarget->hasLPM()">,
288 AssemblerPredicate<(all_of FeatureLPM)>;
290 def HasLPMX : Predicate<"Subtarget->hasLPMX()">,
291 AssemblerPredicate<(all_of FeatureLPMX)>;
293 def HasELPM : Predicate<"Subtarget->hasELPM()">,
294 AssemblerPredicate<(all_of FeatureELPM)>;
296 def HasELPMX : Predicate<"Subtarget->hasELPMX()">,
297 AssemblerPredicate<(all_of FeatureELPMX)>;
299 def HasSPM : Predicate<"Subtarget->hasSPM()">,
300 AssemblerPredicate<(all_of FeatureSPM)>;
302 def HasSPMX : Predicate<"Subtarget->hasSPMX()">,
303 AssemblerPredicate<(all_of FeatureSPMX)>;
305 def HasDES : Predicate<"Subtarget->hasDES()">,
306 AssemblerPredicate<(all_of FeatureDES)>;
308 def SupportsRMW : Predicate<"Subtarget->supportsRMW()">,
309 AssemblerPredicate<(all_of FeatureRMW)>;
311 def SupportsMultiplication : Predicate<"Subtarget->supportsMultiplication()">,
312 AssemblerPredicate<(all_of FeatureMultiplication)>;
314 def HasBREAK : Predicate<"Subtarget->hasBREAK()">,
315 AssemblerPredicate<(all_of FeatureBREAK)>;
317 def HasTinyEncoding : Predicate<"Subtarget->hasTinyEncoding()">,
318 AssemblerPredicate<(all_of FeatureTinyEncoding)>;
320 def HasNonTinyEncoding : Predicate<"!Subtarget->hasTinyEncoding()">,
321 AssemblerPredicate<(any_of (not FeatureTinyEncoding))>;
323 // AVR specific condition code. These correspond to AVR_*_COND in
324 // AVRInstrInfo.td. They must be kept in synch.
325 def AVR_COND_EQ : PatLeaf<(i8 0)>;
326 def AVR_COND_NE : PatLeaf<(i8 1)>;
327 def AVR_COND_GE : PatLeaf<(i8 2)>;
328 def AVR_COND_LT : PatLeaf<(i8 3)>;
329 def AVR_COND_SH : PatLeaf<(i8 4)>;
330 def AVR_COND_LO : PatLeaf<(i8 5)>;
331 def AVR_COND_MI : PatLeaf<(i8 6)>;
332 def AVR_COND_PL : PatLeaf<(i8 7)>;
334 //===----------------------------------------------------------------------===//
335 //===----------------------------------------------------------------------===//
336 // AVR Instruction list
337 //===----------------------------------------------------------------------===//
338 //===----------------------------------------------------------------------===//
340 // ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into
341 // a stack adjustment and the codegen must know that they may modify the stack
342 // pointer before prolog-epilog rewriting occurs.
343 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
344 // sub / add which can clobber SREG.
345 let Defs = [SP, SREG], Uses = [SP] in {
346 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt, i16imm:$amt2),
348 [(AVRcallseq_start timm:$amt, timm:$amt2)]>;
350 // R31R30 is used to update SP. It is normally free because it is a
351 // call-clobbered register but it is necessary to set it as a def as the
352 // register allocator might use it in rare cases (for rematerialization, it
353 // seems). hasSideEffects needs to be set to true so this instruction isn't
355 let Defs = [R31R30], hasSideEffects = 1 in def ADJCALLSTACKUP
356 : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
357 "#ADJCALLSTACKUP", [(AVRcallseq_end timm:$amt1, timm:$amt2)]>;
360 //===----------------------------------------------------------------------===//
362 //===----------------------------------------------------------------------===//
363 let isCommutable = 1, Constraints = "$src = $rd", Defs = [SREG] in {
365 // Adds two 8-bit registers.
366 def ADDRdRr : FRdRr<0b0000, 0b11, (outs GPR8:$rd),(ins GPR8:$src, GPR8:$rr),
368 [(set i8:$rd, (add i8:$src, i8:$rr)), (implicit SREG)]>;
370 // ADDW Rd+1:Rd, Rr+1:Rr
371 // Pseudo instruction to add four 8-bit registers as two 16-bit values.
376 def ADDWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$src, DREGS:$rr),
378 [(set i16:$rd, (add i16:$src, i16:$rr)),
382 // Adds two 8-bit registers with carry.
384 def ADCRdRr : FRdRr<0b0001, 0b11, (outs GPR8:$rd), (ins GPR8:$src, GPR8:$rr),
386 [(set i8:$rd, (adde i8:$src, i8:$rr)), (implicit SREG)]>;
388 // ADCW Rd+1:Rd, Rr+1:Rr
389 // Pseudo instruction to add four 8-bit registers as two 16-bit values with
396 def ADCWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$src, DREGS:$rr),
398 [(set i16:$rd, (adde i16:$src, i16:$rr)),
402 // Adds an immediate 6-bit value K to Rd, placing the result in Rd.
403 def ADIWRdK : FWRdK<0b0, (outs IWREGS:$rd), (ins IWREGS :$src, imm_arith6:$k),
405 [(set i16:$rd, (add i16:$src, uimm6:$k)),
407 Requires<[HasADDSUBIW]>;
410 //===----------------------------------------------------------------------===//
412 //===----------------------------------------------------------------------===//
413 let Constraints = "$rs = $rd", Defs = [SREG] in {
415 // Subtracts the 8-bit value of Rr from Rd and places the value in Rd.
416 def SUBRdRr : FRdRr<0b0001, 0b10, (outs GPR8:$rd), (ins GPR8:$rs, GPR8:$rr),
418 [(set i8:$rd, (sub i8:$rs, i8:$rr)), (implicit SREG)]>;
420 // SUBW Rd+1:Rd, Rr+1:Rr
421 // Subtracts two 16-bit values and places the result into Rd.
426 def SUBWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$rs, DREGS:$rr),
428 [(set i16:$rd, (sub i16:$rs, i16:$rr)),
431 def SUBIRdK : FRdK<0b0101, (outs LD8:$rd), (ins LD8:$rs, imm_ldi8:$k),
433 [(set i8:$rd, (sub i8:$rs, imm:$k)), (implicit SREG)]>;
435 // SUBIW Rd+1:Rd, K+1:K
440 def SUBIWRdK : Pseudo<(outs DLDREGS:$rd), (ins DLDREGS:$rs, i16imm:$rr),
442 [(set i16:$rd, (sub i16:$rs, imm:$rr)),
445 def SBIWRdK : FWRdK<0b1, (outs IWREGS:$rd), (ins IWREGS:$rs, imm_arith6:$k),
447 [(set i16:$rd, (sub i16:$rs, uimm6:$k)),
449 Requires<[HasADDSUBIW]>;
451 // Subtract with carry operations which must read the carry flag in SREG.
452 let Uses = [SREG] in {
453 def SBCRdRr : FRdRr<0b0000, 0b10, (outs GPR8:$rd), (ins GPR8:$rs, GPR8:$rr),
455 [(set i8:$rd, (sube i8:$rs, i8:$rr)), (implicit SREG)]>;
457 // SBCW Rd+1:Rd, Rr+1:Rr
462 def SBCWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$rs, DREGS:$rr),
464 [(set i16:$rd, (sube i16:$rs, i16:$rr)),
467 def SBCIRdK : FRdK<0b0100, (outs LD8:$rd), (ins LD8:$rs, imm_ldi8:$k),
469 [(set i8:$rd, (sube i8:$rs, imm:$k)), (implicit SREG)]>;
471 // SBCIW Rd+1:Rd, K+1:K
474 def SBCIWRdK : Pseudo<(outs DLDREGS:$rd), (ins DLDREGS:$rs, i16imm:$rr),
476 [(set i16:$rd, (sube i16:$rs, imm:$rr)),
481 //===----------------------------------------------------------------------===//
482 // Increment and Decrement
483 //===----------------------------------------------------------------------===//
484 let Constraints = "$src = $rd", Defs = [SREG] in {
485 def INCRd : FRd<0b1001, 0b0100011, (outs GPR8:$rd), (ins GPR8:$src),
487 [(set i8:$rd, (add i8:$src, 1)), (implicit SREG)]>;
489 def DECRd : FRd<0b1001, 0b0101010, (outs GPR8:$rd), (ins GPR8:$src),
491 [(set i8:$rd, (add i8:$src, -1)), (implicit SREG)]>;
494 //===----------------------------------------------------------------------===//
496 //===----------------------------------------------------------------------===//
498 let isCommutable = 1, Defs = [R1, R0, SREG] in {
500 // Multiplies Rd by Rr and places the result into R1:R0.
501 let usesCustomInserter = 1 in {
502 def MULRdRr : FRdRr<0b1001, 0b11, (outs), (ins GPR8:$rd, GPR8:$rr),
503 "mul\t$rd, $rr", []>,
504 Requires<[SupportsMultiplication]>;
506 def MULSRdRr : FMUL2RdRr<0, (outs), (ins LD8:$rd, LD8:$rr),
507 "muls\t$rd, $rr", []>,
508 Requires<[SupportsMultiplication]>;
511 def MULSURdRr : FMUL2RdRr<1, (outs), (ins LD8lo:$rd, LD8lo:$rr),
512 "mulsu\t$rd, $rr", []>,
513 Requires<[SupportsMultiplication]>;
515 def FMUL : FFMULRdRr<0b01, (outs), (ins LD8lo:$rd, LD8lo:$rr),
516 "fmul\t$rd, $rr", []>,
517 Requires<[SupportsMultiplication]>;
519 def FMULS : FFMULRdRr<0b10, (outs), (ins LD8lo:$rd, LD8lo:$rr),
520 "fmuls\t$rd, $rr", []>,
521 Requires<[SupportsMultiplication]>;
523 def FMULSU : FFMULRdRr<0b11, (outs), (ins LD8lo:$rd, LD8lo:$rr),
524 "fmulsu\t$rd, $rr", []>,
525 Requires<[SupportsMultiplication]>;
529 [R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R1, R0] in
530 def DESK : FDES<(outs), (ins i8imm:$k), "des\t$k", []>, Requires<[HasDES]>;
532 //===----------------------------------------------------------------------===//
534 //===----------------------------------------------------------------------===//
535 let Constraints = "$src = $rd", Defs = [SREG] in {
536 // Register-Register logic instructions (which have the
537 // property of commutativity).
538 let isCommutable = 1 in {
539 def ANDRdRr : FRdRr<0b0010, 0b00, (outs GPR8:$rd),
540 (ins GPR8:$src, GPR8:$rr), "and\t$rd, $rr",
541 [(set i8:$rd, (and i8:$src, i8:$rr)), (implicit SREG)]>;
543 // ANDW Rd+1:Rd, Rr+1:Rr
548 def ANDWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$src, DREGS:$rr),
550 [(set i16:$rd, (and i16:$src, i16:$rr)),
553 def ORRdRr : FRdRr<0b0010, 0b10, (outs GPR8:$rd), (ins GPR8:$src, GPR8:$rr),
555 [(set i8:$rd, (or i8:$src, i8:$rr)), (implicit SREG)]>;
557 // ORW Rd+1:Rd, Rr+1:Rr
562 def ORWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$src, DREGS:$rr),
564 [(set i16:$rd, (or i16:$src, i16:$rr)),
567 def EORRdRr : FRdRr<0b0010, 0b01, (outs GPR8:$rd),
568 (ins GPR8:$src, GPR8:$rr), "eor\t$rd, $rr",
569 [(set i8:$rd, (xor i8:$src, i8:$rr)), (implicit SREG)]>;
571 // EORW Rd+1:Rd, Rr+1:Rr
576 def EORWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$src, DREGS:$rr),
578 [(set i16:$rd, (xor i16:$src, i16:$rr)),
582 def ANDIRdK : FRdK<0b0111, (outs LD8:$rd), (ins LD8:$src, imm_ldi8:$k),
584 [(set i8:$rd, (and i8:$src, imm:$k)), (implicit SREG)]>;
586 // ANDI Rd+1:Rd, K+1:K
591 def ANDIWRdK : Pseudo<(outs DLDREGS:$rd), (ins DLDREGS:$src, i16imm:$k),
593 [(set i16:$rd, (and i16:$src, imm:$k)),
596 def ORIRdK : FRdK<0b0110, (outs LD8:$rd), (ins LD8:$src, imm_ldi8:$k),
598 [(set i8:$rd, (or i8:$src, imm:$k)), (implicit SREG)]>;
600 // ORIW Rd+1:Rd, K+1,K
605 def ORIWRdK : Pseudo<(outs DLDREGS:$rd), (ins DLDREGS:$src, i16imm:$rr),
607 [(set i16:$rd, (or i16:$src, imm:$rr)),
611 //===----------------------------------------------------------------------===//
612 // One's/Two's Complement
613 //===----------------------------------------------------------------------===//
614 let Constraints = "$src = $rd", Defs = [SREG] in {
615 def COMRd : FRd<0b1001, 0b0100000, (outs GPR8:$rd), (ins GPR8:$src),
616 "com\t$rd", [(set i8:$rd, (not i8:$src)), (implicit SREG)]>;
623 def COMWRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "comw\t$rd",
624 [(set i16:$rd, (not i16:$src)), (implicit SREG)]>;
626 def NEGRd : FRd<0b1001, 0b0100001, (outs GPR8:$rd), (ins GPR8:$src),
627 "neg\t$rd", [(set i8:$rd, (ineg i8:$src)), (implicit SREG)]>;
635 let hasSideEffects=0 in
636 def NEGWRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src, GPR8:$zero),
641 // Test for zero of minus.
642 // This operation is identical to a `Rd AND Rd`.
643 def : InstAlias<"tst\t$rd", (ANDRdRr GPR8:$rd, GPR8:$rd)>;
647 // Mnemonic alias to 'ORI Rd, K'. Same bit pattern, same operands,
649 def : InstAlias<"sbr\t$rd, $k", (ORIRdK LD8:$rd, imm_ldi8:$k),
650 /* Disable display, so we don't override ORI */ 0>;
652 //===----------------------------------------------------------------------===//
654 //===----------------------------------------------------------------------===//
655 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
656 def RJMPk : FBRk<0, (outs), (ins brtarget_13:$k), "rjmp\t$k", [(br bb:$k)]>;
658 let isIndirectBranch = 1, Uses = [R31R30] in
659 def IJMP : F16<0b1001010000001001, (outs), (ins), "ijmp", []>,
660 Requires<[HasIJMPCALL]>;
662 let isIndirectBranch = 1, Uses = [R31R30] in
663 def EIJMP : F16<0b1001010000011001, (outs), (ins), "eijmp", []>,
664 Requires<[HasEIJMPCALL]>;
666 def JMPk : F32BRk<0b110, (outs), (ins call_target:$k), "jmp\t$k", []>,
667 Requires<[HasJMPCALL]>;
670 //===----------------------------------------------------------------------===//
672 //===----------------------------------------------------------------------===//
674 // SP is marked as a use to prevent stack-pointer assignments that appear
675 // immediately before calls from potentially appearing dead.
677 def RCALLk : FBRk<1, (outs), (ins rcalltarget_13:$k), "rcall\t$k",
680 // SP is marked as a use to prevent stack-pointer assignments that appear
681 // immediately before calls from potentially appearing dead.
682 let Uses = [SP, R31R30] in
683 def ICALL : F16<0b1001010100001001, (outs), (ins variable_ops), "icall", []>,
684 Requires<[HasIJMPCALL]>;
686 // SP is marked as a use to prevent stack-pointer assignments that appear
687 // immediately before calls from potentially appearing dead.
688 let Uses = [SP, R31R30] in
689 def EICALL : F16<0b1001010100011001, (outs), (ins variable_ops), "eicall",
691 Requires<[HasEIJMPCALL]>;
693 // SP is marked as a use to prevent stack-pointer assignments that appear
694 // immediately before calls from potentially appearing dead.
696 // TODO: the imm field can be either 16 or 22 bits in devices with more
697 // than 64k of ROM, fix it once we support the largest devices.
699 def CALLk : F32BRk<0b111, (outs), (ins call_target:$k), "call\t$k",
701 Requires<[HasJMPCALL]>;
704 //===----------------------------------------------------------------------===//
705 // Return instructions.
706 //===----------------------------------------------------------------------===//
707 let isTerminator = 1, isReturn = 1, isBarrier = 1 in {
708 def RET : F16<0b1001010100001000, (outs), (ins), "ret", [(AVRretglue)]>;
710 def RETI : F16<0b1001010100011000, (outs), (ins), "reti", [(AVRretiglue)]>;
713 //===----------------------------------------------------------------------===//
714 // Compare operations.
715 //===----------------------------------------------------------------------===//
716 let Defs = [SREG] in {
718 // Compare Rd and Rr, skipping the next instruction if they are equal.
719 let isBarrier = 1, isBranch = 1, isTerminator = 1 in
720 def CPSE : FRdRr<0b0001, 0b00, (outs), (ins GPR8:$rd, GPR8:$rr),
721 "cpse\t$rd, $rr", []>;
723 def CPRdRr : FRdRr<0b0001, 0b01, (outs), (ins GPR8:$rd, GPR8:$rr),
725 [(AVRcmp i8:$rd, i8:$rr), (implicit SREG)]>;
727 // CPW Rd+1:Rd, Rr+1:Rr
732 def CPWRdRr : Pseudo<(outs), (ins DREGS:$src, DREGS:$src2),
734 [(AVRcmp i16:$src, i16:$src2), (implicit SREG)]>;
737 def CPCRdRr : FRdRr<0b0000, 0b01, (outs), (ins GPR8:$rd, GPR8:$rr),
739 [(AVRcmpc i8:$rd, i8:$rr), (implicit SREG)]>;
741 // CPCW Rd+1:Rd. Rr+1:Rr
747 def CPCWRdRr : Pseudo<(outs), (ins DREGS:$src, DREGS:$src2),
749 [(AVRcmpc i16:$src, i16:$src2), (implicit SREG)]>;
752 // Compares a register with an 8 bit immediate.
753 def CPIRdK : FRdK<0b0011, (outs), (ins LD8:$rd, imm_ldi8:$k), "cpi\t$rd, $k",
754 [(AVRcmp i8:$rd, imm:$k), (implicit SREG)]>;
757 //===----------------------------------------------------------------------===//
758 // Register conditional skipping/branching operations.
759 //===----------------------------------------------------------------------===//
760 let isBranch = 1, isTerminator = 1 in {
761 // Conditional skipping on GPR register bits, and
762 // conditional skipping on IO register bits.
763 let isBarrier = 1 in {
764 def SBRCRrB : FRdB<0b10, (outs), (ins GPR8:$rd, i8imm:$b), "sbrc\t$rd, $b",
767 def SBRSRrB : FRdB<0b11, (outs), (ins GPR8:$rd, i8imm:$b), "sbrs\t$rd, $b",
770 def SBICAb : FIOBIT<0b01, (outs), (ins imm_port5:$addr, i8imm:$b),
771 "sbic\t$addr, $b", []>;
773 def SBISAb : FIOBIT<0b11, (outs), (ins imm_port5:$addr, i8imm:$b),
774 "sbis\t$addr, $b", []>;
777 // Relative branches on status flag bits.
778 let Uses = [SREG] in {
780 // Branch if `s` flag in status register is set.
781 def BRBSsk : FSK<0, (outs), (ins i8imm:$s, relbrtarget_7:$k),
785 // Branch if `s` flag in status register is clear.
786 def BRBCsk : FSK<1, (outs), (ins i8imm:$s, relbrtarget_7:$k),
792 // Branch if carry flag is set
793 def : InstAlias<"brcs\t$k", (BRBSsk 0, relbrtarget_7 : $k)>;
796 // Branch if carry flag is clear
797 def : InstAlias<"brcc\t$k", (BRBCsk 0, relbrtarget_7 : $k)>;
800 // Branch if half carry flag is set
801 def : InstAlias<"brhs\t$k", (BRBSsk 5, relbrtarget_7 : $k)>;
804 // Branch if half carry flag is clear
805 def : InstAlias<"brhc\t$k", (BRBCsk 5, relbrtarget_7 : $k)>;
808 // Branch if the T flag is set
809 def : InstAlias<"brts\t$k", (BRBSsk 6, relbrtarget_7 : $k)>;
812 // Branch if the T flag is clear
813 def : InstAlias<"brtc\t$k", (BRBCsk 6, relbrtarget_7 : $k)>;
816 // Branch if the overflow flag is set
817 def : InstAlias<"brvs\t$k", (BRBSsk 3, relbrtarget_7 : $k)>;
820 // Branch if the overflow flag is clear
821 def : InstAlias<"brvc\t$k", (BRBCsk 3, relbrtarget_7 : $k)>;
824 // Branch if the global interrupt flag is enabled
825 def : InstAlias<"brie\t$k", (BRBSsk 7, relbrtarget_7 : $k)>;
828 // Branch if the global interrupt flag is disabled
829 def : InstAlias<"brid\t$k", (BRBCsk 7, relbrtarget_7 : $k)>;
831 //===----------------------------------------------------------------------===//
832 // PC-relative conditional branches
833 //===----------------------------------------------------------------------===//
834 // Based on status register. We cannot simplify these into instruction aliases
835 // because we also need to be able to specify a pattern to match for ISel.
836 let isBranch = 1, isTerminator = 1, Uses = [SREG] in {
837 def BREQk : FBRsk<0, 0b001, (outs), (ins relbrtarget_7:$k), "breq\t$k",
838 [(AVRbrcond bb:$k, AVR_COND_EQ)]>;
840 def BRNEk : FBRsk<1, 0b001, (outs), (ins relbrtarget_7:$k), "brne\t$k",
841 [(AVRbrcond bb:$k, AVR_COND_NE)]>;
843 def BRSHk : FBRsk<1, 0b000, (outs), (ins relbrtarget_7:$k), "brsh\t$k",
844 [(AVRbrcond bb:$k, AVR_COND_SH)]>;
846 def BRLOk : FBRsk<0, 0b000, (outs), (ins relbrtarget_7:$k), "brlo\t$k",
847 [(AVRbrcond bb:$k, AVR_COND_LO)]>;
849 def BRMIk : FBRsk<0, 0b010, (outs), (ins relbrtarget_7:$k), "brmi\t$k",
850 [(AVRbrcond bb:$k, AVR_COND_MI)]>;
852 def BRPLk : FBRsk<1, 0b010, (outs), (ins relbrtarget_7:$k), "brpl\t$k",
853 [(AVRbrcond bb:$k, AVR_COND_PL)]>;
855 def BRGEk : FBRsk<1, 0b100, (outs), (ins relbrtarget_7:$k), "brge\t$k",
856 [(AVRbrcond bb:$k, AVR_COND_GE)]>;
858 def BRLTk : FBRsk<0, 0b100, (outs), (ins relbrtarget_7:$k), "brlt\t$k",
859 [(AVRbrcond bb:$k, AVR_COND_LT)]>;
862 //===----------------------------------------------------------------------===//
863 // Data transfer instructions
864 //===----------------------------------------------------------------------===//
865 // 8 and 16-bit register move instructions.
866 let hasSideEffects = 0 in {
867 def MOVRdRr : FRdRr<0b0010, 0b11, (outs GPR8:$rd), (ins GPR8:$rr),
868 "mov\t$rd, $rr", []>;
870 def MOVWRdRr : FMOVWRdRr<(outs DREGS:$rd), (ins DREGS:$rr), "movw\t$rd, $rr",
875 // Load immediate values into registers.
876 let isReMaterializable = 1 in {
877 def LDIRdK : FRdK<0b1110, (outs LD8:$rd), (ins imm_ldi8:$k), "ldi\t$rd, $k",
878 [(set i8:$rd, imm:$k)]>;
880 // LDIW Rd+1:Rd, K+1:K
885 def LDIWRdK : Pseudo<(outs DLDREGS:$dst), (ins i16imm:$src),
886 "ldiw\t$dst, $src", [(set i16:$dst, imm:$src)]>;
889 // Load from data space into register.
890 let canFoldAsLoad = 1, isReMaterializable = 1 in {
891 def LDSRdK : F32DM<0b0, (outs GPR8:$rd), (ins imm16:$k), "lds\t$rd, $k",
892 [(set i8:$rd, (load imm:$k))]>,
893 Requires<[HasSRAM, HasNonTinyEncoding]>;
895 // Load from data space into register, which is only available on AVRTiny.
896 def LDSRdKTiny : FLDSSTSTINY<0b0, (outs LD8:$rd), (ins imm7tiny:$k),
897 "lds\t$rd, $k", [(set i8:$rd, (load imm:$k))]>,
898 Requires<[HasSRAM, HasTinyEncoding]>;
900 // LDSW Rd+1:Rd, K+1:K
904 // lds Rd+1 (K+1:K) + 1
905 def LDSWRdK : Pseudo<(outs DREGS:$dst), (ins i16imm:$src), "ldsw\t$dst, $src",
906 [(set i16:$dst, (load imm:$src))]>,
907 Requires<[HasSRAM, HasNonTinyEncoding]>;
911 let canFoldAsLoad = 1, isReMaterializable = 1 in {
912 def LDRdPtr : FSTLD<0, 0b00, (outs GPR8:$reg), (ins LDSTPtrReg:$ptrreg),
914 [(set GPR8:$reg, (load i16:$ptrreg))]>,
922 // On reduced tiny cores, this instruction expands to:
926 let Constraints = "@earlyclobber $reg" in def LDWRdPtr
927 : Pseudo<(outs DREGS:$reg), (ins PTRDISPREGS:$ptrreg),
928 "ldw\t$reg, $ptrreg", [(set i16:$reg, (load i16:$ptrreg))]>,
932 // Indirect loads (with postincrement or predecrement).
933 let mayLoad = 1, hasSideEffects = 0,
934 Constraints = "$ptrreg = $base_wb,@earlyclobber $reg" in {
935 def LDRdPtrPi : FSTLD<0, 0b01,
941 "ld\t$reg, $ptrreg+", []>,
948 def LDWRdPtrPi : Pseudo<(outs DREGS:$reg, PTRREGS:$base_wb),
949 (ins PTRREGS:$ptrreg), "ldw\t$reg, $ptrreg+", []>,
952 def LDRdPtrPd : FSTLD<0, 0b10, (outs GPR8:$reg, PTRREGS:$base_wb),
953 (ins LDSTPtrReg:$ptrreg), "ld\t$reg, -$ptrreg", []>,
961 def LDWRdPtrPd : Pseudo<(outs DREGS:$reg, PTRREGS:$base_wb),
962 (ins PTRREGS:$ptrreg), "ldw\t$reg, -$ptrreg", []>,
966 // Load indirect with displacement operations.
967 let canFoldAsLoad = 1, isReMaterializable = 1 in {
968 def LDDRdPtrQ : FSTDLDD<0, (outs GPR8:$reg), (ins memri:$memri),
970 [(set i8:$reg, (load addr:$memri))]>,
971 Requires<[HasSRAM, HasNonTinyEncoding]>;
978 // On reduced tiny cores, this instruction expands to:
983 let Constraints = "@earlyclobber $dst" in
984 def LDDWRdPtrQ : Pseudo<(outs DREGS:$dst), (ins memri:$memri),
985 "lddw\t$dst, $memri",
986 [(set i16:$dst, (load addr:$memri))]>,
989 // An identical pseudo instruction to LDDWRdPtrQ, expect restricted to the Y
990 // register and without the @earlyclobber flag.
992 // Used to work around a bug caused by the register allocator not
993 // being able to handle the expansion of a COPY into an machine instruction
994 // that has an earlyclobber flag. This is because the register allocator will
995 // try expand a copy from a register slot into an earlyclobber instruction.
996 // Instructions that are earlyclobber need to be in a dedicated earlyclobber
999 // This pseudo instruction can be used pre-AVR pseudo expansion in order to
1000 // get a frame index load without directly using earlyclobber instructions.
1002 // The pseudo expansion pass trivially expands this into LDDWRdPtrQ.
1004 // This instruction may be removed once PR13375 is fixed.
1005 let mayLoad = 1, hasSideEffects = 0 in
1006 def LDDWRdYQ : Pseudo<(outs DREGS:$dst), (ins memri:$memri),
1007 "lddw\t$dst, $memri", []>,
1008 Requires<[HasSRAM]>;
1011 class AtomicLoad<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>
1012 : Pseudo<(outs DRC:$rd), (ins PTRRC:$rr), "atomic_op",
1013 [(set DRC:$rd, (Op i16:$rr))]>;
1015 class AtomicStore<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>
1016 : Pseudo<(outs), (ins PTRRC:$rd, DRC:$rr), "atomic_op",
1017 [(Op DRC:$rr, i16:$rd)]>;
1019 class AtomicLoadOp<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>
1020 : Pseudo<(outs DRC:$rd), (ins PTRRC:$rr, DRC:$operand), "atomic_op",
1021 [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>;
1023 // Atomic instructions
1024 // ===================
1026 // 8-bit operations can use any pointer register because
1027 // they are expanded directly into an LD/ST instruction.
1029 // 16-bit operations use 16-bit load/store postincrement instructions,
1030 // which require PTRDISPREGS.
1032 def AtomicLoad8 : AtomicLoad<atomic_load_8, GPR8, PTRREGS>;
1033 def AtomicLoad16 : AtomicLoad<atomic_load_16, DREGS, PTRDISPREGS>;
1035 def AtomicStore8 : AtomicStore<atomic_store_8, GPR8, PTRREGS>;
1036 def AtomicStore16 : AtomicStore<atomic_store_16, DREGS, PTRDISPREGS>;
1038 class AtomicLoadOp8<PatFrag Op> : AtomicLoadOp<Op, GPR8, PTRREGS>;
1039 class AtomicLoadOp16<PatFrag Op> : AtomicLoadOp<Op, DREGS, PTRDISPREGS>;
1041 let usesCustomInserter=1 in {
1042 def AtomicLoadAdd8 : AtomicLoadOp8<atomic_load_add_i8>;
1043 def AtomicLoadAdd16 : AtomicLoadOp16<atomic_load_add_i16>;
1044 def AtomicLoadSub8 : AtomicLoadOp8<atomic_load_sub_i8>;
1045 def AtomicLoadSub16 : AtomicLoadOp16<atomic_load_sub_i16>;
1046 def AtomicLoadAnd8 : AtomicLoadOp8<atomic_load_and_i8>;
1047 def AtomicLoadAnd16 : AtomicLoadOp16<atomic_load_and_i16>;
1048 def AtomicLoadOr8 : AtomicLoadOp8<atomic_load_or_i8>;
1049 def AtomicLoadOr16 : AtomicLoadOp16<atomic_load_or_i16>;
1050 def AtomicLoadXor8 : AtomicLoadOp8<atomic_load_xor_i8>;
1051 def AtomicLoadXor16 : AtomicLoadOp16<atomic_load_xor_i16>;
1055 : Pseudo<(outs), (ins), "atomic_fence", [(atomic_fence timm, timm)]>;
1057 // Indirect store from register to data space.
1058 def STSKRr : F32DM<0b1, (outs), (ins imm16:$k, GPR8:$rd), "sts\t$k, $rd",
1059 [(store i8:$rd, imm:$k)]>,
1060 Requires<[HasSRAM, HasNonTinyEncoding]>;
1062 // Store from register to data space, which is only available on AVRTiny.
1063 def STSKRrTiny : FLDSSTSTINY<0b1, (outs), (ins imm7tiny:$k, LD8:$rd),
1064 "sts\t$k, $rd", [(store i8:$rd, imm:$k)]>,
1065 Requires<[HasSRAM, HasTinyEncoding]>;
1067 // STSW K+1:K, Rr+1:Rr
1070 // sts Rr+1, (K+1:K) + 1
1072 def STSWKRr : Pseudo<(outs), (ins i16imm:$dst, DREGS:$src),
1073 "stsw\t$dst, $src", [(store i16:$src, imm:$dst)]>,
1074 Requires<[HasSRAM, HasNonTinyEncoding]>;
1078 // Stores the value of Rr into the location addressed by pointer P.
1079 def STPtrRr : FSTLD<1, 0b00, (outs), (ins LDSTPtrReg:$ptrreg, GPR8:$reg),
1080 "st\t$ptrreg, $reg", [(store GPR8:$reg, i16:$ptrreg)]>,
1081 Requires<[HasSRAM]>;
1084 // Stores the value of Rr into the location addressed by pointer P.
1089 // On reduced tiny cores, this instruction expands to:
1093 def STWPtrRr : Pseudo<(outs), (ins PTRDISPREGS:$ptrreg, DREGS:$reg),
1094 "stw\t$ptrreg, $reg", [(store i16:$reg, i16:$ptrreg)]>,
1095 Requires<[HasSRAM]>;
1097 // Indirect stores (with postincrement or predecrement).
1098 let Constraints = "$ptrreg = $base_wb,@earlyclobber $base_wb" in {
1101 // Stores the value of Rr into the location addressed by pointer P.
1102 // Post increments P.
1103 def STPtrPiRr : FSTLD<1, 0b01, (outs LDSTPtrReg:$base_wb),
1104 (ins LDSTPtrReg:$ptrreg, GPR8:$reg, i8imm:$offs),
1105 "st\t$ptrreg+, $reg",
1106 [(set i16:$base_wb, (post_store GPR8:$reg, i16:$ptrreg,
1108 Requires<[HasSRAM]>;
1111 // Stores the value of Rr into the location addressed by pointer P.
1112 // Post increments P.
1117 def STWPtrPiRr : Pseudo<(outs PTRREGS:$base_wb),
1118 (ins PTRREGS:$ptrreg, DREGS:$trh, i8imm:$offs),
1119 "stw\t$ptrreg+, $trh",
1120 [(set PTRREGS:$base_wb,
1121 (post_store DREGS:$trh, PTRREGS:$ptrreg,
1123 Requires<[HasSRAM]>;
1126 // Stores the value of Rr into the location addressed by pointer P.
1127 // Pre decrements P.
1128 def STPtrPdRr : FSTLD<1, 0b10, (outs LDSTPtrReg:$base_wb),
1129 (ins LDSTPtrReg:$ptrreg, GPR8:$reg, i8imm:$offs),
1130 "st\t-$ptrreg, $reg",
1131 [(set i16: $base_wb,
1132 (pre_store GPR8:$reg, i16:$ptrreg, imm:$offs))]>,
1133 Requires<[HasSRAM]>;
1136 // Stores the value of Rr into the location addressed by pointer P.
1137 // Pre decrements P.
1142 def STWPtrPdRr : Pseudo<(outs PTRREGS:$base_wb),
1143 (ins PTRREGS:$ptrreg, DREGS:$reg, i8imm:$offs),
1144 "stw\t-$ptrreg, $reg",
1145 [(set PTRREGS:$base_wb,
1146 (pre_store i16:$reg, i16:$ptrreg, imm:$offs))]>,
1147 Requires<[HasSRAM]>;
1150 // Store indirect with displacement operations.
1152 // Stores the value of Rr into the location addressed by pointer P with a
1153 // displacement of q. Does not modify P.
1154 def STDPtrQRr : FSTDLDD<1, (outs), (ins memri:$memri, GPR8:$reg),
1155 "std\t$memri, $reg", [(store i8:$reg, addr:$memri)]>,
1156 Requires<[HasSRAM, HasNonTinyEncoding]>;
1158 // STDW P+q, Rr+1:Rr
1159 // Stores the value of Rr into the location addressed by pointer P with a
1160 // displacement of q. Does not modify P.
1165 // On reduced tiny cores, this instruction expands to:
1170 def STDWPtrQRr : Pseudo<(outs), (ins memri:$memri, DREGS:$src),
1171 "stdw\t$memri, $src", [(store i16:$src, addr:$memri)]>,
1172 Requires<[HasSRAM]>;
1174 // Load program memory operations.
1175 let canFoldAsLoad = 1, isReMaterializable = 1, mayLoad = 1,
1176 hasSideEffects = 0 in {
1178 Uses = [R31R30] in def LPM
1179 : F16<0b1001010111001000, (outs), (ins), "lpm", []>,
1182 // These pseudo instructions are combination of the OUT and LPM instructions.
1183 let Defs = [R0] in {
1184 def LPMBRdZ : Pseudo<(outs GPR8:$dst), (ins ZREG:$z), "lpmb\t$dst, $z", []>,
1187 let Constraints = "@earlyclobber $dst" in
1188 def LPMWRdZ : Pseudo<(outs DREGS:$dst), (ins ZREG:$z), "lpmw\t$dst, $z", []>,
1192 def LPMRdZ : FLPMX<0, 0,
1197 "lpm\t$rd, $z", []>,
1198 Requires<[HasLPMX]>;
1200 // Load program memory, while postincrementing the Z register.
1201 let Defs = [R31R30] in {
1202 def LPMRdZPi : FLPMX<0, 1,
1207 "lpm\t$rd, $z+", []>,
1208 Requires<[HasLPMX]>;
1210 def LPMWRdZPi : Pseudo<(outs DREGS
1214 "lpmw\t$dst, $z+", []>,
1215 Requires<[HasLPMX]>;
1219 // Extended load program memory operations.
1220 let mayLoad = 1, hasSideEffects = 0 in {
1222 Uses = [R31R30] in def ELPM
1223 : F16<0b1001010111011000, (outs), (ins), "elpm", []>,
1224 Requires<[HasELPM]>;
1226 def ELPMRdZ : FLPMX<1, 0, (outs GPR8:$rd), (ins ZREG:$z),
1227 "elpm\t$rd, $z", []>,
1228 Requires<[HasELPMX]>;
1230 let Defs = [R31R30] in {
1231 def ELPMRdZPi : FLPMX<1, 1, (outs GPR8:$rd), (ins ZREG:$z),
1232 "elpm\t$rd, $z+", []>,
1233 Requires<[HasELPMX]>;
1236 // These pseudo instructions are combination of the OUT and ELPM instructions.
1237 let Defs = [R0] in {
1238 def ELPMBRdZ : Pseudo<(outs GPR8:$dst), (ins ZREG:$z, LD8:$p),
1239 "elpmb\t$dst, $z, $p", []>,
1240 Requires<[HasELPM]>;
1242 let Constraints = "@earlyclobber $dst" in
1243 def ELPMWRdZ : Pseudo<(outs DREGS:$dst), (ins ZREG:$z, LD8:$p),
1244 "elpmw\t$dst, $z, $p", []>,
1245 Requires<[HasELPM]>;
1248 // These pseudos are combination of the OUT and ELPM instructions.
1249 let Defs = [R31R30], hasSideEffects = 1 in {
1250 def ELPMBRdZPi : Pseudo<(outs GPR8:$dst), (ins ZREG:$z, LD8:$p),
1251 "elpmb\t$dst, $z+, $p", []>,
1252 Requires<[HasELPMX]>;
1254 def ELPMWRdZPi : Pseudo<(outs DREGS:$dst), (ins ZREG:$z, LD8:$p),
1255 "elpmw\t$dst, $z+, $p", []>,
1256 Requires<[HasELPMX]>;
1260 // Store program memory operations.
1261 let Uses = [R1, R0] in {
1262 let Uses = [R31R30, R1, R0] in def SPM
1263 : F16<0b1001010111101000, (outs), (ins), "spm", []>,
1266 let Defs = [R31R30] in def SPMZPi : F16<0b1001010111111000, (outs),
1270 Requires<[HasSPMX]>;
1273 // Read data from IO location operations.
1274 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1275 def INRdA : FIORdA<(outs GPR8
1279 "in\t$rd, $A", [(set i8
1280 : $rd, (load ioaddr8
1283 def INWRdA : Pseudo<(outs DREGS
1287 "inw\t$dst, $src", [(set i16
1288 : $dst, (load ioaddr16
1292 // Write data to IO location operations.
1293 def OUTARr : FIOARr<(outs),
1297 "out\t$A, $rr", [(store i8
1301 def OUTWARr : Pseudo<(outs),
1305 "outw\t$dst, $src", [(store i16
1309 // Stack push/pop operations.
1310 let Defs = [SP], Uses = [SP], hasSideEffects = 0 in {
1311 // Stack push operations.
1312 let mayStore = 1 in {
1313 def PUSHRr : FRd<0b1001, 0b0011111, (outs),
1317 Requires<[HasSRAM]>;
1319 def PUSHWRr : Pseudo<(outs),
1323 Requires<[HasSRAM]>;
1326 // Stack pop operations.
1327 let mayLoad = 1 in {
1328 def POPRd : FRd<0b1001, 0b0001111,
1331 (ins), "pop\t$rd", []>,
1332 Requires<[HasSRAM]>;
1334 def POPWRd : Pseudo<(outs DREGS
1336 (ins), "popw\t$reg", []>,
1337 Requires<[HasSRAM]>;
1341 // Read-Write-Modify (RMW) instructions.
1342 def XCHZRd : FZRd<0b100,
1347 "xch\t$z, $rd", []>,
1348 Requires<[SupportsRMW]>;
1350 def LASZRd : FZRd<0b101,
1355 "las\t$z, $rd", []>,
1356 Requires<[SupportsRMW]>;
1358 def LACZRd : FZRd<0b110,
1363 "lac\t$z, $rd", []>,
1364 Requires<[SupportsRMW]>;
1366 def LATZRd : FZRd<0b111,
1371 "lat\t$z, $rd", []>,
1372 Requires<[SupportsRMW]>;
1374 //===----------------------------------------------------------------------===//
1375 // Bit and bit-test instructions
1376 //===----------------------------------------------------------------------===//
1378 // Bit shift/rotate operations.
1379 let Constraints = "$src = $rd", Defs = [SREG] in {
1380 // 8-bit LSL is an alias of ADD Rd, Rd
1382 def LSLWRd : Pseudo<(outs DREGS
1392 def LSLWHiRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "lslwhi\t$rd",
1393 [(set i16:$rd, (AVRlslhi i16:$src)), (implicit SREG)]>;
1395 def LSLWNRd : Pseudo<(outs DLDREGS
1400 "lslwn\t$rd, $bits", [
1402 : $rd, (AVRlslwn i16
1408 def LSLBNRd : Pseudo<(outs LD8
1413 "lslbn\t$rd, $bits", [
1422 : FRd<0b1001, 0b0100110,
1427 "lsr\t$rd", [(set i8
1432 def LSRWRd : Pseudo<(outs DREGS
1442 def LSRWLoRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "lsrwlo\t$rd",
1443 [(set i16:$rd, (AVRlsrlo i16:$src)), (implicit SREG)]>;
1445 def LSRWNRd : Pseudo<(outs DLDREGS
1450 "lsrwn\t$rd, $bits", [
1452 : $rd, (AVRlsrwn i16
1458 def LSRBNRd : Pseudo<(outs LD8
1463 "lsrbn\t$rd, $bits", [
1472 : FRd<0b1001, 0b0100101,
1477 "asr\t$rd", [(set i8
1482 def ASRWNRd : Pseudo<(outs DREGS
1487 "asrwn\t$rd, $bits", [
1489 : $rd, (AVRasrwn i16
1495 def ASRBNRd : Pseudo<(outs LD8
1500 "asrbn\t$rd, $bits", [
1508 def ASRWRd : Pseudo<(outs DREGS
1518 def ASRWLoRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "asrwlo\t$rd",
1519 [(set i16:$rd, (AVRasrlo i16:$src)), (implicit SREG)]>;
1521 def ROLBRdR1 : Pseudo<(outs GPR8:$rd),
1524 [(set i8:$rd, (AVRrol i8:$src)),
1526 Requires<[HasNonTinyEncoding]>;
1529 def ROLBRdR17 : Pseudo<(outs GPR8:$rd),
1532 [(set i8:$rd, (AVRrol i8:$src)),
1534 Requires<[HasTinyEncoding]>;
1536 def RORBRd : Pseudo<(outs GPR8
1546 // Bit rotate operations.
1547 let Uses = [SREG] in {
1550 : Pseudo<(outs DREGS
1560 def RORRd : FRd<0b1001, 0b0100111,
1568 : Pseudo<(outs DREGS
1581 // Swaps the high and low nibbles in a register.
1583 "$src = $rd" in def SWAPRd : FRd<0b1001, 0b0100010,
1588 "swap\t$rd", [(set i8
1592 // IO register bit set/clear operations.
1593 //: TODO: add patterns when popcount(imm)==2 to be expanded with 2 sbi/cbi
1594 // instead of in+ori+out which requires one more instr.
1595 def SBIAb : FIOBIT<0b10, (outs),
1599 "sbi\t$addr, $b", [(store(or(i8(load lowioaddr8
1606 def CBIAb : FIOBIT<0b00, (outs),
1610 "cbi\t$addr, $b", [(store(and(i8(load lowioaddr8
1617 // Status register bit load/store operations.
1618 let Defs = [SREG] in def BST : FRdB<0b01, (outs),
1622 "bst\t$rd, $b", []>;
1624 let Constraints = "$src = $rd",
1625 Uses = [SREG] in def BLD : FRdB<0b00,
1631 "bld\t$rd, $b", []>;
1633 def CBR : InstAlias<"cbr\t$rd, $k", (ANDIRdK LD8 : $rd, imm_com8 : $k), 0>;
1636 // Alias for EOR Rd, Rd
1638 // Clears all bits in a register.
1639 def CLR : InstAlias<"clr\t$rd", (EORRdRr GPR8 : $rd, GPR8 : $rd)>;
1642 // Alias for ADD Rd, Rd
1644 // Logical shift left one bit.
1645 def LSL : InstAlias<"lsl\t$rd", (ADDRdRr GPR8 : $rd, GPR8 : $rd)>;
1647 def ROL : InstAlias<"rol\t$rd", (ADCRdRr GPR8 : $rd, GPR8 : $rd)>;
1650 // Alias for LDI Rd, 0xff
1652 // Sets all bits in a register.
1653 def : InstAlias<"ser\t$rd", (LDIRdK LD8 : $rd, 0xff), 0>;
1655 let hasSideEffects=1 in {
1656 let Defs = [SREG] in def BSETs : FS<0,
1661 let Defs = [SREG] in def BCLRs : FS<1,
1667 // Set/clear aliases for the carry (C) status flag (bit 0).
1668 def : InstAlias<"sec", (BSETs 0)>;
1669 def : InstAlias<"clc", (BCLRs 0)>;
1671 // Set/clear aliases for the zero (Z) status flag (bit 1).
1672 def : InstAlias<"sez", (BSETs 1)>;
1673 def : InstAlias<"clz", (BCLRs 1)>;
1675 // Set/clear aliases for the negative (N) status flag (bit 2).
1676 def : InstAlias<"sen", (BSETs 2)>;
1677 def : InstAlias<"cln", (BCLRs 2)>;
1679 // Set/clear aliases for the overflow (V) status flag (bit 3).
1680 def : InstAlias<"sev", (BSETs 3)>;
1681 def : InstAlias<"clv", (BCLRs 3)>;
1683 // Set/clear aliases for the signed (S) status flag (bit 4).
1684 def : InstAlias<"ses", (BSETs 4)>;
1685 def : InstAlias<"cls", (BCLRs 4)>;
1687 // Set/clear aliases for the half-carry (H) status flag (bit 5).
1688 def : InstAlias<"seh", (BSETs 5)>;
1689 def : InstAlias<"clh", (BCLRs 5)>;
1691 // Set/clear aliases for the T status flag (bit 6).
1692 def : InstAlias<"set", (BSETs 6)>;
1693 def : InstAlias<"clt", (BCLRs 6)>;
1695 // Set/clear aliases for the interrupt (I) status flag (bit 7).
1696 def : InstAlias<"sei", (BSETs 7)>;
1697 def : InstAlias<"cli", (BCLRs 7)>;
1699 //===----------------------------------------------------------------------===//
1700 // Special/Control instructions
1701 //===----------------------------------------------------------------------===//
1704 // Breakpoint instruction
1706 // <|1001|0101|1001|1000>
1707 def BREAK : F16<0b1001010110011000, (outs), (ins), "break", []>,
1708 Requires<[HasBREAK]>;
1711 // No-operation instruction
1713 // <|0000|0000|0000|0000>
1714 def NOP : F16<0b0000000000000000, (outs), (ins), "nop", []>;
1717 // Sleep instruction
1719 // <|1001|0101|1000|1000>
1720 def SLEEP : F16<0b1001010110001000, (outs), (ins), "sleep", []>;
1725 // <|1001|0101|1010|1000>
1726 def WDR : F16<0b1001010110101000, (outs), (ins), "wdr", []>;
1728 //===----------------------------------------------------------------------===//
1729 // Pseudo instructions for later expansion
1730 //===----------------------------------------------------------------------===//
1732 //: TODO: Optimize this for wider types AND optimize the following code
1733 // compile int foo(char a, char b, char c, char d) {return d+b;}
1734 // looks like a missed sext_inreg opportunity.
1736 : ExtensionPseudo<(outs DREGS
1747 : ExtensionPseudo<(outs DREGS
1757 // This pseudo gets expanded into a movw+adiw thus it clobbers SREG.
1759 hasSideEffects = 0 in def FRMIDX : Pseudo<(outs DLDREGS
1764 "frmidx\t$dst, $src, $src2", []>;
1766 // This pseudo is either converted to a regular store or a push which clobbers
1768 def STDSPQRr : StorePseudo<(outs),
1772 "stdstk\t$dst, $src", [(store i8
1776 // This pseudo is either converted to a regular store or a push which clobbers
1778 def STDWSPQRr : StorePseudo<(outs),
1782 "stdwstk\t$dst, $src", [(store i16
1786 // SP read/write pseudos.
1787 let hasSideEffects = 0 in {
1788 let Uses = [SP] in def SPREAD : Pseudo<(outs DREGS
1792 "spread\t$dst, $src", []>;
1794 let Defs = [SP] in def SPWRITE : Pseudo<(outs GPRSP
1798 "spwrite\t$dst, $src", []>;
1801 def Select8 : SelectPseudo<(outs GPR8
1807 "# Select8 PSEUDO", [(set i8
1808 : $dst, (AVRselectcc i8
1813 def Select16 : SelectPseudo<(outs DREGS
1819 "# Select16 PSEUDO", [(set i16
1820 : $dst, (AVRselectcc i16
1825 def Lsl8 : ShiftPseudo<(outs GPR8
1830 "# Lsl8 PSEUDO", [(set i8
1831 : $dst, (AVRlslLoop i8
1835 def Lsl16 : ShiftPseudo<(outs DREGS
1840 "# Lsl16 PSEUDO", [(set i16
1841 : $dst, (AVRlslLoop i16
1845 def Lsl32 : ShiftPseudo<(outs DREGS:$dstlo, DREGS:$dsthi),
1846 (ins DREGS:$srclo, DREGS:$srchi, i8imm:$cnt),
1848 [(set i16:$dstlo, i16:$dsthi, (AVRlslw i16:$srclo, i16:$srchi, i8:$cnt))]>;
1850 def Lsr8 : ShiftPseudo<(outs GPR8
1855 "# Lsr8 PSEUDO", [(set i8
1856 : $dst, (AVRlsrLoop i8
1860 def Lsr16 : ShiftPseudo<(outs DREGS
1865 "# Lsr16 PSEUDO", [(set i16
1866 : $dst, (AVRlsrLoop i16
1870 def Lsr32 : ShiftPseudo<(outs DREGS:$dstlo, DREGS:$dsthi),
1871 (ins DREGS:$srclo, DREGS:$srchi, i8imm:$cnt),
1873 [(set i16:$dstlo, i16:$dsthi, (AVRlsrw i16:$srclo, i16:$srchi, i8:$cnt))]>;
1875 def Rol8 : ShiftPseudo<(outs GPR8
1880 "# Rol8 PSEUDO", [(set i8
1881 : $dst, (AVRrolLoop i8
1885 def Rol16 : ShiftPseudo<(outs DREGS
1890 "# Rol16 PSEUDO", [(set i16
1891 : $dst, (AVRrolLoop i16
1895 def Ror8 : ShiftPseudo<(outs GPR8
1900 "# Ror8 PSEUDO", [(set i8
1901 : $dst, (AVRrorLoop i8
1905 def Ror16 : ShiftPseudo<(outs DREGS
1910 "# Ror16 PSEUDO", [(set i16
1911 : $dst, (AVRrorLoop i16
1915 def Asr8 : ShiftPseudo<(outs GPR8
1920 "# Asr8 PSEUDO", [(set i8
1921 : $dst, (AVRasrLoop i8
1925 def Asr16 : ShiftPseudo<(outs DREGS
1930 "# Asr16 PSEUDO", [(set i16
1931 : $dst, (AVRasrLoop i16
1935 def Asr32 : ShiftPseudo<(outs DREGS:$dstlo, DREGS:$dsthi),
1936 (ins DREGS:$srclo, DREGS:$srchi, i8imm:$cnt),
1938 [(set i16:$dstlo, i16:$dsthi, (AVRasrw i16:$srclo, i16:$srchi, i8:$cnt))]>;
1940 // lowered to a copy from the zero register.
1941 let usesCustomInserter=1 in
1942 def CopyZero : Pseudo<(outs GPR8:$rd), (ins), "clrz\t$rd", [(set i8:$rd, 0)]>;
1944 //===----------------------------------------------------------------------===//
1945 // Non-Instruction Patterns
1946 //===----------------------------------------------------------------------===//
1948 //: TODO: look in x86InstrCompiler.td for odd encoding trick related to
1949 // add x, 128 -> sub x, -128. Clang is emitting an eor for this (ldi+eor)
1951 // the add instruction always writes the carry flag
1952 def : Pat<(addc i8 : $src, i8 : $src2), (ADDRdRr i8 : $src, i8 : $src2)>;
1953 def : Pat<(addc DREGS
1960 // all sub instruction variants always writes the carry flag
1961 def : Pat<(subc i8 : $src, i8 : $src2), (SUBRdRr i8 : $src, i8 : $src2)>;
1962 def : Pat<(subc i16 : $src, i16 : $src2), (SUBWRdRr i16 : $src, i16 : $src2)>;
1963 def : Pat<(subc i8 : $src, imm : $src2), (SUBIRdK i8 : $src, imm : $src2)>;
1964 def : Pat<(subc i16 : $src, imm : $src2), (SUBIWRdK i16 : $src, imm : $src2)>;
1966 // These patterns convert add (x, -imm) to sub (x, imm) since we dont have
1967 // any add with imm instructions. Also take care of the adiw/sbiw instructions.
1969 : $src1, imm0_63_neg
1972 : $src1, (imm0_63_neg
1974 Requires<[HasADDSUBIW]>;
1979 : $src1, (imm16_neg_XFORM imm
1985 : $src1, (imm16_neg_XFORM imm
1992 : $src1, (imm8_neg_XFORM imm
1998 : $src1, (imm8_neg_XFORM imm
2004 : $src1, (imm8_neg_XFORM imm
2007 // Emit NEGWRd with an extra zero register operand.
2008 def : Pat<(ineg i16:$src),
2009 (NEGWRd i16:$src, (CopyZero))>;
2012 let Predicates = [HasJMPCALL] in {
2013 def : Pat<(AVRcall(i16 tglobaladdr:$dst)), (CALLk tglobaladdr:$dst)>;
2014 def : Pat<(AVRcall(i16 texternalsym:$dst)), (CALLk texternalsym:$dst)>;
2016 def : Pat<(AVRcall(i16 tglobaladdr:$dst)), (RCALLk tglobaladdr:$dst)>;
2017 def : Pat<(AVRcall(i16 texternalsym:$dst)), (RCALLk texternalsym:$dst)>;
2020 def : Pat<(i16(anyext i8
2022 (INSERT_SUBREG(i16(IMPLICIT_DEF)), i8
2026 def : Pat<(i8(trunc i16 : $src)), (EXTRACT_SUBREG i16 : $src, sub_lo)>;
2029 def : Pat<(sext_inreg i16
2031 (SEXT(i8(EXTRACT_SUBREG i16
2035 def : Pat<(i16(AVRWrapper tglobaladdr : $dst)), (LDIWRdK tglobaladdr : $dst)>;
2037 : $src, (AVRWrapper tglobaladdr
2042 def : Pat<(i8(load(AVRWrapper tglobaladdr:$dst))),
2043 (LDSRdK tglobaladdr:$dst)>,
2044 Requires<[HasSRAM, HasNonTinyEncoding]>;
2045 def : Pat<(i8(load(AVRWrapper tglobaladdr:$dst))),
2046 (LDSRdKTiny tglobaladdr:$dst)>,
2047 Requires<[HasSRAM, HasTinyEncoding]>;
2048 def : Pat<(i16(load(AVRWrapper tglobaladdr:$dst))),
2049 (LDSWRdK tglobaladdr:$dst)>,
2050 Requires<[HasSRAM, HasNonTinyEncoding]>;
2051 def : Pat<(store i8:$src, (i16(AVRWrapper tglobaladdr:$dst))),
2052 (STSKRr tglobaladdr:$dst, i8:$src)>,
2053 Requires<[HasSRAM, HasNonTinyEncoding]>;
2054 def : Pat<(store i8:$src, (i16(AVRWrapper tglobaladdr:$dst))),
2055 (STSKRrTiny tglobaladdr:$dst, i8:$src)>,
2056 Requires<[HasSRAM, HasTinyEncoding]>;
2057 def : Pat<(store i16:$src, (i16(AVRWrapper tglobaladdr:$dst))),
2058 (STSWKRr tglobaladdr:$dst, i16:$src)>,
2059 Requires<[HasSRAM, HasNonTinyEncoding]>;
2062 def : Pat<(i16(AVRWrapper tblockaddress
2064 (LDIWRdK tblockaddress
2067 def : Pat<(i8(trunc(AVRlsrwn DLDREGS
2069 (EXTRACT_SUBREG DREGS
2072 // :FIXME: DAGCombiner produces an shl node after legalization from these seq:
2073 // BR_JT -> (mul x, 2) -> (shl x, 1)
2074 def : Pat<(shl i16 : $src1, (i8 1)), (LSLWRd i16 : $src1)>;
2076 // Lowering of 'tst' node to 'TST' instruction.
2077 // TST is an alias of AND Rd, Rd.
2078 def : Pat<(AVRtst i8 : $rd), (ANDRdRr GPR8 : $rd, GPR8 : $rd)>;
2080 // Lowering of 'lsl' node to 'LSL' instruction.
2081 // LSL is an alias of 'ADD Rd, Rd'
2082 def : Pat<(AVRlsl i8 : $rd), (ADDRdRr GPR8 : $rd, GPR8 : $rd)>;