llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h

   1 //==- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass -*- C++ -*-==//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 /// \file
   8 /// This file implements a TargetTransformInfo analysis pass specific to the
   9 /// Hexagon target machine. It uses the target's detailed information to provide
  10 /// more precise answers to certain TTI queries, while letting the target
  11 /// independent and default TTI implementations handle the rest.
  12 ///
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H
  16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H
  17
  18 #include "Hexagon.h"
  19 #include "HexagonSubtarget.h"
  20 #include "HexagonTargetMachine.h"
  21 #include "llvm/ADT/ArrayRef.h"
  22 #include "llvm/Analysis/TargetTransformInfo.h"
  23 #include "llvm/CodeGen/BasicTTIImpl.h"
  24 #include "llvm/IR/Function.h"
  25
  26 namespace llvm {
  27
  28 class Loop;
  29 class ScalarEvolution;
  30 class User;
  31 class Value;
  32
  33 class HexagonTTIImpl : public BasicTTIImplBase<HexagonTTIImpl> {
  34   using BaseT = BasicTTIImplBase<HexagonTTIImpl>;
  35   using TTI = TargetTransformInfo;
  36
  37   friend BaseT;
  38
  39   const HexagonSubtarget &ST;
  40   const HexagonTargetLowering &TLI;
  41
  42   const HexagonSubtarget *getST() const { return &ST; }
  43   const HexagonTargetLowering *getTLI() const { return &TLI; }
  44
  45   bool useHVX() const;
  46   bool isHVXVectorType(Type *Ty) const;
  47
  48   // Returns the number of vector elements of Ty, if Ty is a vector type,
  49   // or 1 if Ty is a scalar type. It is incorrect to call this function
  50   // with any other type.
  51   unsigned getTypeNumElements(Type *Ty) const;
  52
  53 public:
  54   explicit HexagonTTIImpl(const HexagonTargetMachine *TM, const Function &F)
  55       : BaseT(TM, F.getDataLayout()),
  56         ST(*TM->getSubtargetImpl(F)), TLI(*ST.getTargetLowering()) {}
  57
  58   /// \name Scalar TTI Implementations
  59   /// @{
  60
  61   TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const;
  62
  63   // The Hexagon target can unroll loops with run-time trip counts.
  64   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
  65                                TTI::UnrollingPreferences &UP,
  66                                OptimizationRemarkEmitter *ORE);
  67
  68   void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
  69                              TTI::PeelingPreferences &PP);
  70
  71   /// Bias LSR towards creating post-increment opportunities.
  72   TTI::AddressingModeKind
  73     getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const;
  74
  75   // L1 cache prefetch.
  76   unsigned getPrefetchDistance() const override;
  77   unsigned getCacheLineSize() const override;
  78
  79   /// @}
  80
  81   /// \name Vector TTI Implementations
  82   /// @{
  83
  84   unsigned getNumberOfRegisters(bool vector) const;
  85   unsigned getMaxInterleaveFactor(ElementCount VF);
  86   TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const;
  87   unsigned getMinVectorRegisterBitWidth() const;
  88   ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const;
  89
  90   bool
  91   shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const {
  92     return true;
  93   }
  94   bool supportsEfficientVectorElementLoadStore() { return false; }
  95   bool hasBranchDivergence(const Function *F = nullptr) { return false; }
  96   bool enableAggressiveInterleaving(bool LoopHasReductions) {
  97     return false;
  98   }
  99   bool prefersVectorizedAddressing() {
 100     return false;
 101   }
 102   bool enableInterleavedAccessVectorization() {
 103     return true;
 104   }
 105
 106   InstructionCost getCallInstrCost(Function *F, Type *RetTy,
 107                                    ArrayRef<Type *> Tys,
 108                                    TTI::TargetCostKind CostKind);
 109   InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
 110                                         TTI::TargetCostKind CostKind);
 111   InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *SE,
 112                                             const SCEV *S);
 113   InstructionCost
 114   getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
 115                   unsigned AddressSpace, TTI::TargetCostKind CostKind,
 116                   TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None},
 117                   const Instruction *I = nullptr);
 118   InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
 119                                         Align Alignment, unsigned AddressSpace,
 120                                         TTI::TargetCostKind CostKind);
 121   InstructionCost getShuffleCost(TTI::ShuffleKind Kind, Type *Tp,
 122                                  ArrayRef<int> Mask,
 123                                  TTI::TargetCostKind CostKind, int Index,
 124                                  Type *SubTp,
 125                                  ArrayRef<const Value *> Args = std::nullopt,
 126                                  const Instruction *CxtI = nullptr);
 127   InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
 128                                          const Value *Ptr, bool VariableMask,
 129                                          Align Alignment,
 130                                          TTI::TargetCostKind CostKind,
 131                                          const Instruction *I);
 132   InstructionCost getInterleavedMemoryOpCost(
 133       unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
 134       Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
 135       bool UseMaskForCond = false, bool UseMaskForGaps = false);
 136   InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
 137                                      CmpInst::Predicate VecPred,
 138                                      TTI::TargetCostKind CostKind,
 139                                      const Instruction *I = nullptr);
 140   InstructionCost getArithmeticInstrCost(
 141       unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
 142       TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
 143       TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
 144       ArrayRef<const Value *> Args = std::nullopt,
 145       const Instruction *CxtI = nullptr);
 146   InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
 147                                    TTI::CastContextHint CCH,
 148                                    TTI::TargetCostKind CostKind,
 149                                    const Instruction *I = nullptr);
 150   using BaseT::getVectorInstrCost;
 151   InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
 152                                      TTI::TargetCostKind CostKind,
 153                                      unsigned Index, Value *Op0, Value *Op1);
 154
 155   InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
 156                                  const Instruction *I = nullptr) {
 157     return 1;
 158   }
 159
 160   bool isLegalMaskedStore(Type *DataType, Align Alignment);
 161   bool isLegalMaskedLoad(Type *DataType, Align Alignment);
 162
 163   /// @}
 164
 165   InstructionCost getInstructionCost(const User *U,
 166                                      ArrayRef<const Value *> Operands,
 167                                      TTI::TargetCostKind CostKind);
 168
 169   // Hexagon specific decision to generate a lookup table.
 170   bool shouldBuildLookupTables() const;
 171 };
 172
 173 } // end namespace llvm
 174 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H