llvm/lib/Target/Lanai/LanaiTargetMachine.cpp

   1 //===-- LanaiTargetMachine.cpp - Define TargetMachine for Lanai ---------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // Implements the info about Lanai target spec.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "LanaiTargetMachine.h"
  14
  15 #include "Lanai.h"
  16 #include "LanaiMachineFunctionInfo.h"
  17 #include "LanaiTargetObjectFile.h"
  18 #include "LanaiTargetTransformInfo.h"
  19 #include "TargetInfo/LanaiTargetInfo.h"
  20 #include "llvm/Analysis/TargetTransformInfo.h"
  21 #include "llvm/CodeGen/Passes.h"
  22 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
  23 #include "llvm/CodeGen/TargetPassConfig.h"
  24 #include "llvm/MC/TargetRegistry.h"
  25 #include "llvm/Support/FormattedStream.h"
  26 #include "llvm/Target/TargetOptions.h"
  27 #include <optional>
  28
  29 using namespace llvm;
  30
  31 namespace llvm {
  32 void initializeLanaiMemAluCombinerPass(PassRegistry &);
  33 } // namespace llvm
  34
  35 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLanaiTarget() {
  36   // Register the target.
  37   RegisterTargetMachine<LanaiTargetMachine> registered_target(
  38       getTheLanaiTarget());
  39   PassRegistry &PR = *PassRegistry::getPassRegistry();
  40   initializeLanaiDAGToDAGISelLegacyPass(PR);
  41 }
  42
  43 static std::string computeDataLayout() {
  44   // Data layout (keep in sync with clang/lib/Basic/Targets.cpp)
  45   return "E"        // Big endian
  46          "-m:e"     // ELF name manging
  47          "-p:32:32" // 32-bit pointers, 32 bit aligned
  48          "-i64:64"  // 64 bit integers, 64 bit aligned
  49          "-a:0:32"  // 32 bit alignment of objects of aggregate type
  50          "-n32"     // 32 bit native integer width
  51          "-S64";    // 64 bit natural stack alignment
  52 }
  53
  54 static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
  55   return RM.value_or(Reloc::PIC_);
  56 }
  57
  58 LanaiTargetMachine::LanaiTargetMachine(
  59     const Target &T, const Triple &TT, StringRef Cpu, StringRef FeatureString,
  60     const TargetOptions &Options, std::optional<Reloc::Model> RM,
  61     std::optional<CodeModel::Model> CodeModel, CodeGenOptLevel OptLevel,
  62     bool JIT)
  63     : LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options,
  64                         getEffectiveRelocModel(RM),
  65                         getEffectiveCodeModel(CodeModel, CodeModel::Medium),
  66                         OptLevel),
  67       Subtarget(TT, Cpu, FeatureString, *this, Options, getCodeModel(),
  68                 OptLevel),
  69       TLOF(new LanaiTargetObjectFile()) {
  70   initAsmInfo();
  71 }
  72
  73 TargetTransformInfo
  74 LanaiTargetMachine::getTargetTransformInfo(const Function &F) const {
  75   return TargetTransformInfo(LanaiTTIImpl(this, F));
  76 }
  77
  78 MachineFunctionInfo *LanaiTargetMachine::createMachineFunctionInfo(
  79     BumpPtrAllocator &Allocator, const Function &F,
  80     const TargetSubtargetInfo *STI) const {
  81   return LanaiMachineFunctionInfo::create<LanaiMachineFunctionInfo>(Allocator,
  82                                                                     F, STI);
  83 }
  84
  85 namespace {
  86 // Lanai Code Generator Pass Configuration Options.
  87 class LanaiPassConfig : public TargetPassConfig {
  88 public:
  89   LanaiPassConfig(LanaiTargetMachine &TM, PassManagerBase *PassManager)
  90       : TargetPassConfig(TM, *PassManager) {}
  91
  92   LanaiTargetMachine &getLanaiTargetMachine() const {
  93     return getTM<LanaiTargetMachine>();
  94   }
  95
  96   void addIRPasses() override;
  97   bool addInstSelector() override;
  98   void addPreSched2() override;
  99   void addPreEmitPass() override;
 100 };
 101 } // namespace
 102
 103 TargetPassConfig *
 104 LanaiTargetMachine::createPassConfig(PassManagerBase &PassManager) {
 105   return new LanaiPassConfig(*this, &PassManager);
 106 }
 107
 108 void LanaiPassConfig::addIRPasses() {
 109   addPass(createAtomicExpandLegacyPass());
 110
 111   TargetPassConfig::addIRPasses();
 112 }
 113
 114 // Install an instruction selector pass.
 115 bool LanaiPassConfig::addInstSelector() {
 116   addPass(createLanaiISelDag(getLanaiTargetMachine()));
 117   return false;
 118 }
 119
 120 // Implemented by targets that want to run passes immediately before
 121 // machine code is emitted.
 122 void LanaiPassConfig::addPreEmitPass() {
 123   addPass(createLanaiDelaySlotFillerPass(getLanaiTargetMachine()));
 124 }
 125
 126 // Run passes after prolog-epilog insertion and before the second instruction
 127 // scheduling pass.
 128 void LanaiPassConfig::addPreSched2() {
 129   addPass(createLanaiMemAluCombinerPass());
 130 }