llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp

   1 //===- NVPTXRegisterInfo.cpp - NVPTX Register Information -----------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the NVPTX implementation of the TargetRegisterInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "NVPTXRegisterInfo.h"
  14 #include "NVPTX.h"
  15 #include "NVPTXSubtarget.h"
  16 #include "NVPTXTargetMachine.h"
  17 #include "llvm/ADT/BitVector.h"
  18 #include "llvm/CodeGen/MachineFrameInfo.h"
  19 #include "llvm/CodeGen/MachineFunction.h"
  20 #include "llvm/CodeGen/MachineInstrBuilder.h"
  21 #include "llvm/CodeGen/TargetInstrInfo.h"
  22 #include "llvm/MC/MachineLocation.h"
  23
  24 using namespace llvm;
  25
  26 #define DEBUG_TYPE "nvptx-reg-info"
  27
  28 namespace llvm {
  29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) {
  30   if (RC == &NVPTX::Float32RegsRegClass)
  31     return ".f32";
  32   if (RC == &NVPTX::Float64RegsRegClass)
  33     return ".f64";
  34   if (RC == &NVPTX::Int128RegsRegClass)
  35     return ".b128";
  36   if (RC == &NVPTX::Int64RegsRegClass)
  37     // We use untyped (.b) integer registers here as NVCC does.
  38     // Correctness of generated code does not depend on register type,
  39     // but using .s/.u registers runs into ptxas bug that prevents
  40     // assembly of otherwise valid PTX into SASS. Despite PTX ISA
  41     // specifying only argument size for fp16 instructions, ptxas does
  42     // not allow using .s16 or .u16 arguments for .fp16
  43     // instructions. At the same time it allows using .s32/.u32
  44     // arguments for .fp16v2 instructions:
  45     //
  46     //   .reg .b16 rb16
  47     //   .reg .s16 rs16
  48     //   add.f16 rb16,rb16,rb16; // OK
  49     //   add.f16 rs16,rs16,rs16; // Arguments mismatch for instruction 'add'
  50     // but:
  51     //   .reg .b32 rb32
  52     //   .reg .s32 rs32
  53     //   add.f16v2 rb32,rb32,rb32; // OK
  54     //   add.f16v2 rs32,rs32,rs32; // OK
  55     return ".b64";
  56   if (RC == &NVPTX::Int32RegsRegClass)
  57     return ".b32";
  58   if (RC == &NVPTX::Int16RegsRegClass)
  59     return ".b16";
  60   if (RC == &NVPTX::Int1RegsRegClass)
  61     return ".pred";
  62   if (RC == &NVPTX::SpecialRegsRegClass)
  63     return "!Special!";
  64   return "INTERNAL";
  65 }
  66
  67 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) {
  68   if (RC == &NVPTX::Float32RegsRegClass)
  69     return "%f";
  70   if (RC == &NVPTX::Float64RegsRegClass)
  71     return "%fd";
  72   if (RC == &NVPTX::Int128RegsRegClass)
  73     return "%rq";
  74   if (RC == &NVPTX::Int64RegsRegClass)
  75     return "%rd";
  76   if (RC == &NVPTX::Int32RegsRegClass)
  77     return "%r";
  78   if (RC == &NVPTX::Int16RegsRegClass)
  79     return "%rs";
  80   if (RC == &NVPTX::Int1RegsRegClass)
  81     return "%p";
  82   if (RC == &NVPTX::SpecialRegsRegClass)
  83     return "!Special!";
  84   return "INTERNAL";
  85 }
  86 }
  87
  88 NVPTXRegisterInfo::NVPTXRegisterInfo()
  89     : NVPTXGenRegisterInfo(0), StrPool(StrAlloc) {}
  90
  91 #define GET_REGINFO_TARGET_DESC
  92 #include "NVPTXGenRegisterInfo.inc"
  93
  94 /// NVPTX Callee Saved Registers
  95 const MCPhysReg *
  96 NVPTXRegisterInfo::getCalleeSavedRegs(const MachineFunction *) const {
  97   static const MCPhysReg CalleeSavedRegs[] = { 0 };
  98   return CalleeSavedRegs;
  99 }
 100
 101 BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
 102   BitVector Reserved(getNumRegs());
 103   for (unsigned Reg = NVPTX::ENVREG0; Reg <= NVPTX::ENVREG31; ++Reg) {
 104     markSuperRegs(Reserved, Reg);
 105   }
 106   markSuperRegs(Reserved, NVPTX::VRFrame32);
 107   markSuperRegs(Reserved, NVPTX::VRFrameLocal32);
 108   markSuperRegs(Reserved, NVPTX::VRFrame64);
 109   markSuperRegs(Reserved, NVPTX::VRFrameLocal64);
 110   markSuperRegs(Reserved, NVPTX::VRDepot);
 111   return Reserved;
 112 }
 113
 114 bool NVPTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 115                                             int SPAdj, unsigned FIOperandNum,
 116                                             RegScavenger *RS) const {
 117   assert(SPAdj == 0 && "Unexpected");
 118
 119   MachineInstr &MI = *II;
 120   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
 121
 122   MachineFunction &MF = *MI.getParent()->getParent();
 123   int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex) +
 124                MI.getOperand(FIOperandNum + 1).getImm();
 125
 126   // Using I0 as the frame pointer
 127   MI.getOperand(FIOperandNum).ChangeToRegister(getFrameRegister(MF), false);
 128   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
 129   return false;
 130 }
 131
 132 Register NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
 133   const NVPTXTargetMachine &TM =
 134       static_cast<const NVPTXTargetMachine &>(MF.getTarget());
 135   return TM.is64Bit() ? NVPTX::VRFrame64 : NVPTX::VRFrame32;
 136 }
 137
 138 Register
 139 NVPTXRegisterInfo::getFrameLocalRegister(const MachineFunction &MF) const {
 140   const NVPTXTargetMachine &TM =
 141       static_cast<const NVPTXTargetMachine &>(MF.getTarget());
 142   return TM.is64Bit() ? NVPTX::VRFrameLocal64 : NVPTX::VRFrameLocal32;
 143 }