| blob | 34ac4f6361d963da6e075b637b40861809ef38aa |
1 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 ; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
4 define i32 @gep_nusw_nuw(ptr %ptr, i32 %idx) {
5 ; CHECK-LABEL: name: gep_nusw_nuw
6 ; CHECK: bb.1 (%ir-block.0):
7 ; CHECK-NEXT: liveins: $w1, $x0
8 ; CHECK-NEXT: {{ $}}
9 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
11 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
12 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
13 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
14 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64)
15 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
16 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
17 ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
18 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL1]](s64)
19 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
20 ; CHECK-NEXT: %11:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
21 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD %11(p0) :: (load (s32) from %ir.gep2)
22 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
23 ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
24 ; CHECK-NEXT: RET_ReallyLR implicit $w0
25 %sidx = sext i32 %idx to i64
26 %gep1 = getelementptr inbounds [4 x i32], ptr %ptr, i64 %sidx, i64 0
27 %v1 = load i32, ptr %gep1
28 %gep2 = getelementptr nusw nuw [4 x i32], ptr %ptr, i64 %sidx, i64 1
29 %v2 = load i32, ptr %gep2
30 %res = add i32 %v1, %v2
31 ret i32 %res
32 }
34 define i32 @gep_nuw(ptr %ptr, i32 %idx) {
35 ; CHECK-LABEL: name: gep_nuw
36 ; CHECK: bb.1 (%ir-block.0):
37 ; CHECK-NEXT: liveins: $w1, $x0
38 ; CHECK-NEXT: {{ $}}
39 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
40 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
41 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
42 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
43 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
44 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64)
45 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
46 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
47 ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
48 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL1]](s64)
49 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
50 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
51 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.gep2)
52 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
53 ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
54 ; CHECK-NEXT: RET_ReallyLR implicit $w0
55 %sidx = sext i32 %idx to i64
56 %gep1 = getelementptr inbounds [4 x i32], ptr %ptr, i64 %sidx, i64 0
57 %v1 = load i32, ptr %gep1
58 %gep2 = getelementptr nuw [4 x i32], ptr %ptr, i64 %sidx, i64 1
59 %v2 = load i32, ptr %gep2
60 %res = add i32 %v1, %v2
61 ret i32 %res
62 }
64 define i32 @gep_nusw(ptr %ptr, i32 %idx) {
65 ; CHECK-LABEL: name: gep_nusw
66 ; CHECK: bb.1 (%ir-block.0):
67 ; CHECK-NEXT: liveins: $w1, $x0
68 ; CHECK-NEXT: {{ $}}
69 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
70 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
71 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
72 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
73 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
74 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64)
75 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
76 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
77 ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
78 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL1]](s64)
79 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
80 ; CHECK-NEXT: %11:_(p0) = nusw G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
81 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD %11(p0) :: (load (s32) from %ir.gep2)
82 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
83 ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
84 ; CHECK-NEXT: RET_ReallyLR implicit $w0
85 %sidx = sext i32 %idx to i64
86 %gep1 = getelementptr inbounds [4 x i32], ptr %ptr, i64 %sidx, i64 0
87 %v1 = load i32, ptr %gep1
88 %gep2 = getelementptr nusw [4 x i32], ptr %ptr, i64 %sidx, i64 1
89 %v2 = load i32, ptr %gep2
90 %res = add i32 %v1, %v2
91 ret i32 %res
92 }
94 define i32 @gep_none(ptr %ptr, i32 %idx) {
95 ; CHECK-LABEL: name: gep_none
96 ; CHECK: bb.1 (%ir-block.0):
97 ; CHECK-NEXT: liveins: $w1, $x0
98 ; CHECK-NEXT: {{ $}}
99 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
100 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
101 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
102 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
103 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
104 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64)
105 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
106 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
107 ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
108 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL1]](s64)
109 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
110 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
111 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.gep2)
112 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
113 ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
114 ; CHECK-NEXT: RET_ReallyLR implicit $w0
115 %sidx = sext i32 %idx to i64
116 %gep1 = getelementptr inbounds [4 x i32], ptr %ptr, i64 %sidx, i64 0
117 %v1 = load i32, ptr %gep1
118 %gep2 = getelementptr [4 x i32], ptr %ptr, i64 %sidx, i64 1
119 %v2 = load i32, ptr %gep2
120 %res = add i32 %v1, %v2
121 ret i32 %res
122 }