1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -simplify-mir -aarch64-neon-syntax=apple -mattr=-fullfp16 -o - | FileCheck %s --check-prefix=NO-FP16
3 # RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -simplify-mir -aarch64-neon-syntax=apple -mattr=+fullfp16 -o - | FileCheck %s --check-prefix=FP16
8 tracksRegLiveness: true
9 machineFunctionInfo: {}
12 liveins: $d0, $d1, $d2
14 ; NO-FP16-LABEL: name: test_v4f16.fma
15 ; NO-FP16: liveins: $d0, $d1, $d2
16 ; NO-FP16-NEXT: {{ $}}
17 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
18 ; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
19 ; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
20 ; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY]](<4 x s16>)
21 ; NO-FP16-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY1]](<4 x s16>)
22 ; NO-FP16-NEXT: [[FPEXT2:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY2]](<4 x s16>)
23 ; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[FPEXT]], [[FPEXT1]], [[FPEXT2]]
24 ; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[FMA]](<4 x s32>)
25 ; NO-FP16-NEXT: $d0 = COPY [[FPTRUNC]](<4 x s16>)
26 ; NO-FP16-NEXT: RET_ReallyLR implicit $d0
28 ; FP16-LABEL: name: test_v4f16.fma
29 ; FP16: liveins: $d0, $d1, $d2
31 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
32 ; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
33 ; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
34 ; FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s16>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
35 ; FP16-NEXT: $d0 = COPY [[FMA]](<4 x s16>)
36 ; FP16-NEXT: RET_ReallyLR implicit $d0
37 %0:_(<4 x s16>) = COPY $d0
38 %1:_(<4 x s16>) = COPY $d1
39 %2:_(<4 x s16>) = COPY $d2
40 %3:_(<4 x s16>) = G_FMA %0, %1, %2
41 $d0 = COPY %3(<4 x s16>)
42 RET_ReallyLR implicit $d0
48 tracksRegLiveness: true
49 machineFunctionInfo: {}
52 liveins: $q0, $q1, $q2
54 ; NO-FP16-LABEL: name: test_v8f16.fma
55 ; NO-FP16: liveins: $q0, $q1, $q2
56 ; NO-FP16-NEXT: {{ $}}
57 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
58 ; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
59 ; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s16>) = COPY $q2
60 ; NO-FP16-NEXT: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
61 ; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV]](<4 x s16>)
62 ; NO-FP16-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV1]](<4 x s16>)
63 ; NO-FP16-NEXT: [[UV2:%[0-9]+]]:_(<4 x s16>), [[UV3:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY1]](<8 x s16>)
64 ; NO-FP16-NEXT: [[FPEXT2:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV2]](<4 x s16>)
65 ; NO-FP16-NEXT: [[FPEXT3:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV3]](<4 x s16>)
66 ; NO-FP16-NEXT: [[UV4:%[0-9]+]]:_(<4 x s16>), [[UV5:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY2]](<8 x s16>)
67 ; NO-FP16-NEXT: [[FPEXT4:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV4]](<4 x s16>)
68 ; NO-FP16-NEXT: [[FPEXT5:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV5]](<4 x s16>)
69 ; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[FPEXT]], [[FPEXT2]], [[FPEXT4]]
70 ; NO-FP16-NEXT: [[FMA1:%[0-9]+]]:_(<4 x s32>) = G_FMA [[FPEXT1]], [[FPEXT3]], [[FPEXT5]]
71 ; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[FMA]](<4 x s32>)
72 ; NO-FP16-NEXT: [[FPTRUNC1:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[FMA1]](<4 x s32>)
73 ; NO-FP16-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[FPTRUNC]](<4 x s16>), [[FPTRUNC1]](<4 x s16>)
74 ; NO-FP16-NEXT: $q0 = COPY [[CONCAT_VECTORS]](<8 x s16>)
75 ; NO-FP16-NEXT: RET_ReallyLR implicit $q0
77 ; FP16-LABEL: name: test_v8f16.fma
78 ; FP16: liveins: $q0, $q1, $q2
80 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
81 ; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
82 ; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s16>) = COPY $q2
83 ; FP16-NEXT: [[FMA:%[0-9]+]]:_(<8 x s16>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
84 ; FP16-NEXT: $q0 = COPY [[FMA]](<8 x s16>)
85 ; FP16-NEXT: RET_ReallyLR implicit $q0
86 %0:_(<8 x s16>) = COPY $q0
87 %1:_(<8 x s16>) = COPY $q1
88 %2:_(<8 x s16>) = COPY $q2
89 %3:_(<8 x s16>) = G_FMA %0, %1, %2
90 $q0 = COPY %3(<8 x s16>)
91 RET_ReallyLR implicit $q0
97 tracksRegLiveness: true
98 machineFunctionInfo: {}
101 liveins: $d0, $d1, $d2
103 ; NO-FP16-LABEL: name: test_v2f32.fma
104 ; NO-FP16: liveins: $d0, $d1, $d2
105 ; NO-FP16-NEXT: {{ $}}
106 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
107 ; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
108 ; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
109 ; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
110 ; NO-FP16-NEXT: $d0 = COPY [[FMA]](<2 x s32>)
111 ; NO-FP16-NEXT: RET_ReallyLR implicit $d0
113 ; FP16-LABEL: name: test_v2f32.fma
114 ; FP16: liveins: $d0, $d1, $d2
116 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
117 ; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
118 ; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
119 ; FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
120 ; FP16-NEXT: $d0 = COPY [[FMA]](<2 x s32>)
121 ; FP16-NEXT: RET_ReallyLR implicit $d0
122 %0:_(<2 x s32>) = COPY $d0
123 %1:_(<2 x s32>) = COPY $d1
124 %2:_(<2 x s32>) = COPY $d2
125 %3:_(<2 x s32>) = G_FMA %0, %1, %2
126 $d0 = COPY %3(<2 x s32>)
127 RET_ReallyLR implicit $d0
133 tracksRegLiveness: true
134 machineFunctionInfo: {}
137 liveins: $q0, $q1, $q2
139 ; NO-FP16-LABEL: name: test_v4f32.fma
140 ; NO-FP16: liveins: $q0, $q1, $q2
141 ; NO-FP16-NEXT: {{ $}}
142 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
143 ; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
144 ; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
145 ; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
146 ; NO-FP16-NEXT: $q0 = COPY [[FMA]](<4 x s32>)
147 ; NO-FP16-NEXT: RET_ReallyLR implicit $q0
149 ; FP16-LABEL: name: test_v4f32.fma
150 ; FP16: liveins: $q0, $q1, $q2
152 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
153 ; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
154 ; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
155 ; FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
156 ; FP16-NEXT: $q0 = COPY [[FMA]](<4 x s32>)
157 ; FP16-NEXT: RET_ReallyLR implicit $q0
158 %0:_(<4 x s32>) = COPY $q0
159 %1:_(<4 x s32>) = COPY $q1
160 %2:_(<4 x s32>) = COPY $q2
161 %3:_(<4 x s32>) = G_FMA %0, %1, %2
162 $q0 = COPY %3(<4 x s32>)
163 RET_ReallyLR implicit $q0
169 tracksRegLiveness: true
170 machineFunctionInfo: {}
173 liveins: $q0, $q1, $q2
175 ; NO-FP16-LABEL: name: test_v2f64.fma
176 ; NO-FP16: liveins: $q0, $q1, $q2
177 ; NO-FP16-NEXT: {{ $}}
178 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
179 ; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
180 ; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
181 ; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x s64>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
182 ; NO-FP16-NEXT: $q0 = COPY [[FMA]](<2 x s64>)
183 ; NO-FP16-NEXT: RET_ReallyLR implicit $q0
185 ; FP16-LABEL: name: test_v2f64.fma
186 ; FP16: liveins: $q0, $q1, $q2
188 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
189 ; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
190 ; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
191 ; FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x s64>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
192 ; FP16-NEXT: $q0 = COPY [[FMA]](<2 x s64>)
193 ; FP16-NEXT: RET_ReallyLR implicit $q0
194 %0:_(<2 x s64>) = COPY $q0
195 %1:_(<2 x s64>) = COPY $q1
196 %2:_(<2 x s64>) = COPY $q2
197 %3:_(<2 x s64>) = G_FMA %0, %1, %2
198 $q0 = COPY %3(<2 x s64>)
199 RET_ReallyLR implicit $q0