1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
8 define <vscale x 4 x i32> @adrb_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
9 ; CHECK-LABEL: adrb_i32:
11 ; CHECK-NEXT: adr z0.s, [z0.s, z1.s]
13 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32> %a,
14 <vscale x 4 x i32> %b)
15 ret <vscale x 4 x i32> %out
18 define <vscale x 2 x i64> @adrb_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
19 ; CHECK-LABEL: adrb_i64:
21 ; CHECK-NEXT: adr z0.d, [z0.d, z1.d]
23 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64> %a,
24 <vscale x 2 x i64> %b)
25 ret <vscale x 2 x i64> %out
32 define <vscale x 4 x i32> @adrh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
33 ; CHECK-LABEL: adrh_i32:
35 ; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #1]
37 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32> %a,
38 <vscale x 4 x i32> %b)
39 ret <vscale x 4 x i32> %out
42 define <vscale x 2 x i64> @adrh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
43 ; CHECK-LABEL: adrh_i64:
45 ; CHECK-NEXT: adr z0.d, [z0.d, z1.d, lsl #1]
47 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64> %a,
48 <vscale x 2 x i64> %b)
49 ret <vscale x 2 x i64> %out
56 define <vscale x 4 x i32> @adrw_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
57 ; CHECK-LABEL: adrw_i32:
59 ; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #2]
61 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32> %a,
62 <vscale x 4 x i32> %b)
63 ret <vscale x 4 x i32> %out
66 define <vscale x 2 x i64> @adrw_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
67 ; CHECK-LABEL: adrw_i64:
69 ; CHECK-NEXT: adr z0.d, [z0.d, z1.d, lsl #2]
71 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64> %a,
72 <vscale x 2 x i64> %b)
73 ret <vscale x 2 x i64> %out
80 define <vscale x 4 x i32> @adrd_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
81 ; CHECK-LABEL: adrd_i32:
83 ; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #3]
85 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32> %a,
86 <vscale x 4 x i32> %b)
87 ret <vscale x 4 x i32> %out
90 define <vscale x 2 x i64> @adrd_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
91 ; CHECK-LABEL: adrd_i64:
93 ; CHECK-NEXT: adr z0.d, [z0.d, z1.d, lsl #3]
95 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64> %a,
96 <vscale x 2 x i64> %b)
97 ret <vscale x 2 x i64> %out
100 declare <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
101 declare <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
103 declare <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
104 declare <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
106 declare <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
107 declare <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
109 declare <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
110 declare <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)