| blob | 557aa010b3a7d9565e2c9e6e178f2071ddd0ef4d |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2 ; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon -verify-machineinstrs < %s | FileCheck %s
4 ; Basic tests from input vector to bitmask
5 ; IR generated from clang for:
6 ; __builtin_convertvector + reinterpret_cast<uint16&>
8 define i16 @convert_to_bitmask16(<16 x i8> %vec) {
9 ; Bits used in mask
10 ; CHECK-LABEL: convert_to_bitmask16:
11 ; CHECK: ; %bb.0:
12 ; CHECK-NEXT: Lloh0:
13 ; CHECK-NEXT: adrp x8, lCPI0_0@PAGE
14 ; CHECK-NEXT: cmeq.16b v0, v0, #0
15 ; CHECK-NEXT: Lloh1:
16 ; CHECK-NEXT: ldr q1, [x8, lCPI0_0@PAGEOFF]
17 ; CHECK-NEXT: bic.16b v0, v1, v0
18 ; CHECK-NEXT: ext.16b v1, v0, v0, #8
19 ; CHECK-NEXT: zip1.16b v0, v0, v1
20 ; CHECK-NEXT: addv.8h h0, v0
21 ; CHECK-NEXT: fmov w0, s0
22 ; CHECK-NEXT: ret
23 ; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1
25 ; Actual conversion
27 %cmp_result = icmp ne <16 x i8> %vec, zeroinitializer
28 %bitmask = bitcast <16 x i1> %cmp_result to i16
29 ret i16 %bitmask
30 }
32 define i16 @convert_to_bitmask8(<8 x i16> %vec) {
33 ; CHECK-LABEL: convert_to_bitmask8:
34 ; CHECK: ; %bb.0:
35 ; CHECK-NEXT: Lloh2:
36 ; CHECK-NEXT: adrp x8, lCPI1_0@PAGE
37 ; CHECK-NEXT: cmeq.8h v0, v0, #0
38 ; CHECK-NEXT: Lloh3:
39 ; CHECK-NEXT: ldr q1, [x8, lCPI1_0@PAGEOFF]
40 ; CHECK-NEXT: bic.16b v0, v1, v0
41 ; CHECK-NEXT: addv.8h h0, v0
42 ; CHECK-NEXT: fmov w8, s0
43 ; CHECK-NEXT: and w0, w8, #0xff
44 ; CHECK-NEXT: ret
45 ; CHECK-NEXT: .loh AdrpLdr Lloh2, Lloh3
48 %cmp_result = icmp ne <8 x i16> %vec, zeroinitializer
49 %bitmask = bitcast <8 x i1> %cmp_result to i8
50 %extended_bitmask = zext i8 %bitmask to i16
51 ret i16 %extended_bitmask
52 }
54 define i4 @convert_to_bitmask4(<4 x i32> %vec) {
55 ; CHECK-LABEL: convert_to_bitmask4:
56 ; CHECK: ; %bb.0:
57 ; CHECK-NEXT: Lloh4:
58 ; CHECK-NEXT: adrp x8, lCPI2_0@PAGE
59 ; CHECK-NEXT: cmeq.4s v0, v0, #0
60 ; CHECK-NEXT: Lloh5:
61 ; CHECK-NEXT: ldr q1, [x8, lCPI2_0@PAGEOFF]
62 ; CHECK-NEXT: bic.16b v0, v1, v0
63 ; CHECK-NEXT: addv.4s s0, v0
64 ; CHECK-NEXT: fmov w0, s0
65 ; CHECK-NEXT: ret
66 ; CHECK-NEXT: .loh AdrpLdr Lloh4, Lloh5
69 %cmp_result = icmp ne <4 x i32> %vec, zeroinitializer
70 %bitmask = bitcast <4 x i1> %cmp_result to i4
71 ret i4 %bitmask
72 }
74 define i8 @convert_to_bitmask2(<2 x i64> %vec) {
75 ; CHECK-LABEL: convert_to_bitmask2:
76 ; CHECK: ; %bb.0:
77 ; CHECK-NEXT: Lloh6:
78 ; CHECK-NEXT: adrp x8, lCPI3_0@PAGE
79 ; CHECK-NEXT: cmeq.2d v0, v0, #0
80 ; CHECK-NEXT: Lloh7:
81 ; CHECK-NEXT: ldr q1, [x8, lCPI3_0@PAGEOFF]
82 ; CHECK-NEXT: bic.16b v0, v1, v0
83 ; CHECK-NEXT: addp.2d d0, v0
84 ; CHECK-NEXT: fmov x8, d0
85 ; CHECK-NEXT: and w0, w8, #0x3
86 ; CHECK-NEXT: ret
87 ; CHECK-NEXT: .loh AdrpLdr Lloh6, Lloh7
90 %cmp_result = icmp ne <2 x i64> %vec, zeroinitializer
91 %bitmask = bitcast <2 x i1> %cmp_result to i2
92 %extended_bitmask = zext i2 %bitmask to i8
93 ret i8 %extended_bitmask
94 }
96 ; Clang's __builtin_convertvector adds an undef vector concat for vectors with <8 elements.
97 define i8 @clang_builtins_undef_concat_convert_to_bitmask4(<4 x i32> %vec) {
98 ; CHECK-LABEL: clang_builtins_undef_concat_convert_to_bitmask4:
99 ; CHECK: ; %bb.0:
100 ; CHECK-NEXT: Lloh8:
101 ; CHECK-NEXT: adrp x8, lCPI4_0@PAGE
102 ; CHECK-NEXT: cmeq.4s v0, v0, #0
103 ; CHECK-NEXT: Lloh9:
104 ; CHECK-NEXT: ldr q1, [x8, lCPI4_0@PAGEOFF]
105 ; CHECK-NEXT: bic.16b v0, v1, v0
106 ; CHECK-NEXT: addv.4s s0, v0
107 ; CHECK-NEXT: fmov w0, s0
108 ; CHECK-NEXT: ret
109 ; CHECK-NEXT: .loh AdrpLdr Lloh8, Lloh9
112 %cmp_result = icmp ne <4 x i32> %vec, zeroinitializer
113 %vector_pad = shufflevector <4 x i1> %cmp_result, <4 x i1> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
114 %bitmask = bitcast <8 x i1> %vector_pad to i8
115 ret i8 %bitmask
116 }
119 define i4 @convert_to_bitmask_no_compare(<4 x i32> %vec1, <4 x i32> %vec2) {
120 ; CHECK-LABEL: convert_to_bitmask_no_compare:
121 ; CHECK: ; %bb.0:
122 ; CHECK-NEXT: and.16b v0, v0, v1
123 ; CHECK-NEXT: Lloh10:
124 ; CHECK-NEXT: adrp x8, lCPI5_0@PAGE
125 ; CHECK-NEXT: Lloh11:
126 ; CHECK-NEXT: ldr q1, [x8, lCPI5_0@PAGEOFF]
127 ; CHECK-NEXT: shl.4s v0, v0, #31
128 ; CHECK-NEXT: cmlt.4s v0, v0, #0
129 ; CHECK-NEXT: and.16b v0, v0, v1
130 ; CHECK-NEXT: addv.4s s0, v0
131 ; CHECK-NEXT: fmov w0, s0
132 ; CHECK-NEXT: ret
133 ; CHECK-NEXT: .loh AdrpLdr Lloh10, Lloh11
136 %cmp = and <4 x i32> %vec1, %vec2
137 %trunc = trunc <4 x i32> %cmp to <4 x i1>
138 %bitmask = bitcast <4 x i1> %trunc to i4
139 ret i4 %bitmask
140 }
142 define i4 @convert_to_bitmask_with_compare_chain(<4 x i32> %vec1, <4 x i32> %vec2) {
143 ; CHECK-LABEL: convert_to_bitmask_with_compare_chain:
144 ; CHECK: ; %bb.0:
145 ; CHECK-NEXT: cmeq.4s v2, v0, #0
146 ; CHECK-NEXT: cmeq.4s v0, v0, v1
147 ; CHECK-NEXT: Lloh12:
148 ; CHECK-NEXT: adrp x8, lCPI6_0@PAGE
149 ; CHECK-NEXT: Lloh13:
150 ; CHECK-NEXT: ldr q1, [x8, lCPI6_0@PAGEOFF]
151 ; CHECK-NEXT: bic.16b v0, v0, v2
152 ; CHECK-NEXT: and.16b v0, v0, v1
153 ; CHECK-NEXT: addv.4s s0, v0
154 ; CHECK-NEXT: fmov w0, s0
155 ; CHECK-NEXT: ret
156 ; CHECK-NEXT: .loh AdrpLdr Lloh12, Lloh13
159 %cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer
160 %cmp2 = icmp eq <4 x i32> %vec1, %vec2
161 %cmp3 = and <4 x i1> %cmp1, %cmp2
162 %bitmask = bitcast <4 x i1> %cmp3 to i4
163 ret i4 %bitmask
164 }
166 define i4 @convert_to_bitmask_with_trunc_in_chain(<4 x i32> %vec1, <4 x i32> %vec2) {
167 ; CHECK-LABEL: convert_to_bitmask_with_trunc_in_chain:
168 ; CHECK: ; %bb.0:
169 ; CHECK-NEXT: cmeq.4s v0, v0, #0
170 ; CHECK-NEXT: Lloh14:
171 ; CHECK-NEXT: adrp x8, lCPI7_0@PAGE
172 ; CHECK-NEXT: bic.16b v0, v1, v0
173 ; CHECK-NEXT: Lloh15:
174 ; CHECK-NEXT: ldr q1, [x8, lCPI7_0@PAGEOFF]
175 ; CHECK-NEXT: shl.4s v0, v0, #31
176 ; CHECK-NEXT: cmlt.4s v0, v0, #0
177 ; CHECK-NEXT: and.16b v0, v0, v1
178 ; CHECK-NEXT: addv.4s s0, v0
179 ; CHECK-NEXT: fmov w0, s0
180 ; CHECK-NEXT: ret
181 ; CHECK-NEXT: .loh AdrpLdr Lloh14, Lloh15
184 %cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer
185 %trunc_vec = trunc <4 x i32> %vec2 to <4 x i1>
186 %and_res = and <4 x i1> %cmp1, %trunc_vec
187 %bitmask = bitcast <4 x i1> %and_res to i4
188 ret i4 %bitmask
189 }
191 define i4 @convert_to_bitmask_with_unknown_type_in_long_chain(<4 x i32> %vec1, <4 x i32> %vec2) {
192 ; CHECK-LABEL: convert_to_bitmask_with_unknown_type_in_long_chain:
193 ; CHECK: ; %bb.0:
194 ; CHECK-NEXT: cmeq.4s v0, v0, #0
195 ; CHECK-NEXT: cmeq.4s v1, v1, #0
196 ; CHECK-NEXT: Lloh16:
197 ; CHECK-NEXT: adrp x8, lCPI8_0@PAGE
198 ; CHECK-NEXT: movi d2, #0x000000ffffffff
199 ; CHECK-NEXT: movi d3, #0x00ffffffffffff
200 ; CHECK-NEXT: bic.16b v0, v1, v0
201 ; CHECK-NEXT: movi d1, #0xffff0000ffff0000
202 ; CHECK-NEXT: xtn.4h v0, v0
203 ; CHECK-NEXT: orr.8b v0, v0, v2
204 ; CHECK-NEXT: movi d2, #0x00ffffffff0000
205 ; CHECK-NEXT: eor.8b v1, v0, v1
206 ; CHECK-NEXT: eor.8b v0, v0, v2
207 ; CHECK-NEXT: mov.h v1[2], wzr
208 ; CHECK-NEXT: orr.8b v0, v0, v3
209 ; CHECK-NEXT: orr.8b v0, v1, v0
210 ; CHECK-NEXT: Lloh17:
211 ; CHECK-NEXT: ldr d1, [x8, lCPI8_0@PAGEOFF]
212 ; CHECK-NEXT: shl.4h v0, v0, #15
213 ; CHECK-NEXT: cmlt.4h v0, v0, #0
214 ; CHECK-NEXT: and.8b v0, v0, v1
215 ; CHECK-NEXT: addv.4h h0, v0
216 ; CHECK-NEXT: fmov w0, s0
217 ; CHECK-NEXT: ret
218 ; CHECK-NEXT: .loh AdrpLdr Lloh16, Lloh17
221 %cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer
222 %cmp2 = icmp eq <4 x i32> %vec2, zeroinitializer
224 ; Artificially make this a long chain to hide the original type
225 %chain1 = and <4 x i1> %cmp1, %cmp2;
226 %chain2 = or <4 x i1> %chain1, <i1 1, i1 1, i1 0, i1 0>;
227 %chain3 = xor <4 x i1> %chain2, <i1 0, i1 1, i1 0, i1 1>;
228 %chain4 = and <4 x i1> %chain3, <i1 1, i1 1, i1 0, i1 1>;
229 %chain5 = or <4 x i1> %chain4, <i1 1, i1 1, i1 1, i1 0>;
230 %chain6 = xor <4 x i1> <i1 0, i1 1, i1 1, i1 0>, %chain2;
231 %chain7 = or <4 x i1> %chain5, %chain6;
232 %bitmask = bitcast <4 x i1> %chain7 to i4
233 ret i4 %bitmask
234 }
236 define i4 @convert_to_bitmask_with_different_types_in_chain(<4 x i16> %vec1, <4 x i32> %vec2) {
237 ; CHECK-LABEL: convert_to_bitmask_with_different_types_in_chain:
238 ; CHECK: ; %bb.0:
239 ; CHECK-NEXT: cmeq.4s v1, v1, #0
240 ; CHECK-NEXT: cmeq.4h v0, v0, #0
241 ; CHECK-NEXT: Lloh18:
242 ; CHECK-NEXT: adrp x8, lCPI9_0@PAGE
243 ; CHECK-NEXT: xtn.4h v1, v1
244 ; CHECK-NEXT: orn.8b v0, v1, v0
245 ; CHECK-NEXT: Lloh19:
246 ; CHECK-NEXT: ldr d1, [x8, lCPI9_0@PAGEOFF]
247 ; CHECK-NEXT: and.8b v0, v0, v1
248 ; CHECK-NEXT: addv.4h h0, v0
249 ; CHECK-NEXT: fmov w0, s0
250 ; CHECK-NEXT: ret
251 ; CHECK-NEXT: .loh AdrpLdr Lloh18, Lloh19
254 %cmp1 = icmp ne <4 x i16> %vec1, zeroinitializer
255 %cmp2 = icmp eq <4 x i32> %vec2, zeroinitializer
256 %chain1 = or <4 x i1> %cmp1, %cmp2
257 %bitmask = bitcast <4 x i1> %chain1 to i4
258 ret i4 %bitmask
259 }
261 define i16 @convert_to_bitmask_without_knowing_type(<16 x i1> %vec) {
262 ; CHECK-LABEL: convert_to_bitmask_without_knowing_type:
263 ; CHECK: ; %bb.0:
264 ; CHECK-NEXT: shl.16b v0, v0, #7
265 ; CHECK-NEXT: Lloh20:
266 ; CHECK-NEXT: adrp x8, lCPI10_0@PAGE
267 ; CHECK-NEXT: Lloh21:
268 ; CHECK-NEXT: ldr q1, [x8, lCPI10_0@PAGEOFF]
269 ; CHECK-NEXT: cmlt.16b v0, v0, #0
270 ; CHECK-NEXT: and.16b v0, v0, v1
271 ; CHECK-NEXT: ext.16b v1, v0, v0, #8
272 ; CHECK-NEXT: zip1.16b v0, v0, v1
273 ; CHECK-NEXT: addv.8h h0, v0
274 ; CHECK-NEXT: fmov w0, s0
275 ; CHECK-NEXT: ret
276 ; CHECK-NEXT: .loh AdrpLdr Lloh20, Lloh21
278 %bitmask = bitcast <16 x i1> %vec to i16
279 ret i16 %bitmask
280 }
282 define i2 @convert_to_bitmask_2xi32(<2 x i32> %vec) {
283 ; CHECK-LABEL: convert_to_bitmask_2xi32:
284 ; CHECK: ; %bb.0:
285 ; CHECK-NEXT: Lloh22:
286 ; CHECK-NEXT: adrp x8, lCPI11_0@PAGE
287 ; CHECK-NEXT: cmeq.2s v0, v0, #0
288 ; CHECK-NEXT: Lloh23:
289 ; CHECK-NEXT: ldr d1, [x8, lCPI11_0@PAGEOFF]
290 ; CHECK-NEXT: bic.8b v0, v1, v0
291 ; CHECK-NEXT: addp.2s v0, v0, v0
292 ; CHECK-NEXT: fmov w0, s0
293 ; CHECK-NEXT: ret
294 ; CHECK-NEXT: .loh AdrpLdr Lloh22, Lloh23
296 %cmp_result = icmp ne <2 x i32> %vec, zeroinitializer
297 %bitmask = bitcast <2 x i1> %cmp_result to i2
298 ret i2 %bitmask
299 }
301 define i4 @convert_to_bitmask_4xi8(<4 x i8> %vec) {
302 ; CHECK-LABEL: convert_to_bitmask_4xi8:
303 ; CHECK: ; %bb.0:
304 ; CHECK-NEXT: bic.4h v0, #255, lsl #8
305 ; CHECK-NEXT: Lloh24:
306 ; CHECK-NEXT: adrp x8, lCPI12_0@PAGE
307 ; CHECK-NEXT: Lloh25:
308 ; CHECK-NEXT: ldr d1, [x8, lCPI12_0@PAGEOFF]
309 ; CHECK-NEXT: cmeq.4h v0, v0, #0
310 ; CHECK-NEXT: bic.8b v0, v1, v0
311 ; CHECK-NEXT: addv.4h h0, v0
312 ; CHECK-NEXT: fmov w0, s0
313 ; CHECK-NEXT: ret
314 ; CHECK-NEXT: .loh AdrpLdr Lloh24, Lloh25
316 %cmp_result = icmp ne <4 x i8> %vec, zeroinitializer
317 %bitmask = bitcast <4 x i1> %cmp_result to i4
318 ret i4 %bitmask
319 }
321 define i8 @convert_to_bitmask_8xi2(<8 x i2> %vec) {
322 ; CHECK-LABEL: convert_to_bitmask_8xi2:
323 ; CHECK: ; %bb.0:
324 ; CHECK-NEXT: movi.8b v1, #3
325 ; CHECK-NEXT: Lloh26:
326 ; CHECK-NEXT: adrp x8, lCPI13_0@PAGE
327 ; CHECK-NEXT: and.8b v0, v0, v1
328 ; CHECK-NEXT: Lloh27:
329 ; CHECK-NEXT: ldr d1, [x8, lCPI13_0@PAGEOFF]
330 ; CHECK-NEXT: cmeq.8b v0, v0, #0
331 ; CHECK-NEXT: bic.8b v0, v1, v0
332 ; CHECK-NEXT: addv.8b b0, v0
333 ; CHECK-NEXT: fmov w0, s0
334 ; CHECK-NEXT: ret
335 ; CHECK-NEXT: .loh AdrpLdr Lloh26, Lloh27
337 %cmp_result = icmp ne <8 x i2> %vec, zeroinitializer
338 %bitmask = bitcast <8 x i1> %cmp_result to i8
339 ret i8 %bitmask
340 }
342 define i4 @convert_to_bitmask_float(<4 x float> %vec) {
343 ; CHECK-LABEL: convert_to_bitmask_float:
344 ; CHECK: ; %bb.0:
345 ; CHECK-NEXT: fcmgt.4s v1, v0, #0.0
346 ; CHECK-NEXT: fcmlt.4s v0, v0, #0.0
347 ; CHECK-NEXT: Lloh28:
348 ; CHECK-NEXT: adrp x8, lCPI14_0@PAGE
349 ; CHECK-NEXT: orr.16b v0, v0, v1
350 ; CHECK-NEXT: Lloh29:
351 ; CHECK-NEXT: ldr q1, [x8, lCPI14_0@PAGEOFF]
352 ; CHECK-NEXT: and.16b v0, v0, v1
353 ; CHECK-NEXT: addv.4s s0, v0
354 ; CHECK-NEXT: fmov w0, s0
355 ; CHECK-NEXT: ret
356 ; CHECK-NEXT: .loh AdrpLdr Lloh28, Lloh29
359 %cmp_result = fcmp one <4 x float> %vec, zeroinitializer
360 %bitmask = bitcast <4 x i1> %cmp_result to i4
361 ret i4 %bitmask
362 }
364 ; Larger vector types don't map directly, but the can be split/truncated and then converted.
365 ; After the comparison against 0, this is truncated to <8 x i16>, which is valid again.
366 define i8 @convert_large_vector(<8 x i32> %vec) {
367 ; CHECK-LABEL: convert_large_vector:
368 ; CHECK: ; %bb.0:
369 ; CHECK-NEXT: sub sp, sp, #16
370 ; CHECK-NEXT: .cfi_def_cfa_offset 16
371 ; CHECK-NEXT: cmeq.4s v1, v1, #0
372 ; CHECK-NEXT: cmeq.4s v0, v0, #0
373 ; CHECK-NEXT: Lloh30:
374 ; CHECK-NEXT: adrp x8, lCPI15_0@PAGE
375 ; CHECK-NEXT: uzp1.8h v0, v0, v1
376 ; CHECK-NEXT: Lloh31:
377 ; CHECK-NEXT: ldr q1, [x8, lCPI15_0@PAGEOFF]
378 ; CHECK-NEXT: bic.16b v0, v1, v0
379 ; CHECK-NEXT: addv.8h h0, v0
380 ; CHECK-NEXT: fmov w8, s0
381 ; CHECK-NEXT: and w0, w8, #0xff
382 ; CHECK-NEXT: add sp, sp, #16
383 ; CHECK-NEXT: ret
384 ; CHECK-NEXT: .loh AdrpLdr Lloh30, Lloh31
387 %cmp_result = icmp ne <8 x i32> %vec, zeroinitializer
388 %bitmask = bitcast <8 x i1> %cmp_result to i8
389 ret i8 %bitmask
390 }
392 define i4 @convert_legalized_illegal_element_size(<4 x i22> %vec) {
393 ; CHECK-LABEL: convert_legalized_illegal_element_size:
394 ; CHECK: ; %bb.0:
395 ; CHECK-NEXT: movi.4s v1, #63, msl #16
396 ; CHECK-NEXT: Lloh32:
397 ; CHECK-NEXT: adrp x8, lCPI16_0@PAGE
398 ; CHECK-NEXT: cmtst.4s v0, v0, v1
399 ; CHECK-NEXT: Lloh33:
400 ; CHECK-NEXT: ldr d1, [x8, lCPI16_0@PAGEOFF]
401 ; CHECK-NEXT: xtn.4h v0, v0
402 ; CHECK-NEXT: and.8b v0, v0, v1
403 ; CHECK-NEXT: addv.4h h0, v0
404 ; CHECK-NEXT: fmov w0, s0
405 ; CHECK-NEXT: ret
406 ; CHECK-NEXT: .loh AdrpLdr Lloh32, Lloh33
408 %cmp_result = icmp ne <4 x i22> %vec, zeroinitializer
409 %bitmask = bitcast <4 x i1> %cmp_result to i4
410 ret i4 %bitmask
411 }
413 ; This may still be converted as a v8i8 after the vector concat (but not as v4iX).
414 define i8 @no_direct_convert_for_bad_concat(<4 x i32> %vec) {
415 ; CHECK-LABEL: no_direct_convert_for_bad_concat:
416 ; CHECK: ; %bb.0:
417 ; CHECK-NEXT: cmtst.4s v0, v0, v0
418 ; CHECK-NEXT: Lloh34:
419 ; CHECK-NEXT: adrp x8, lCPI17_0@PAGE
420 ; CHECK-NEXT: xtn.4h v0, v0
421 ; CHECK-NEXT: umov.h w9, v0[0]
422 ; CHECK-NEXT: mov.b v1[4], w9
423 ; CHECK-NEXT: umov.h w9, v0[1]
424 ; CHECK-NEXT: mov.b v1[5], w9
425 ; CHECK-NEXT: umov.h w9, v0[2]
426 ; CHECK-NEXT: mov.b v1[6], w9
427 ; CHECK-NEXT: umov.h w9, v0[3]
428 ; CHECK-NEXT: mov.b v1[7], w9
429 ; CHECK-NEXT: shl.8b v0, v1, #7
430 ; CHECK-NEXT: Lloh35:
431 ; CHECK-NEXT: ldr d1, [x8, lCPI17_0@PAGEOFF]
432 ; CHECK-NEXT: cmlt.8b v0, v0, #0
433 ; CHECK-NEXT: and.8b v0, v0, v1
434 ; CHECK-NEXT: addv.8b b0, v0
435 ; CHECK-NEXT: fmov w0, s0
436 ; CHECK-NEXT: ret
437 ; CHECK-NEXT: .loh AdrpLdr Lloh34, Lloh35
439 %cmp_result = icmp ne <4 x i32> %vec, zeroinitializer
440 %vector_pad = shufflevector <4 x i1> poison, <4 x i1> %cmp_result, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 4, i32 5, i32 6, i32 7>
441 %bitmask = bitcast <8 x i1> %vector_pad to i8
442 ret i8 %bitmask
443 }
445 define <8 x i1> @no_convert_without_direct_bitcast(<8 x i16> %vec) {
446 ; CHECK-LABEL: no_convert_without_direct_bitcast:
447 ; CHECK: ; %bb.0:
448 ; CHECK-NEXT: cmtst.8h v0, v0, v0
449 ; CHECK-NEXT: xtn.8b v0, v0
450 ; CHECK-NEXT: ret
452 %cmp_result = icmp ne <8 x i16> %vec, zeroinitializer
453 ret <8 x i1> %cmp_result
454 }
456 define i6 @no_combine_illegal_num_elements(<6 x i32> %vec) {
457 ; CHECK-LABEL: no_combine_illegal_num_elements:
458 ; CHECK: ; %bb.0:
459 ; CHECK-NEXT: sub sp, sp, #16
460 ; CHECK-NEXT: .cfi_def_cfa_offset 16
461 ; CHECK-NEXT: fmov s0, w0
462 ; CHECK-NEXT: fmov s1, w4
463 ; CHECK-NEXT: mov.s v0[1], w1
464 ; CHECK-NEXT: mov.s v1[1], w5
465 ; CHECK-NEXT: mov.s v0[2], w2
466 ; CHECK-NEXT: cmeq.4s v1, v1, #0
467 ; CHECK-NEXT: mov.s v0[3], w3
468 ; CHECK-NEXT: cmeq.4s v0, v0, #0
469 ; CHECK-NEXT: uzp1.8h v0, v0, v1
470 ; CHECK-NEXT: mvn.16b v0, v0
471 ; CHECK-NEXT: xtn.8b v0, v0
472 ; CHECK-NEXT: umov.b w8, v0[0]
473 ; CHECK-NEXT: umov.b w9, v0[1]
474 ; CHECK-NEXT: umov.b w10, v0[2]
475 ; CHECK-NEXT: and w8, w8, #0x1
476 ; CHECK-NEXT: bfi w8, w9, #1, #1
477 ; CHECK-NEXT: umov.b w9, v0[3]
478 ; CHECK-NEXT: bfi w8, w10, #2, #1
479 ; CHECK-NEXT: umov.b w10, v0[4]
480 ; CHECK-NEXT: bfi w8, w9, #3, #1
481 ; CHECK-NEXT: umov.b w9, v0[5]
482 ; CHECK-NEXT: bfi w8, w10, #4, #1
483 ; CHECK-NEXT: orr w8, w8, w9, lsl #5
484 ; CHECK-NEXT: and w0, w8, #0x3f
485 ; CHECK-NEXT: add sp, sp, #16
486 ; CHECK-NEXT: ret
488 %cmp_result = icmp ne <6 x i32> %vec, zeroinitializer
489 %bitmask = bitcast <6 x i1> %cmp_result to i6
490 ret i6 %bitmask
491 }
493 ; Only apply the combine when casting a vector to a scalar.
494 define <2 x i8> @vector_to_vector_cast(<16 x i1> %arg) nounwind {
495 ; CHECK-LABEL: vector_to_vector_cast:
496 ; CHECK: ; %bb.0:
497 ; CHECK-NEXT: sub sp, sp, #16
498 ; CHECK-NEXT: shl.16b v0, v0, #7
499 ; CHECK-NEXT: Lloh36:
500 ; CHECK-NEXT: adrp x8, lCPI20_0@PAGE
501 ; CHECK-NEXT: Lloh37:
502 ; CHECK-NEXT: ldr q1, [x8, lCPI20_0@PAGEOFF]
503 ; CHECK-NEXT: add x8, sp, #14
504 ; CHECK-NEXT: cmlt.16b v0, v0, #0
505 ; CHECK-NEXT: and.16b v0, v0, v1
506 ; CHECK-NEXT: ext.16b v1, v0, v0, #8
507 ; CHECK-NEXT: zip1.16b v0, v0, v1
508 ; CHECK-NEXT: addv.8h h0, v0
509 ; CHECK-NEXT: str h0, [sp, #14]
510 ; CHECK-NEXT: ld1.b { v0 }[0], [x8]
511 ; CHECK-NEXT: orr x8, x8, #0x1
512 ; CHECK-NEXT: ld1.b { v0 }[4], [x8]
513 ; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
514 ; CHECK-NEXT: add sp, sp, #16
515 ; CHECK-NEXT: ret
516 ; CHECK-NEXT: .loh AdrpLdr Lloh36, Lloh37
517 %bc = bitcast <16 x i1> %arg to <2 x i8>
518 ret <2 x i8> %bc
519 }