| blob | 5503de2b4c5db9a0a6e366d6246dd796947a36da |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
4 define <1 x i64> @llrint_v1i64_v1f16(<1 x half> %x) {
5 ; CHECK-LABEL: llrint_v1i64_v1f16:
6 ; CHECK: // %bb.0:
7 ; CHECK-NEXT: fcvt s0, h0
8 ; CHECK-NEXT: frintx s0, s0
9 ; CHECK-NEXT: fcvtzs x8, s0
10 ; CHECK-NEXT: fmov d0, x8
11 ; CHECK-NEXT: ret
12 %a = call <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half> %x)
13 ret <1 x i64> %a
14 }
15 declare <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half>)
17 define <2 x i64> @llrint_v1i64_v2f16(<2 x half> %x) {
18 ; CHECK-LABEL: llrint_v1i64_v2f16:
19 ; CHECK: // %bb.0:
20 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
21 ; CHECK-NEXT: mov h1, v0.h[1]
22 ; CHECK-NEXT: fcvt s0, h0
23 ; CHECK-NEXT: fcvt s1, h1
24 ; CHECK-NEXT: frintx s0, s0
25 ; CHECK-NEXT: frintx s1, s1
26 ; CHECK-NEXT: fcvtzs x8, s0
27 ; CHECK-NEXT: fcvtzs x9, s1
28 ; CHECK-NEXT: fmov d0, x8
29 ; CHECK-NEXT: mov v0.d[1], x9
30 ; CHECK-NEXT: ret
31 %a = call <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half> %x)
32 ret <2 x i64> %a
33 }
34 declare <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half>)
36 define <4 x i64> @llrint_v4i64_v4f16(<4 x half> %x) {
37 ; CHECK-LABEL: llrint_v4i64_v4f16:
38 ; CHECK: // %bb.0:
39 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
40 ; CHECK-NEXT: mov h1, v0.h[2]
41 ; CHECK-NEXT: mov h2, v0.h[1]
42 ; CHECK-NEXT: mov h3, v0.h[3]
43 ; CHECK-NEXT: fcvt s0, h0
44 ; CHECK-NEXT: fcvt s1, h1
45 ; CHECK-NEXT: fcvt s2, h2
46 ; CHECK-NEXT: fcvt s3, h3
47 ; CHECK-NEXT: frintx s0, s0
48 ; CHECK-NEXT: frintx s1, s1
49 ; CHECK-NEXT: frintx s2, s2
50 ; CHECK-NEXT: frintx s3, s3
51 ; CHECK-NEXT: fcvtzs x8, s0
52 ; CHECK-NEXT: fcvtzs x9, s1
53 ; CHECK-NEXT: fcvtzs x10, s2
54 ; CHECK-NEXT: fcvtzs x11, s3
55 ; CHECK-NEXT: fmov d0, x8
56 ; CHECK-NEXT: fmov d1, x9
57 ; CHECK-NEXT: mov v0.d[1], x10
58 ; CHECK-NEXT: mov v1.d[1], x11
59 ; CHECK-NEXT: ret
60 %a = call <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half> %x)
61 ret <4 x i64> %a
62 }
63 declare <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half>)
65 define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) {
66 ; CHECK-LABEL: llrint_v8i64_v8f16:
67 ; CHECK: // %bb.0:
68 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
69 ; CHECK-NEXT: mov h4, v0.h[2]
70 ; CHECK-NEXT: mov h3, v0.h[1]
71 ; CHECK-NEXT: mov h7, v0.h[3]
72 ; CHECK-NEXT: fcvt s0, h0
73 ; CHECK-NEXT: mov h2, v1.h[2]
74 ; CHECK-NEXT: mov h5, v1.h[1]
75 ; CHECK-NEXT: mov h6, v1.h[3]
76 ; CHECK-NEXT: fcvt s1, h1
77 ; CHECK-NEXT: fcvt s4, h4
78 ; CHECK-NEXT: fcvt s3, h3
79 ; CHECK-NEXT: fcvt s7, h7
80 ; CHECK-NEXT: frintx s0, s0
81 ; CHECK-NEXT: fcvt s2, h2
82 ; CHECK-NEXT: fcvt s5, h5
83 ; CHECK-NEXT: fcvt s6, h6
84 ; CHECK-NEXT: frintx s1, s1
85 ; CHECK-NEXT: frintx s4, s4
86 ; CHECK-NEXT: frintx s3, s3
87 ; CHECK-NEXT: frintx s7, s7
88 ; CHECK-NEXT: fcvtzs x9, s0
89 ; CHECK-NEXT: frintx s2, s2
90 ; CHECK-NEXT: frintx s5, s5
91 ; CHECK-NEXT: frintx s6, s6
92 ; CHECK-NEXT: fcvtzs x8, s1
93 ; CHECK-NEXT: fcvtzs x12, s4
94 ; CHECK-NEXT: fcvtzs x11, s3
95 ; CHECK-NEXT: fcvtzs x15, s7
96 ; CHECK-NEXT: fmov d0, x9
97 ; CHECK-NEXT: fcvtzs x10, s2
98 ; CHECK-NEXT: fcvtzs x13, s5
99 ; CHECK-NEXT: fcvtzs x14, s6
100 ; CHECK-NEXT: fmov d2, x8
101 ; CHECK-NEXT: fmov d1, x12
102 ; CHECK-NEXT: mov v0.d[1], x11
103 ; CHECK-NEXT: fmov d3, x10
104 ; CHECK-NEXT: mov v2.d[1], x13
105 ; CHECK-NEXT: mov v1.d[1], x15
106 ; CHECK-NEXT: mov v3.d[1], x14
107 ; CHECK-NEXT: ret
108 %a = call <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half> %x)
109 ret <8 x i64> %a
110 }
111 declare <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half>)
113 define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) {
114 ; CHECK-LABEL: llrint_v16i64_v16f16:
115 ; CHECK: // %bb.0:
116 ; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
117 ; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
118 ; CHECK-NEXT: mov h17, v0.h[1]
119 ; CHECK-NEXT: mov h19, v0.h[2]
120 ; CHECK-NEXT: fcvt s18, h0
121 ; CHECK-NEXT: mov h0, v0.h[3]
122 ; CHECK-NEXT: mov h4, v2.h[1]
123 ; CHECK-NEXT: mov h5, v2.h[2]
124 ; CHECK-NEXT: fcvt s7, h3
125 ; CHECK-NEXT: fcvt s6, h2
126 ; CHECK-NEXT: mov h16, v3.h[2]
127 ; CHECK-NEXT: mov h2, v2.h[3]
128 ; CHECK-NEXT: fcvt s17, h17
129 ; CHECK-NEXT: fcvt s19, h19
130 ; CHECK-NEXT: frintx s18, s18
131 ; CHECK-NEXT: fcvt s0, h0
132 ; CHECK-NEXT: fcvt s4, h4
133 ; CHECK-NEXT: fcvt s5, h5
134 ; CHECK-NEXT: frintx s7, s7
135 ; CHECK-NEXT: frintx s6, s6
136 ; CHECK-NEXT: fcvt s16, h16
137 ; CHECK-NEXT: fcvt s2, h2
138 ; CHECK-NEXT: frintx s17, s17
139 ; CHECK-NEXT: frintx s19, s19
140 ; CHECK-NEXT: fcvtzs x13, s18
141 ; CHECK-NEXT: frintx s0, s0
142 ; CHECK-NEXT: frintx s4, s4
143 ; CHECK-NEXT: frintx s5, s5
144 ; CHECK-NEXT: fcvtzs x9, s7
145 ; CHECK-NEXT: mov h7, v1.h[2]
146 ; CHECK-NEXT: fcvtzs x8, s6
147 ; CHECK-NEXT: mov h6, v1.h[1]
148 ; CHECK-NEXT: frintx s16, s16
149 ; CHECK-NEXT: fcvtzs x14, s17
150 ; CHECK-NEXT: fcvtzs x15, s19
151 ; CHECK-NEXT: fcvtzs x10, s4
152 ; CHECK-NEXT: mov h4, v3.h[1]
153 ; CHECK-NEXT: fcvtzs x11, s5
154 ; CHECK-NEXT: mov h5, v1.h[3]
155 ; CHECK-NEXT: mov h3, v3.h[3]
156 ; CHECK-NEXT: fcvt s1, h1
157 ; CHECK-NEXT: fcvt s7, h7
158 ; CHECK-NEXT: fcvt s6, h6
159 ; CHECK-NEXT: fcvtzs x12, s16
160 ; CHECK-NEXT: frintx s16, s2
161 ; CHECK-NEXT: fmov d2, x8
162 ; CHECK-NEXT: fcvt s4, h4
163 ; CHECK-NEXT: fcvt s3, h3
164 ; CHECK-NEXT: fcvt s5, h5
165 ; CHECK-NEXT: frintx s1, s1
166 ; CHECK-NEXT: frintx s7, s7
167 ; CHECK-NEXT: frintx s17, s6
168 ; CHECK-NEXT: fmov d6, x9
169 ; CHECK-NEXT: mov v2.d[1], x10
170 ; CHECK-NEXT: frintx s4, s4
171 ; CHECK-NEXT: frintx s18, s3
172 ; CHECK-NEXT: frintx s5, s5
173 ; CHECK-NEXT: fcvtzs x8, s1
174 ; CHECK-NEXT: fcvtzs x9, s7
175 ; CHECK-NEXT: fmov d3, x11
176 ; CHECK-NEXT: fcvtzs x11, s0
177 ; CHECK-NEXT: fmov d7, x12
178 ; CHECK-NEXT: fcvtzs x12, s16
179 ; CHECK-NEXT: fcvtzs x16, s17
180 ; CHECK-NEXT: fcvtzs x17, s4
181 ; CHECK-NEXT: fmov d0, x13
182 ; CHECK-NEXT: fmov d1, x15
183 ; CHECK-NEXT: fcvtzs x18, s18
184 ; CHECK-NEXT: fcvtzs x0, s5
185 ; CHECK-NEXT: fmov d4, x8
186 ; CHECK-NEXT: fmov d5, x9
187 ; CHECK-NEXT: mov v0.d[1], x14
188 ; CHECK-NEXT: mov v1.d[1], x11
189 ; CHECK-NEXT: mov v3.d[1], x12
190 ; CHECK-NEXT: mov v4.d[1], x16
191 ; CHECK-NEXT: mov v6.d[1], x17
192 ; CHECK-NEXT: mov v7.d[1], x18
193 ; CHECK-NEXT: mov v5.d[1], x0
194 ; CHECK-NEXT: ret
195 %a = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> %x)
196 ret <16 x i64> %a
197 }
198 declare <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half>)
200 define <32 x i64> @llrint_v32i64_v32f16(<32 x half> %x) {
201 ; CHECK-LABEL: llrint_v32i64_v32f16:
202 ; CHECK: // %bb.0:
203 ; CHECK-NEXT: ext v4.16b, v1.16b, v1.16b, #8
204 ; CHECK-NEXT: ext v5.16b, v2.16b, v2.16b, #8
205 ; CHECK-NEXT: ext v6.16b, v3.16b, v3.16b, #8
206 ; CHECK-NEXT: ext v7.16b, v0.16b, v0.16b, #8
207 ; CHECK-NEXT: mov h19, v0.h[1]
208 ; CHECK-NEXT: fcvt s21, h0
209 ; CHECK-NEXT: mov h23, v1.h[2]
210 ; CHECK-NEXT: fcvt s22, h1
211 ; CHECK-NEXT: fcvt s26, h2
212 ; CHECK-NEXT: mov h27, v2.h[1]
213 ; CHECK-NEXT: mov h28, v2.h[2]
214 ; CHECK-NEXT: mov h16, v4.h[2]
215 ; CHECK-NEXT: fcvt s17, h5
216 ; CHECK-NEXT: mov h18, v5.h[2]
217 ; CHECK-NEXT: mov h20, v6.h[2]
218 ; CHECK-NEXT: fcvt s24, h7
219 ; CHECK-NEXT: fcvt s25, h6
220 ; CHECK-NEXT: fcvt s19, h19
221 ; CHECK-NEXT: frintx s22, s22
222 ; CHECK-NEXT: fcvt s16, h16
223 ; CHECK-NEXT: frintx s17, s17
224 ; CHECK-NEXT: fcvt s18, h18
225 ; CHECK-NEXT: fcvt s20, h20
226 ; CHECK-NEXT: frintx s16, s16
227 ; CHECK-NEXT: fcvtzs x12, s17
228 ; CHECK-NEXT: frintx s17, s18
229 ; CHECK-NEXT: frintx s18, s21
230 ; CHECK-NEXT: fcvt s21, h23
231 ; CHECK-NEXT: frintx s23, s24
232 ; CHECK-NEXT: frintx s24, s25
233 ; CHECK-NEXT: frintx s25, s19
234 ; CHECK-NEXT: mov h19, v7.h[1]
235 ; CHECK-NEXT: fcvtzs x13, s16
236 ; CHECK-NEXT: frintx s16, s20
237 ; CHECK-NEXT: frintx s20, s26
238 ; CHECK-NEXT: fcvtzs x9, s23
239 ; CHECK-NEXT: mov h23, v3.h[2]
240 ; CHECK-NEXT: fcvt s26, h27
241 ; CHECK-NEXT: fcvtzs x15, s24
242 ; CHECK-NEXT: fcvtzs x10, s25
243 ; CHECK-NEXT: fcvt s24, h28
244 ; CHECK-NEXT: mov h25, v3.h[3]
245 ; CHECK-NEXT: fcvtzs x14, s17
246 ; CHECK-NEXT: frintx s21, s21
247 ; CHECK-NEXT: fmov d17, x12
248 ; CHECK-NEXT: fcvtzs x12, s16
249 ; CHECK-NEXT: fmov d16, x13
250 ; CHECK-NEXT: fcvtzs x13, s22
251 ; CHECK-NEXT: fcvt s22, h3
252 ; CHECK-NEXT: mov h3, v3.h[1]
253 ; CHECK-NEXT: mov h27, v0.h[2]
254 ; CHECK-NEXT: mov h28, v2.h[3]
255 ; CHECK-NEXT: fcvt s23, h23
256 ; CHECK-NEXT: frintx s26, s26
257 ; CHECK-NEXT: fcvtzs x16, s20
258 ; CHECK-NEXT: frintx s20, s24
259 ; CHECK-NEXT: fcvt s24, h25
260 ; CHECK-NEXT: fcvtzs x11, s18
261 ; CHECK-NEXT: fmov d18, x14
262 ; CHECK-NEXT: fcvtzs x14, s21
263 ; CHECK-NEXT: frintx s22, s22
264 ; CHECK-NEXT: fcvt s3, h3
265 ; CHECK-NEXT: fcvt s25, h27
266 ; CHECK-NEXT: fcvt s27, h28
267 ; CHECK-NEXT: frintx s23, s23
268 ; CHECK-NEXT: mov h21, v1.h[3]
269 ; CHECK-NEXT: fmov d2, x15
270 ; CHECK-NEXT: fcvtzs x15, s26
271 ; CHECK-NEXT: fmov d26, x13
272 ; CHECK-NEXT: mov h1, v1.h[1]
273 ; CHECK-NEXT: fcvtzs x13, s20
274 ; CHECK-NEXT: frintx s20, s24
275 ; CHECK-NEXT: fmov d24, x14
276 ; CHECK-NEXT: fcvtzs x14, s22
277 ; CHECK-NEXT: frintx s3, s3
278 ; CHECK-NEXT: fmov d22, x16
279 ; CHECK-NEXT: frintx s27, s27
280 ; CHECK-NEXT: fcvtzs x16, s23
281 ; CHECK-NEXT: fcvt s21, h21
282 ; CHECK-NEXT: frintx s25, s25
283 ; CHECK-NEXT: fcvt s1, h1
284 ; CHECK-NEXT: mov h0, v0.h[3]
285 ; CHECK-NEXT: mov h23, v7.h[2]
286 ; CHECK-NEXT: mov v22.d[1], x15
287 ; CHECK-NEXT: fcvtzs x15, s20
288 ; CHECK-NEXT: fmov d20, x13
289 ; CHECK-NEXT: fcvtzs x13, s3
290 ; CHECK-NEXT: fmov d3, x14
291 ; CHECK-NEXT: fcvtzs x14, s27
292 ; CHECK-NEXT: fmov d27, x16
293 ; CHECK-NEXT: frintx s21, s21
294 ; CHECK-NEXT: mov h7, v7.h[3]
295 ; CHECK-NEXT: frintx s1, s1
296 ; CHECK-NEXT: fcvt s0, h0
297 ; CHECK-NEXT: fcvt s23, h23
298 ; CHECK-NEXT: fcvt s19, h19
299 ; CHECK-NEXT: mov v27.d[1], x15
300 ; CHECK-NEXT: fcvtzs x15, s25
301 ; CHECK-NEXT: mov h25, v6.h[3]
302 ; CHECK-NEXT: mov h6, v6.h[1]
303 ; CHECK-NEXT: mov v3.d[1], x13
304 ; CHECK-NEXT: fcvtzs x13, s21
305 ; CHECK-NEXT: mov h21, v5.h[1]
306 ; CHECK-NEXT: mov h5, v5.h[3]
307 ; CHECK-NEXT: mov v20.d[1], x14
308 ; CHECK-NEXT: fcvtzs x14, s1
309 ; CHECK-NEXT: mov h1, v4.h[1]
310 ; CHECK-NEXT: frintx s0, s0
311 ; CHECK-NEXT: fcvt s25, h25
312 ; CHECK-NEXT: fcvt s7, h7
313 ; CHECK-NEXT: stp q3, q27, [x8, #192]
314 ; CHECK-NEXT: fcvt s6, h6
315 ; CHECK-NEXT: mov h3, v4.h[3]
316 ; CHECK-NEXT: stp q22, q20, [x8, #128]
317 ; CHECK-NEXT: fcvt s21, h21
318 ; CHECK-NEXT: fcvt s5, h5
319 ; CHECK-NEXT: mov v24.d[1], x13
320 ; CHECK-NEXT: mov v26.d[1], x14
321 ; CHECK-NEXT: fcvt s4, h4
322 ; CHECK-NEXT: frintx s22, s25
323 ; CHECK-NEXT: fmov d20, x12
324 ; CHECK-NEXT: fcvt s1, h1
325 ; CHECK-NEXT: frintx s6, s6
326 ; CHECK-NEXT: fcvt s3, h3
327 ; CHECK-NEXT: fcvtzs x12, s0
328 ; CHECK-NEXT: frintx s5, s5
329 ; CHECK-NEXT: frintx s21, s21
330 ; CHECK-NEXT: fmov d0, x11
331 ; CHECK-NEXT: stp q26, q24, [x8, #64]
332 ; CHECK-NEXT: fmov d24, x15
333 ; CHECK-NEXT: frintx s4, s4
334 ; CHECK-NEXT: fcvtzs x11, s22
335 ; CHECK-NEXT: frintx s22, s23
336 ; CHECK-NEXT: frintx s1, s1
337 ; CHECK-NEXT: fcvtzs x13, s6
338 ; CHECK-NEXT: frintx s3, s3
339 ; CHECK-NEXT: frintx s6, s7
340 ; CHECK-NEXT: fcvtzs x14, s5
341 ; CHECK-NEXT: mov v24.d[1], x12
342 ; CHECK-NEXT: frintx s5, s19
343 ; CHECK-NEXT: fcvtzs x12, s21
344 ; CHECK-NEXT: mov v0.d[1], x10
345 ; CHECK-NEXT: fcvtzs x10, s4
346 ; CHECK-NEXT: mov v20.d[1], x11
347 ; CHECK-NEXT: fcvtzs x11, s22
348 ; CHECK-NEXT: mov v2.d[1], x13
349 ; CHECK-NEXT: fcvtzs x15, s3
350 ; CHECK-NEXT: fcvtzs x13, s1
351 ; CHECK-NEXT: mov v18.d[1], x14
352 ; CHECK-NEXT: fcvtzs x14, s6
353 ; CHECK-NEXT: stp q0, q24, [x8]
354 ; CHECK-NEXT: mov v17.d[1], x12
355 ; CHECK-NEXT: fcvtzs x12, s5
356 ; CHECK-NEXT: fmov d0, x10
357 ; CHECK-NEXT: fmov d1, x11
358 ; CHECK-NEXT: stp q2, q20, [x8, #224]
359 ; CHECK-NEXT: fmov d2, x9
360 ; CHECK-NEXT: mov v16.d[1], x15
361 ; CHECK-NEXT: stp q17, q18, [x8, #160]
362 ; CHECK-NEXT: mov v0.d[1], x13
363 ; CHECK-NEXT: mov v1.d[1], x14
364 ; CHECK-NEXT: mov v2.d[1], x12
365 ; CHECK-NEXT: stp q0, q16, [x8, #96]
366 ; CHECK-NEXT: stp q2, q1, [x8, #32]
367 ; CHECK-NEXT: ret
368 %a = call <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half> %x)
369 ret <32 x i64> %a
370 }
371 declare <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half>)
373 define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x) {
374 ; CHECK-LABEL: llrint_v1i64_v1f32:
375 ; CHECK: // %bb.0:
376 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
377 ; CHECK-NEXT: frintx s0, s0
378 ; CHECK-NEXT: fcvtzs x8, s0
379 ; CHECK-NEXT: fmov d0, x8
380 ; CHECK-NEXT: ret
381 %a = call <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float> %x)
382 ret <1 x i64> %a
383 }
384 declare <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float>)
386 define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x) {
387 ; CHECK-LABEL: llrint_v2i64_v2f32:
388 ; CHECK: // %bb.0:
389 ; CHECK-NEXT: frintx v0.2s, v0.2s
390 ; CHECK-NEXT: fcvtl v0.2d, v0.2s
391 ; CHECK-NEXT: fcvtzs v0.2d, v0.2d
392 ; CHECK-NEXT: ret
393 %a = call <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float> %x)
394 ret <2 x i64> %a
395 }
396 declare <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float>)
398 define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) {
399 ; CHECK-LABEL: llrint_v4i64_v4f32:
400 ; CHECK: // %bb.0:
401 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
402 ; CHECK-NEXT: frintx v0.2s, v0.2s
403 ; CHECK-NEXT: frintx v1.2s, v1.2s
404 ; CHECK-NEXT: fcvtl v0.2d, v0.2s
405 ; CHECK-NEXT: fcvtl v1.2d, v1.2s
406 ; CHECK-NEXT: fcvtzs v0.2d, v0.2d
407 ; CHECK-NEXT: fcvtzs v1.2d, v1.2d
408 ; CHECK-NEXT: ret
409 %a = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> %x)
410 ret <4 x i64> %a
411 }
412 declare <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float>)
414 define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) {
415 ; CHECK-LABEL: llrint_v8i64_v8f32:
416 ; CHECK: // %bb.0:
417 ; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
418 ; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
419 ; CHECK-NEXT: frintx v0.2s, v0.2s
420 ; CHECK-NEXT: frintx v1.2s, v1.2s
421 ; CHECK-NEXT: frintx v2.2s, v2.2s
422 ; CHECK-NEXT: frintx v3.2s, v3.2s
423 ; CHECK-NEXT: fcvtl v0.2d, v0.2s
424 ; CHECK-NEXT: fcvtl v1.2d, v1.2s
425 ; CHECK-NEXT: fcvtl v4.2d, v2.2s
426 ; CHECK-NEXT: fcvtl v3.2d, v3.2s
427 ; CHECK-NEXT: fcvtzs v0.2d, v0.2d
428 ; CHECK-NEXT: fcvtzs v2.2d, v1.2d
429 ; CHECK-NEXT: fcvtzs v1.2d, v4.2d
430 ; CHECK-NEXT: fcvtzs v3.2d, v3.2d
431 ; CHECK-NEXT: ret
432 %a = call <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float> %x)
433 ret <8 x i64> %a
434 }
435 declare <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float>)
437 define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) {
438 ; CHECK-LABEL: llrint_v16i64_v16f32:
439 ; CHECK: // %bb.0:
440 ; CHECK-NEXT: ext v4.16b, v1.16b, v1.16b, #8
441 ; CHECK-NEXT: ext v5.16b, v0.16b, v0.16b, #8
442 ; CHECK-NEXT: ext v6.16b, v2.16b, v2.16b, #8
443 ; CHECK-NEXT: ext v7.16b, v3.16b, v3.16b, #8
444 ; CHECK-NEXT: frintx v0.2s, v0.2s
445 ; CHECK-NEXT: frintx v1.2s, v1.2s
446 ; CHECK-NEXT: frintx v2.2s, v2.2s
447 ; CHECK-NEXT: frintx v3.2s, v3.2s
448 ; CHECK-NEXT: frintx v5.2s, v5.2s
449 ; CHECK-NEXT: frintx v4.2s, v4.2s
450 ; CHECK-NEXT: frintx v6.2s, v6.2s
451 ; CHECK-NEXT: frintx v7.2s, v7.2s
452 ; CHECK-NEXT: fcvtl v0.2d, v0.2s
453 ; CHECK-NEXT: fcvtl v1.2d, v1.2s
454 ; CHECK-NEXT: fcvtl v16.2d, v2.2s
455 ; CHECK-NEXT: fcvtl v18.2d, v3.2s
456 ; CHECK-NEXT: fcvtl v5.2d, v5.2s
457 ; CHECK-NEXT: fcvtl v17.2d, v4.2s
458 ; CHECK-NEXT: fcvtl v19.2d, v6.2s
459 ; CHECK-NEXT: fcvtl v7.2d, v7.2s
460 ; CHECK-NEXT: fcvtzs v0.2d, v0.2d
461 ; CHECK-NEXT: fcvtzs v2.2d, v1.2d
462 ; CHECK-NEXT: fcvtzs v4.2d, v16.2d
463 ; CHECK-NEXT: fcvtzs v6.2d, v18.2d
464 ; CHECK-NEXT: fcvtzs v1.2d, v5.2d
465 ; CHECK-NEXT: fcvtzs v3.2d, v17.2d
466 ; CHECK-NEXT: fcvtzs v5.2d, v19.2d
467 ; CHECK-NEXT: fcvtzs v7.2d, v7.2d
468 ; CHECK-NEXT: ret
469 %a = call <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float> %x)
470 ret <16 x i64> %a
471 }
472 declare <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float>)
474 define <32 x i64> @llrint_v32i64_v32f32(<32 x float> %x) {
475 ; CHECK-LABEL: llrint_v32i64_v32f32:
476 ; CHECK: // %bb.0:
477 ; CHECK-NEXT: ext v16.16b, v7.16b, v7.16b, #8
478 ; CHECK-NEXT: ext v17.16b, v6.16b, v6.16b, #8
479 ; CHECK-NEXT: frintx v7.2s, v7.2s
480 ; CHECK-NEXT: frintx v6.2s, v6.2s
481 ; CHECK-NEXT: ext v18.16b, v5.16b, v5.16b, #8
482 ; CHECK-NEXT: ext v21.16b, v4.16b, v4.16b, #8
483 ; CHECK-NEXT: ext v22.16b, v2.16b, v2.16b, #8
484 ; CHECK-NEXT: frintx v5.2s, v5.2s
485 ; CHECK-NEXT: ext v23.16b, v3.16b, v3.16b, #8
486 ; CHECK-NEXT: frintx v4.2s, v4.2s
487 ; CHECK-NEXT: ext v19.16b, v0.16b, v0.16b, #8
488 ; CHECK-NEXT: ext v20.16b, v1.16b, v1.16b, #8
489 ; CHECK-NEXT: frintx v16.2s, v16.2s
490 ; CHECK-NEXT: frintx v17.2s, v17.2s
491 ; CHECK-NEXT: fcvtl v7.2d, v7.2s
492 ; CHECK-NEXT: fcvtl v6.2d, v6.2s
493 ; CHECK-NEXT: frintx v18.2s, v18.2s
494 ; CHECK-NEXT: frintx v21.2s, v21.2s
495 ; CHECK-NEXT: frintx v2.2s, v2.2s
496 ; CHECK-NEXT: frintx v3.2s, v3.2s
497 ; CHECK-NEXT: fcvtl v5.2d, v5.2s
498 ; CHECK-NEXT: frintx v23.2s, v23.2s
499 ; CHECK-NEXT: fcvtl v4.2d, v4.2s
500 ; CHECK-NEXT: frintx v1.2s, v1.2s
501 ; CHECK-NEXT: fcvtl v16.2d, v16.2s
502 ; CHECK-NEXT: fcvtl v17.2d, v17.2s
503 ; CHECK-NEXT: fcvtzs v7.2d, v7.2d
504 ; CHECK-NEXT: fcvtzs v6.2d, v6.2d
505 ; CHECK-NEXT: fcvtl v18.2d, v18.2s
506 ; CHECK-NEXT: fcvtl v21.2d, v21.2s
507 ; CHECK-NEXT: frintx v20.2s, v20.2s
508 ; CHECK-NEXT: fcvtl v3.2d, v3.2s
509 ; CHECK-NEXT: fcvtzs v5.2d, v5.2d
510 ; CHECK-NEXT: frintx v0.2s, v0.2s
511 ; CHECK-NEXT: fcvtl v2.2d, v2.2s
512 ; CHECK-NEXT: fcvtzs v4.2d, v4.2d
513 ; CHECK-NEXT: fcvtzs v16.2d, v16.2d
514 ; CHECK-NEXT: fcvtzs v17.2d, v17.2d
515 ; CHECK-NEXT: fcvtl v1.2d, v1.2s
516 ; CHECK-NEXT: fcvtzs v3.2d, v3.2d
517 ; CHECK-NEXT: fcvtl v0.2d, v0.2s
518 ; CHECK-NEXT: fcvtzs v2.2d, v2.2d
519 ; CHECK-NEXT: stp q6, q17, [x8, #192]
520 ; CHECK-NEXT: fcvtl v6.2d, v23.2s
521 ; CHECK-NEXT: frintx v17.2s, v19.2s
522 ; CHECK-NEXT: stp q7, q16, [x8, #224]
523 ; CHECK-NEXT: frintx v7.2s, v22.2s
524 ; CHECK-NEXT: fcvtzs v16.2d, v18.2d
525 ; CHECK-NEXT: fcvtzs v18.2d, v21.2d
526 ; CHECK-NEXT: fcvtzs v1.2d, v1.2d
527 ; CHECK-NEXT: fcvtzs v0.2d, v0.2d
528 ; CHECK-NEXT: fcvtzs v6.2d, v6.2d
529 ; CHECK-NEXT: stp q5, q16, [x8, #160]
530 ; CHECK-NEXT: fcvtl v7.2d, v7.2s
531 ; CHECK-NEXT: fcvtl v5.2d, v20.2s
532 ; CHECK-NEXT: stp q4, q18, [x8, #128]
533 ; CHECK-NEXT: fcvtl v4.2d, v17.2s
534 ; CHECK-NEXT: stp q3, q6, [x8, #96]
535 ; CHECK-NEXT: fcvtzs v7.2d, v7.2d
536 ; CHECK-NEXT: fcvtzs v3.2d, v5.2d
537 ; CHECK-NEXT: stp q1, q3, [x8, #32]
538 ; CHECK-NEXT: stp q2, q7, [x8, #64]
539 ; CHECK-NEXT: fcvtzs v2.2d, v4.2d
540 ; CHECK-NEXT: stp q0, q2, [x8]
541 ; CHECK-NEXT: ret
542 %a = call <32 x i64> @llvm.llrint.v32i64.v32f32(<32 x float> %x)
543 ret <32 x i64> %a
544 }
545 declare <32 x i64> @llvm.llrint.v32i64.v32f32(<32 x float>)
547 define <1 x i64> @llrint_v1i64_v1f64(<1 x double> %x) {
548 ; CHECK-LABEL: llrint_v1i64_v1f64:
549 ; CHECK: // %bb.0:
550 ; CHECK-NEXT: frintx d0, d0
551 ; CHECK-NEXT: fcvtzs x8, d0
552 ; CHECK-NEXT: fmov d0, x8
553 ; CHECK-NEXT: ret
554 %a = call <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double> %x)
555 ret <1 x i64> %a
556 }
557 declare <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double>)
559 define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x) {
560 ; CHECK-LABEL: llrint_v2i64_v2f64:
561 ; CHECK: // %bb.0:
562 ; CHECK-NEXT: frintx v0.2d, v0.2d
563 ; CHECK-NEXT: fcvtzs v0.2d, v0.2d
564 ; CHECK-NEXT: ret
565 %a = call <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double> %x)
566 ret <2 x i64> %a
567 }
568 declare <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double>)
570 define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) {
571 ; CHECK-LABEL: llrint_v4i64_v4f64:
572 ; CHECK: // %bb.0:
573 ; CHECK-NEXT: frintx v0.2d, v0.2d
574 ; CHECK-NEXT: frintx v1.2d, v1.2d
575 ; CHECK-NEXT: fcvtzs v0.2d, v0.2d
576 ; CHECK-NEXT: fcvtzs v1.2d, v1.2d
577 ; CHECK-NEXT: ret
578 %a = call <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double> %x)
579 ret <4 x i64> %a
580 }
581 declare <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double>)
583 define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) {
584 ; CHECK-LABEL: llrint_v8i64_v8f64:
585 ; CHECK: // %bb.0:
586 ; CHECK-NEXT: frintx v0.2d, v0.2d
587 ; CHECK-NEXT: frintx v1.2d, v1.2d
588 ; CHECK-NEXT: frintx v2.2d, v2.2d
589 ; CHECK-NEXT: frintx v3.2d, v3.2d
590 ; CHECK-NEXT: fcvtzs v0.2d, v0.2d
591 ; CHECK-NEXT: fcvtzs v1.2d, v1.2d
592 ; CHECK-NEXT: fcvtzs v2.2d, v2.2d
593 ; CHECK-NEXT: fcvtzs v3.2d, v3.2d
594 ; CHECK-NEXT: ret
595 %a = call <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double> %x)
596 ret <8 x i64> %a
597 }
598 declare <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double>)
600 define <16 x i64> @llrint_v16f64(<16 x double> %x) {
601 ; CHECK-LABEL: llrint_v16f64:
602 ; CHECK: // %bb.0:
603 ; CHECK-NEXT: frintx v0.2d, v0.2d
604 ; CHECK-NEXT: frintx v1.2d, v1.2d
605 ; CHECK-NEXT: frintx v2.2d, v2.2d
606 ; CHECK-NEXT: frintx v3.2d, v3.2d
607 ; CHECK-NEXT: frintx v4.2d, v4.2d
608 ; CHECK-NEXT: frintx v5.2d, v5.2d
609 ; CHECK-NEXT: frintx v6.2d, v6.2d
610 ; CHECK-NEXT: frintx v7.2d, v7.2d
611 ; CHECK-NEXT: fcvtzs v0.2d, v0.2d
612 ; CHECK-NEXT: fcvtzs v1.2d, v1.2d
613 ; CHECK-NEXT: fcvtzs v2.2d, v2.2d
614 ; CHECK-NEXT: fcvtzs v3.2d, v3.2d
615 ; CHECK-NEXT: fcvtzs v4.2d, v4.2d
616 ; CHECK-NEXT: fcvtzs v5.2d, v5.2d
617 ; CHECK-NEXT: fcvtzs v6.2d, v6.2d
618 ; CHECK-NEXT: fcvtzs v7.2d, v7.2d
619 ; CHECK-NEXT: ret
620 %a = call <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double> %x)
621 ret <16 x i64> %a
622 }
623 declare <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double>)
625 define <32 x i64> @llrint_v32f64(<32 x double> %x) {
626 ; CHECK-LABEL: llrint_v32f64:
627 ; CHECK: // %bb.0:
628 ; CHECK-NEXT: ldp q17, q16, [sp, #96]
629 ; CHECK-NEXT: frintx v7.2d, v7.2d
630 ; CHECK-NEXT: ldp q19, q18, [sp, #64]
631 ; CHECK-NEXT: frintx v6.2d, v6.2d
632 ; CHECK-NEXT: ldp q21, q20, [sp, #32]
633 ; CHECK-NEXT: frintx v5.2d, v5.2d
634 ; CHECK-NEXT: frintx v16.2d, v16.2d
635 ; CHECK-NEXT: frintx v17.2d, v17.2d
636 ; CHECK-NEXT: frintx v4.2d, v4.2d
637 ; CHECK-NEXT: frintx v18.2d, v18.2d
638 ; CHECK-NEXT: frintx v19.2d, v19.2d
639 ; CHECK-NEXT: frintx v3.2d, v3.2d
640 ; CHECK-NEXT: ldp q23, q22, [sp]
641 ; CHECK-NEXT: frintx v20.2d, v20.2d
642 ; CHECK-NEXT: frintx v21.2d, v21.2d
643 ; CHECK-NEXT: frintx v2.2d, v2.2d
644 ; CHECK-NEXT: frintx v1.2d, v1.2d
645 ; CHECK-NEXT: fcvtzs v16.2d, v16.2d
646 ; CHECK-NEXT: fcvtzs v17.2d, v17.2d
647 ; CHECK-NEXT: frintx v0.2d, v0.2d
648 ; CHECK-NEXT: frintx v22.2d, v22.2d
649 ; CHECK-NEXT: fcvtzs v18.2d, v18.2d
650 ; CHECK-NEXT: frintx v23.2d, v23.2d
651 ; CHECK-NEXT: fcvtzs v19.2d, v19.2d
652 ; CHECK-NEXT: fcvtzs v20.2d, v20.2d
653 ; CHECK-NEXT: fcvtzs v7.2d, v7.2d
654 ; CHECK-NEXT: fcvtzs v6.2d, v6.2d
655 ; CHECK-NEXT: fcvtzs v5.2d, v5.2d
656 ; CHECK-NEXT: fcvtzs v4.2d, v4.2d
657 ; CHECK-NEXT: stp q17, q16, [x8, #224]
658 ; CHECK-NEXT: fcvtzs v16.2d, v21.2d
659 ; CHECK-NEXT: fcvtzs v3.2d, v3.2d
660 ; CHECK-NEXT: fcvtzs v17.2d, v22.2d
661 ; CHECK-NEXT: fcvtzs v2.2d, v2.2d
662 ; CHECK-NEXT: fcvtzs v1.2d, v1.2d
663 ; CHECK-NEXT: stp q19, q18, [x8, #192]
664 ; CHECK-NEXT: fcvtzs v18.2d, v23.2d
665 ; CHECK-NEXT: fcvtzs v0.2d, v0.2d
666 ; CHECK-NEXT: stp q4, q5, [x8, #64]
667 ; CHECK-NEXT: stp q6, q7, [x8, #96]
668 ; CHECK-NEXT: stp q2, q3, [x8, #32]
669 ; CHECK-NEXT: stp q0, q1, [x8]
670 ; CHECK-NEXT: stp q18, q17, [x8, #128]
671 ; CHECK-NEXT: stp q16, q20, [x8, #160]
672 ; CHECK-NEXT: ret
673 %a = call <32 x i64> @llvm.llrint.v32i64.v16f64(<32 x double> %x)
674 ret <32 x i64> %a
675 }
676 declare <32 x i64> @llvm.llrint.v32i64.v32f64(<32 x double>)