1 ; RUN: opt -march=hexagon -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
2 ; Check that the loop has been interleaved.
3 ; CHECK: store <64 x i32> %interleaved.vec
5 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
6 target triple = "hexagon"
8 define void @f0(ptr noalias nocapture %a0, ptr noalias nocapture readonly %a1, i32 %a2) #0 {
10 %v0 = icmp eq i32 %a2, 0
11 br i1 %v0, label %b3, label %b1
19 b3: ; preds = %b2, %b0
22 b4: ; preds = %b4, %b1
23 %v1 = phi i32 [ %v13, %b4 ], [ 0, %b1 ]
24 %v2 = getelementptr inbounds i32, ptr %a1, i32 %v1
25 %v3 = load i32, ptr %v2, align 4, !tbaa !1
26 %v4 = getelementptr inbounds i32, ptr %a0, i32 %v1
27 %v5 = load i32, ptr %v4, align 4, !tbaa !1
28 %v6 = add nsw i32 %v5, %v3
29 store i32 %v6, ptr %v4, align 4, !tbaa !1
30 %v7 = or disjoint i32 %v1, 1
31 %v8 = getelementptr inbounds i32, ptr %a1, i32 %v7
32 %v9 = load i32, ptr %v8, align 4, !tbaa !1
33 %v10 = getelementptr inbounds i32, ptr %a0, i32 %v7
34 %v11 = load i32, ptr %v10, align 4, !tbaa !1
35 %v12 = add nsw i32 %v11, %v9
36 store i32 %v12, ptr %v10, align 4, !tbaa !1
37 %v13 = add nuw nsw i32 %v1, 2
38 %v14 = icmp eq i32 %v13, %a2
39 br i1 %v14, label %b2, label %b4, !llvm.loop !5
42 attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length128b,+hvxv60" }
44 !llvm.module.flags = !{!0}
46 !0 = !{i32 1, !"wchar_size", i32 4}
48 !2 = !{!"int", !3, i64 0}
49 !3 = !{!"omnipotent char", !4, i64 0}
50 !4 = !{!"Simple C/C++ TBAA"}
51 !5 = distinct !{!5, !6}
52 !6 = !{!"llvm.loop.unroll.disable"}