1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hexagon-misched < %s \
3 ; Check that we generate new value jump, both registers, with one
4 ; of the registers as new.
6 @Reg = common global i32 0, align 4
7 define i32 @main() nounwind {
9 ; CHECK: if (cmp.gt(r{{[0-9]+}}.new,r{{[0-9]+}})) jump:{{[t|nt]}} .LBB{{[0-9]+}}_{{[0-9]+}}
10 %Reg2 = alloca i32, align 4
11 %0 = load i32, ptr %Reg2, align 4
12 %1 = load i32, ptr @Reg, align 4
13 %tobool = icmp sle i32 %0, %1
14 br i1 %tobool, label %if.then, label %if.else
17 call void @bar(i32 1, i32 2)
21 call void @baz(i32 10, i32 20)
28 declare void @bar(i32, i32)
29 declare void @baz(i32, i32)