| blob | e1d5c8c0af4c53393576feab9e9b6a76156dac42 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=mips-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=MIPSEL
3 ; RUN: llc -mtriple=mips64el-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=MIPS64EL
5 define i1 @test_urem_odd(i13 %X) nounwind {
6 ; MIPSEL-LABEL: test_urem_odd:
7 ; MIPSEL: # %bb.0:
8 ; MIPSEL-NEXT: addiu $1, $zero, 3277
9 ; MIPSEL-NEXT: mul $1, $4, $1
10 ; MIPSEL-NEXT: andi $1, $1, 8191
11 ; MIPSEL-NEXT: jr $ra
12 ; MIPSEL-NEXT: sltiu $2, $1, 1639
13 ;
14 ; MIPS64EL-LABEL: test_urem_odd:
15 ; MIPS64EL: # %bb.0:
16 ; MIPS64EL-NEXT: sll $1, $4, 0
17 ; MIPS64EL-NEXT: sll $2, $1, 1
18 ; MIPS64EL-NEXT: addu $2, $2, $1
19 ; MIPS64EL-NEXT: sll $3, $1, 4
20 ; MIPS64EL-NEXT: subu $2, $3, $2
21 ; MIPS64EL-NEXT: sll $3, $1, 6
22 ; MIPS64EL-NEXT: subu $2, $2, $3
23 ; MIPS64EL-NEXT: sll $3, $1, 8
24 ; MIPS64EL-NEXT: addu $2, $3, $2
25 ; MIPS64EL-NEXT: sll $3, $1, 10
26 ; MIPS64EL-NEXT: subu $2, $2, $3
27 ; MIPS64EL-NEXT: sll $1, $1, 12
28 ; MIPS64EL-NEXT: addu $1, $1, $2
29 ; MIPS64EL-NEXT: andi $1, $1, 8191
30 ; MIPS64EL-NEXT: jr $ra
31 ; MIPS64EL-NEXT: sltiu $2, $1, 1639
32 %urem = urem i13 %X, 5
33 %cmp = icmp eq i13 %urem, 0
34 ret i1 %cmp
35 }
37 define i1 @test_urem_even(i27 %X) nounwind {
38 ; MIPSEL-LABEL: test_urem_even:
39 ; MIPSEL: # %bb.0:
40 ; MIPSEL-NEXT: lui $1, 1755
41 ; MIPSEL-NEXT: ori $1, $1, 28087
42 ; MIPSEL-NEXT: mul $1, $4, $1
43 ; MIPSEL-NEXT: sll $2, $1, 26
44 ; MIPSEL-NEXT: lui $3, 2047
45 ; MIPSEL-NEXT: ori $4, $3, 65534
46 ; MIPSEL-NEXT: and $1, $1, $4
47 ; MIPSEL-NEXT: srl $1, $1, 1
48 ; MIPSEL-NEXT: or $1, $1, $2
49 ; MIPSEL-NEXT: ori $2, $3, 65535
50 ; MIPSEL-NEXT: and $1, $1, $2
51 ; MIPSEL-NEXT: lui $2, 146
52 ; MIPSEL-NEXT: ori $2, $2, 18725
53 ; MIPSEL-NEXT: jr $ra
54 ; MIPSEL-NEXT: sltu $2, $1, $2
55 ;
56 ; MIPS64EL-LABEL: test_urem_even:
57 ; MIPS64EL: # %bb.0:
58 ; MIPS64EL-NEXT: lui $1, 1755
59 ; MIPS64EL-NEXT: ori $1, $1, 28087
60 ; MIPS64EL-NEXT: sll $2, $4, 0
61 ; MIPS64EL-NEXT: mul $1, $2, $1
62 ; MIPS64EL-NEXT: sll $2, $1, 26
63 ; MIPS64EL-NEXT: lui $3, 2047
64 ; MIPS64EL-NEXT: ori $4, $3, 65534
65 ; MIPS64EL-NEXT: and $1, $1, $4
66 ; MIPS64EL-NEXT: srl $1, $1, 1
67 ; MIPS64EL-NEXT: or $1, $1, $2
68 ; MIPS64EL-NEXT: ori $2, $3, 65535
69 ; MIPS64EL-NEXT: lui $3, 146
70 ; MIPS64EL-NEXT: and $1, $1, $2
71 ; MIPS64EL-NEXT: ori $2, $3, 18725
72 ; MIPS64EL-NEXT: jr $ra
73 ; MIPS64EL-NEXT: sltu $2, $1, $2
74 %urem = urem i27 %X, 14
75 %cmp = icmp eq i27 %urem, 0
76 ret i1 %cmp
77 }
79 define i1 @test_urem_odd_setne(i4 %X) nounwind {
80 ; MIPSEL-LABEL: test_urem_odd_setne:
81 ; MIPSEL: # %bb.0:
82 ; MIPSEL-NEXT: sll $1, $4, 1
83 ; MIPSEL-NEXT: addu $1, $1, $4
84 ; MIPSEL-NEXT: negu $1, $1
85 ; MIPSEL-NEXT: andi $1, $1, 15
86 ; MIPSEL-NEXT: addiu $2, $zero, 3
87 ; MIPSEL-NEXT: jr $ra
88 ; MIPSEL-NEXT: sltu $2, $2, $1
89 ;
90 ; MIPS64EL-LABEL: test_urem_odd_setne:
91 ; MIPS64EL: # %bb.0:
92 ; MIPS64EL-NEXT: sll $1, $4, 0
93 ; MIPS64EL-NEXT: sll $2, $1, 1
94 ; MIPS64EL-NEXT: addu $1, $2, $1
95 ; MIPS64EL-NEXT: negu $1, $1
96 ; MIPS64EL-NEXT: andi $1, $1, 15
97 ; MIPS64EL-NEXT: addiu $2, $zero, 3
98 ; MIPS64EL-NEXT: jr $ra
99 ; MIPS64EL-NEXT: sltu $2, $2, $1
100 %urem = urem i4 %X, 5
101 %cmp = icmp ne i4 %urem, 0
102 ret i1 %cmp
103 }
105 define i1 @test_urem_negative_odd(i9 %X) nounwind {
106 ; MIPSEL-LABEL: test_urem_negative_odd:
107 ; MIPSEL: # %bb.0:
108 ; MIPSEL-NEXT: sll $1, $4, 1
109 ; MIPSEL-NEXT: addu $1, $1, $4
110 ; MIPSEL-NEXT: sll $2, $4, 4
111 ; MIPSEL-NEXT: subu $1, $1, $2
112 ; MIPSEL-NEXT: sll $2, $4, 6
113 ; MIPSEL-NEXT: addu $1, $2, $1
114 ; MIPSEL-NEXT: sll $2, $4, 8
115 ; MIPSEL-NEXT: addu $1, $2, $1
116 ; MIPSEL-NEXT: andi $1, $1, 511
117 ; MIPSEL-NEXT: addiu $2, $zero, 1
118 ; MIPSEL-NEXT: jr $ra
119 ; MIPSEL-NEXT: sltu $2, $2, $1
120 ;
121 ; MIPS64EL-LABEL: test_urem_negative_odd:
122 ; MIPS64EL: # %bb.0:
123 ; MIPS64EL-NEXT: sll $1, $4, 0
124 ; MIPS64EL-NEXT: sll $2, $1, 1
125 ; MIPS64EL-NEXT: addu $2, $2, $1
126 ; MIPS64EL-NEXT: sll $3, $1, 4
127 ; MIPS64EL-NEXT: subu $2, $2, $3
128 ; MIPS64EL-NEXT: sll $3, $1, 6
129 ; MIPS64EL-NEXT: addu $2, $3, $2
130 ; MIPS64EL-NEXT: sll $1, $1, 8
131 ; MIPS64EL-NEXT: addiu $3, $zero, 1
132 ; MIPS64EL-NEXT: addu $1, $1, $2
133 ; MIPS64EL-NEXT: andi $1, $1, 511
134 ; MIPS64EL-NEXT: jr $ra
135 ; MIPS64EL-NEXT: sltu $2, $3, $1
136 %urem = urem i9 %X, -5
137 %cmp = icmp ne i9 %urem, 0
138 ret i1 %cmp
139 }
141 ; Asserts today
142 ; define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind {
143 ; %urem = urem <3 x i11> %X, <i11 6, i11 7, i11 -5>
144 ; %cmp = icmp ne <3 x i11> %urem, <i11 0, i11 1, i11 2>
145 ; ret <3 x i1> %cmp
146 ; }
148 define i1 @test_urem_oversized(i66 %X) nounwind {
149 ; MIPSEL-LABEL: test_urem_oversized:
150 ; MIPSEL: # %bb.0:
151 ; MIPSEL-NEXT: lui $1, 52741
152 ; MIPSEL-NEXT: ori $1, $1, 40665
153 ; MIPSEL-NEXT: multu $6, $1
154 ; MIPSEL-NEXT: mfhi $2
155 ; MIPSEL-NEXT: mflo $3
156 ; MIPSEL-NEXT: multu $5, $1
157 ; MIPSEL-NEXT: mfhi $7
158 ; MIPSEL-NEXT: mflo $8
159 ; MIPSEL-NEXT: lui $9, 12057
160 ; MIPSEL-NEXT: ori $9, $9, 37186
161 ; MIPSEL-NEXT: multu $6, $9
162 ; MIPSEL-NEXT: mflo $10
163 ; MIPSEL-NEXT: mfhi $11
164 ; MIPSEL-NEXT: addu $2, $8, $2
165 ; MIPSEL-NEXT: addu $12, $10, $2
166 ; MIPSEL-NEXT: sltu $2, $2, $8
167 ; MIPSEL-NEXT: addu $2, $7, $2
168 ; MIPSEL-NEXT: sltu $7, $12, $10
169 ; MIPSEL-NEXT: sll $8, $12, 31
170 ; MIPSEL-NEXT: srl $10, $12, 1
171 ; MIPSEL-NEXT: sll $12, $3, 1
172 ; MIPSEL-NEXT: srl $3, $3, 1
173 ; MIPSEL-NEXT: mul $1, $4, $1
174 ; MIPSEL-NEXT: mul $4, $5, $9
175 ; MIPSEL-NEXT: sll $5, $6, 1
176 ; MIPSEL-NEXT: lui $6, 60010
177 ; MIPSEL-NEXT: addu $7, $11, $7
178 ; MIPSEL-NEXT: addu $2, $2, $7
179 ; MIPSEL-NEXT: addu $2, $4, $2
180 ; MIPSEL-NEXT: addu $1, $5, $1
181 ; MIPSEL-NEXT: addu $1, $2, $1
182 ; MIPSEL-NEXT: sll $2, $1, 31
183 ; MIPSEL-NEXT: or $4, $10, $2
184 ; MIPSEL-NEXT: sltiu $2, $4, 13
185 ; MIPSEL-NEXT: xori $4, $4, 13
186 ; MIPSEL-NEXT: or $3, $3, $8
187 ; MIPSEL-NEXT: ori $5, $6, 61135
188 ; MIPSEL-NEXT: sltu $3, $3, $5
189 ; MIPSEL-NEXT: movz $2, $3, $4
190 ; MIPSEL-NEXT: andi $1, $1, 2
191 ; MIPSEL-NEXT: srl $1, $1, 1
192 ; MIPSEL-NEXT: or $1, $1, $12
193 ; MIPSEL-NEXT: andi $1, $1, 3
194 ; MIPSEL-NEXT: jr $ra
195 ; MIPSEL-NEXT: movn $2, $zero, $1
196 ;
197 ; MIPS64EL-LABEL: test_urem_oversized:
198 ; MIPS64EL: # %bb.0:
199 ; MIPS64EL-NEXT: lui $1, 6029
200 ; MIPS64EL-NEXT: daddiu $1, $1, -14175
201 ; MIPS64EL-NEXT: dsll $1, $1, 16
202 ; MIPS64EL-NEXT: daddiu $1, $1, 26371
203 ; MIPS64EL-NEXT: dsll $1, $1, 17
204 ; MIPS64EL-NEXT: daddiu $1, $1, -24871
205 ; MIPS64EL-NEXT: dmult $5, $1
206 ; MIPS64EL-NEXT: mflo $2
207 ; MIPS64EL-NEXT: dmultu $4, $1
208 ; MIPS64EL-NEXT: mflo $1
209 ; MIPS64EL-NEXT: mfhi $3
210 ; MIPS64EL-NEXT: lui $5, 14
211 ; MIPS64EL-NEXT: daddiu $5, $5, -5525
212 ; MIPS64EL-NEXT: dsll $5, $5, 16
213 ; MIPS64EL-NEXT: daddiu $5, $5, -4401
214 ; MIPS64EL-NEXT: dsll $4, $4, 1
215 ; MIPS64EL-NEXT: daddu $3, $3, $4
216 ; MIPS64EL-NEXT: daddu $3, $3, $2
217 ; MIPS64EL-NEXT: dsll $2, $3, 63
218 ; MIPS64EL-NEXT: dsrl $4, $1, 1
219 ; MIPS64EL-NEXT: or $2, $4, $2
220 ; MIPS64EL-NEXT: sltu $2, $2, $5
221 ; MIPS64EL-NEXT: andi $3, $3, 2
222 ; MIPS64EL-NEXT: dsrl $3, $3, 1
223 ; MIPS64EL-NEXT: dsll $1, $1, 1
224 ; MIPS64EL-NEXT: or $1, $3, $1
225 ; MIPS64EL-NEXT: andi $1, $1, 3
226 ; MIPS64EL-NEXT: jr $ra
227 ; MIPS64EL-NEXT: movn $2, $zero, $1
228 %urem = urem i66 %X, 1234567890
229 %cmp = icmp eq i66 %urem, 0
230 ret i1 %cmp
231 }