| blob | 4992ae287b5a6914a52f8f306e8574734608f556 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
3 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
4 ; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr8 -vec-extabi < %s | FileCheck %s
6 define zeroext i32 @ReverseBits(i32 zeroext %n) {
7 ; CHECK-LABEL: ReverseBits:
8 ; CHECK: # %bb.0: # %entry
9 ; CHECK-NEXT: lis 4, -21846
10 ; CHECK-NEXT: slwi 5, 3, 1
11 ; CHECK-NEXT: srwi 3, 3, 1
12 ; CHECK-NEXT: ori 4, 4, 43690
13 ; CHECK-NEXT: and 4, 5, 4
14 ; CHECK-NEXT: lis 5, 21845
15 ; CHECK-NEXT: ori 5, 5, 21845
16 ; CHECK-NEXT: and 3, 3, 5
17 ; CHECK-NEXT: lis 5, -13108
18 ; CHECK-NEXT: or 3, 3, 4
19 ; CHECK-NEXT: ori 5, 5, 52428
20 ; CHECK-NEXT: slwi 4, 3, 2
21 ; CHECK-NEXT: srwi 3, 3, 2
22 ; CHECK-NEXT: and 4, 4, 5
23 ; CHECK-NEXT: lis 5, 13107
24 ; CHECK-NEXT: ori 5, 5, 13107
25 ; CHECK-NEXT: and 3, 3, 5
26 ; CHECK-NEXT: lis 5, -3856
27 ; CHECK-NEXT: or 3, 3, 4
28 ; CHECK-NEXT: ori 5, 5, 61680
29 ; CHECK-NEXT: slwi 4, 3, 4
30 ; CHECK-NEXT: srwi 3, 3, 4
31 ; CHECK-NEXT: and 4, 4, 5
32 ; CHECK-NEXT: lis 5, 3855
33 ; CHECK-NEXT: ori 5, 5, 3855
34 ; CHECK-NEXT: and 3, 3, 5
35 ; CHECK-NEXT: or 3, 3, 4
36 ; CHECK-NEXT: rotlwi 4, 3, 24
37 ; CHECK-NEXT: rlwimi 4, 3, 8, 8, 15
38 ; CHECK-NEXT: rlwimi 4, 3, 8, 24, 31
39 ; CHECK-NEXT: rldicl 3, 4, 0, 32
40 ; CHECK-NEXT: clrldi 3, 3, 32
41 ; CHECK-NEXT: blr
42 entry:
43 %shr = lshr i32 %n, 1
44 %and = and i32 %shr, 1431655765
45 %and1 = shl i32 %n, 1
46 %shl = and i32 %and1, -1431655766
47 %or = or i32 %and, %shl
48 %shr2 = lshr i32 %or, 2
49 %and3 = and i32 %shr2, 858993459
50 %and4 = shl i32 %or, 2
51 %shl5 = and i32 %and4, -858993460
52 %or6 = or i32 %and3, %shl5
53 %shr7 = lshr i32 %or6, 4
54 %and8 = and i32 %shr7, 252645135
55 %and9 = shl i32 %or6, 4
56 %shl10 = and i32 %and9, -252645136
57 %or11 = or i32 %and8, %shl10
58 %shr13 = lshr i32 %or11, 24
59 %and14 = lshr i32 %or11, 8
60 %shr15 = and i32 %and14, 65280
61 %and17 = shl i32 %or11, 8
62 %shl18 = and i32 %and17, 16711680
63 %shl21 = shl i32 %or11, 24
64 %or16 = or i32 %shl21, %shr13
65 %or19 = or i32 %or16, %shr15
66 %or22 = or i32 %or19, %shl18
67 ret i32 %or22
68 }
70 define i64 @ReverseBits64(i64 %n) {
71 ; CHECK-LABEL: ReverseBits64:
72 ; CHECK: # %bb.0: # %entry
73 ; CHECK-NEXT: lis 4, -21846
74 ; CHECK-NEXT: sldi 5, 3, 1
75 ; CHECK-NEXT: rldicl 3, 3, 63, 1
76 ; CHECK-NEXT: ori 4, 4, 43690
77 ; CHECK-NEXT: sldi 4, 4, 32
78 ; CHECK-NEXT: oris 4, 4, 43690
79 ; CHECK-NEXT: ori 4, 4, 43690
80 ; CHECK-NEXT: and 4, 5, 4
81 ; CHECK-NEXT: lis 5, 21845
82 ; CHECK-NEXT: ori 5, 5, 21845
83 ; CHECK-NEXT: sldi 5, 5, 32
84 ; CHECK-NEXT: oris 5, 5, 21845
85 ; CHECK-NEXT: ori 5, 5, 21845
86 ; CHECK-NEXT: and 3, 3, 5
87 ; CHECK-NEXT: lis 5, -13108
88 ; CHECK-NEXT: ori 5, 5, 52428
89 ; CHECK-NEXT: or 3, 3, 4
90 ; CHECK-NEXT: sldi 5, 5, 32
91 ; CHECK-NEXT: sldi 4, 3, 2
92 ; CHECK-NEXT: rldicl 3, 3, 62, 2
93 ; CHECK-NEXT: oris 5, 5, 52428
94 ; CHECK-NEXT: ori 5, 5, 52428
95 ; CHECK-NEXT: and 4, 4, 5
96 ; CHECK-NEXT: lis 5, 13107
97 ; CHECK-NEXT: ori 5, 5, 13107
98 ; CHECK-NEXT: sldi 5, 5, 32
99 ; CHECK-NEXT: oris 5, 5, 13107
100 ; CHECK-NEXT: ori 5, 5, 13107
101 ; CHECK-NEXT: and 3, 3, 5
102 ; CHECK-NEXT: lis 5, -3856
103 ; CHECK-NEXT: ori 5, 5, 61680
104 ; CHECK-NEXT: or 3, 3, 4
105 ; CHECK-NEXT: sldi 5, 5, 32
106 ; CHECK-NEXT: sldi 4, 3, 4
107 ; CHECK-NEXT: rldicl 3, 3, 60, 4
108 ; CHECK-NEXT: oris 5, 5, 61680
109 ; CHECK-NEXT: ori 5, 5, 61680
110 ; CHECK-NEXT: and 4, 4, 5
111 ; CHECK-NEXT: lis 5, 3855
112 ; CHECK-NEXT: ori 5, 5, 3855
113 ; CHECK-NEXT: sldi 5, 5, 32
114 ; CHECK-NEXT: oris 5, 5, 3855
115 ; CHECK-NEXT: ori 5, 5, 3855
116 ; CHECK-NEXT: and 3, 3, 5
117 ; CHECK-NEXT: or 3, 3, 4
118 ; CHECK-NEXT: rldicl 4, 3, 32, 32
119 ; CHECK-NEXT: rotlwi 5, 4, 24
120 ; CHECK-NEXT: rlwimi 5, 4, 8, 8, 15
121 ; CHECK-NEXT: rlwimi 5, 4, 8, 24, 31
122 ; CHECK-NEXT: rotlwi 4, 3, 24
123 ; CHECK-NEXT: rlwimi 4, 3, 8, 8, 15
124 ; CHECK-NEXT: rlwimi 4, 3, 8, 24, 31
125 ; CHECK-NEXT: sldi 3, 4, 32
126 ; CHECK-NEXT: or 3, 3, 5
127 ; CHECK-NEXT: blr
128 entry:
129 %shr = lshr i64 %n, 1
130 %and = and i64 %shr, 6148914691236517205
131 %and1 = shl i64 %n, 1
132 %shl = and i64 %and1, -6148914691236517206
133 %or = or i64 %and, %shl
134 %shr2 = lshr i64 %or, 2
135 %and3 = and i64 %shr2, 3689348814741910323
136 %and4 = shl i64 %or, 2
137 %shl5 = and i64 %and4, -3689348814741910324
138 %or6 = or i64 %and3, %shl5
139 %shr7 = lshr i64 %or6, 4
140 %and8 = and i64 %shr7, 1085102592571150095
141 %and9 = shl i64 %or6, 4
142 %shl10 = and i64 %and9, -1085102592571150096
143 %or11 = or i64 %and8, %shl10
144 %shr13 = lshr i64 %or11, 56
145 %and14 = lshr i64 %or11, 40
146 %shr15 = and i64 %and14, 65280
147 %and17 = lshr i64 %or11, 24
148 %shr18 = and i64 %and17, 16711680
149 %and20 = lshr i64 %or11, 8
150 %shr21 = and i64 %and20, 4278190080
151 %and23 = shl i64 %or11, 8
152 %shl24 = and i64 %and23, 1095216660480
153 %and26 = shl i64 %or11, 24
154 %shl27 = and i64 %and26, 280375465082880
155 %and29 = shl i64 %or11, 40
156 %shl30 = and i64 %and29, 71776119061217280
157 %shl33 = shl i64 %or11, 56
158 %or16 = or i64 %shl33, %shr13
159 %or19 = or i64 %or16, %shr15
160 %or22 = or i64 %or19, %shr18
161 %or25 = or i64 %or22, %shr21
162 %or28 = or i64 %or25, %shl24
163 %or31 = or i64 %or28, %shl27
164 %or34 = or i64 %or31, %shl30
165 ret i64 %or34
166 }