1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ;; Test that (mul (add x, c1), c2) can be transformed to
3 ;; (add (mul x, c2), c1*c2) if profitable.
5 ; RUN: llc -mtriple=riscv32 -mattr=+m,+zba -verify-machineinstrs < %s \
6 ; RUN: | FileCheck -check-prefix=RV32IMB %s
7 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zba -verify-machineinstrs < %s \
8 ; RUN: | FileCheck -check-prefix=RV64IMB %s
10 define i32 @add_mul_combine_accept_a1(i32 %x) {
11 ; RV32IMB-LABEL: add_mul_combine_accept_a1:
13 ; RV32IMB-NEXT: sh1add a1, a0, a0
14 ; RV32IMB-NEXT: slli a0, a0, 5
15 ; RV32IMB-NEXT: sub a0, a0, a1
16 ; RV32IMB-NEXT: addi a0, a0, 1073
19 ; RV64IMB-LABEL: add_mul_combine_accept_a1:
21 ; RV64IMB-NEXT: sh1add a1, a0, a0
22 ; RV64IMB-NEXT: slli a0, a0, 5
23 ; RV64IMB-NEXT: subw a0, a0, a1
24 ; RV64IMB-NEXT: addiw a0, a0, 1073
26 %tmp0 = add i32 %x, 37
27 %tmp1 = mul i32 %tmp0, 29
31 define signext i32 @add_mul_combine_accept_a2(i32 signext %x) {
32 ; RV32IMB-LABEL: add_mul_combine_accept_a2:
34 ; RV32IMB-NEXT: sh1add a1, a0, a0
35 ; RV32IMB-NEXT: slli a0, a0, 5
36 ; RV32IMB-NEXT: sub a0, a0, a1
37 ; RV32IMB-NEXT: addi a0, a0, 1073
40 ; RV64IMB-LABEL: add_mul_combine_accept_a2:
42 ; RV64IMB-NEXT: sh1add a1, a0, a0
43 ; RV64IMB-NEXT: slli a0, a0, 5
44 ; RV64IMB-NEXT: subw a0, a0, a1
45 ; RV64IMB-NEXT: addiw a0, a0, 1073
47 %tmp0 = add i32 %x, 37
48 %tmp1 = mul i32 %tmp0, 29
52 define i64 @add_mul_combine_accept_a3(i64 %x) {
53 ; RV32IMB-LABEL: add_mul_combine_accept_a3:
55 ; RV32IMB-NEXT: li a2, 29
56 ; RV32IMB-NEXT: mulhu a2, a0, a2
57 ; RV32IMB-NEXT: sh1add a3, a1, a1
58 ; RV32IMB-NEXT: slli a1, a1, 5
59 ; RV32IMB-NEXT: sub a1, a1, a3
60 ; RV32IMB-NEXT: add a1, a2, a1
61 ; RV32IMB-NEXT: sh1add a2, a0, a0
62 ; RV32IMB-NEXT: slli a0, a0, 5
63 ; RV32IMB-NEXT: sub a2, a0, a2
64 ; RV32IMB-NEXT: addi a0, a2, 1073
65 ; RV32IMB-NEXT: sltu a2, a0, a2
66 ; RV32IMB-NEXT: add a1, a1, a2
69 ; RV64IMB-LABEL: add_mul_combine_accept_a3:
71 ; RV64IMB-NEXT: sh1add a1, a0, a0
72 ; RV64IMB-NEXT: slli a0, a0, 5
73 ; RV64IMB-NEXT: sub a0, a0, a1
74 ; RV64IMB-NEXT: addi a0, a0, 1073
76 %tmp0 = add i64 %x, 37
77 %tmp1 = mul i64 %tmp0, 29
81 define i32 @add_mul_combine_accept_b1(i32 %x) {
82 ; RV32IMB-LABEL: add_mul_combine_accept_b1:
84 ; RV32IMB-NEXT: sh3add a1, a0, a0
85 ; RV32IMB-NEXT: slli a0, a0, 5
86 ; RV32IMB-NEXT: sub a0, a0, a1
87 ; RV32IMB-NEXT: lui a1, 50
88 ; RV32IMB-NEXT: addi a1, a1, 1119
89 ; RV32IMB-NEXT: add a0, a0, a1
92 ; RV64IMB-LABEL: add_mul_combine_accept_b1:
94 ; RV64IMB-NEXT: sh3add a1, a0, a0
95 ; RV64IMB-NEXT: slli a0, a0, 5
96 ; RV64IMB-NEXT: subw a0, a0, a1
97 ; RV64IMB-NEXT: lui a1, 50
98 ; RV64IMB-NEXT: addi a1, a1, 1119
99 ; RV64IMB-NEXT: addw a0, a0, a1
101 %tmp0 = add i32 %x, 8953
102 %tmp1 = mul i32 %tmp0, 23
106 define signext i32 @add_mul_combine_accept_b2(i32 signext %x) {
107 ; RV32IMB-LABEL: add_mul_combine_accept_b2:
109 ; RV32IMB-NEXT: sh3add a1, a0, a0
110 ; RV32IMB-NEXT: slli a0, a0, 5
111 ; RV32IMB-NEXT: sub a0, a0, a1
112 ; RV32IMB-NEXT: lui a1, 50
113 ; RV32IMB-NEXT: addi a1, a1, 1119
114 ; RV32IMB-NEXT: add a0, a0, a1
117 ; RV64IMB-LABEL: add_mul_combine_accept_b2:
119 ; RV64IMB-NEXT: sh3add a1, a0, a0
120 ; RV64IMB-NEXT: slli a0, a0, 5
121 ; RV64IMB-NEXT: subw a0, a0, a1
122 ; RV64IMB-NEXT: lui a1, 50
123 ; RV64IMB-NEXT: addi a1, a1, 1119
124 ; RV64IMB-NEXT: addw a0, a0, a1
126 %tmp0 = add i32 %x, 8953
127 %tmp1 = mul i32 %tmp0, 23
131 define i64 @add_mul_combine_accept_b3(i64 %x) {
132 ; RV32IMB-LABEL: add_mul_combine_accept_b3:
134 ; RV32IMB-NEXT: li a2, 23
135 ; RV32IMB-NEXT: mulhu a2, a0, a2
136 ; RV32IMB-NEXT: sh3add a3, a1, a1
137 ; RV32IMB-NEXT: slli a1, a1, 5
138 ; RV32IMB-NEXT: sub a1, a1, a3
139 ; RV32IMB-NEXT: add a1, a2, a1
140 ; RV32IMB-NEXT: sh3add a2, a0, a0
141 ; RV32IMB-NEXT: slli a0, a0, 5
142 ; RV32IMB-NEXT: sub a2, a0, a2
143 ; RV32IMB-NEXT: lui a0, 50
144 ; RV32IMB-NEXT: addi a0, a0, 1119
145 ; RV32IMB-NEXT: add a0, a2, a0
146 ; RV32IMB-NEXT: sltu a2, a0, a2
147 ; RV32IMB-NEXT: add a1, a1, a2
150 ; RV64IMB-LABEL: add_mul_combine_accept_b3:
152 ; RV64IMB-NEXT: sh3add a1, a0, a0
153 ; RV64IMB-NEXT: slli a0, a0, 5
154 ; RV64IMB-NEXT: sub a0, a0, a1
155 ; RV64IMB-NEXT: lui a1, 50
156 ; RV64IMB-NEXT: addiw a1, a1, 1119
157 ; RV64IMB-NEXT: add a0, a0, a1
159 %tmp0 = add i64 %x, 8953
160 %tmp1 = mul i64 %tmp0, 23
164 define i32 @add_mul_combine_reject_a1(i32 %x) {
165 ; RV32IMB-LABEL: add_mul_combine_reject_a1:
167 ; RV32IMB-NEXT: addi a0, a0, 1971
168 ; RV32IMB-NEXT: sh1add a1, a0, a0
169 ; RV32IMB-NEXT: slli a0, a0, 5
170 ; RV32IMB-NEXT: sub a0, a0, a1
173 ; RV64IMB-LABEL: add_mul_combine_reject_a1:
175 ; RV64IMB-NEXT: addi a0, a0, 1971
176 ; RV64IMB-NEXT: sh1add a1, a0, a0
177 ; RV64IMB-NEXT: slli a0, a0, 5
178 ; RV64IMB-NEXT: subw a0, a0, a1
180 %tmp0 = add i32 %x, 1971
181 %tmp1 = mul i32 %tmp0, 29
185 define signext i32 @add_mul_combine_reject_a2(i32 signext %x) {
186 ; RV32IMB-LABEL: add_mul_combine_reject_a2:
188 ; RV32IMB-NEXT: addi a0, a0, 1971
189 ; RV32IMB-NEXT: sh1add a1, a0, a0
190 ; RV32IMB-NEXT: slli a0, a0, 5
191 ; RV32IMB-NEXT: sub a0, a0, a1
194 ; RV64IMB-LABEL: add_mul_combine_reject_a2:
196 ; RV64IMB-NEXT: addi a0, a0, 1971
197 ; RV64IMB-NEXT: sh1add a1, a0, a0
198 ; RV64IMB-NEXT: slli a0, a0, 5
199 ; RV64IMB-NEXT: subw a0, a0, a1
201 %tmp0 = add i32 %x, 1971
202 %tmp1 = mul i32 %tmp0, 29
206 define i64 @add_mul_combine_reject_a3(i64 %x) {
207 ; RV32IMB-LABEL: add_mul_combine_reject_a3:
209 ; RV32IMB-NEXT: li a2, 29
210 ; RV32IMB-NEXT: mulhu a2, a0, a2
211 ; RV32IMB-NEXT: sh1add a3, a1, a1
212 ; RV32IMB-NEXT: slli a1, a1, 5
213 ; RV32IMB-NEXT: sub a1, a1, a3
214 ; RV32IMB-NEXT: add a1, a2, a1
215 ; RV32IMB-NEXT: sh1add a2, a0, a0
216 ; RV32IMB-NEXT: slli a0, a0, 5
217 ; RV32IMB-NEXT: sub a2, a0, a2
218 ; RV32IMB-NEXT: lui a0, 14
219 ; RV32IMB-NEXT: addi a0, a0, -185
220 ; RV32IMB-NEXT: add a0, a2, a0
221 ; RV32IMB-NEXT: sltu a2, a0, a2
222 ; RV32IMB-NEXT: add a1, a1, a2
225 ; RV64IMB-LABEL: add_mul_combine_reject_a3:
227 ; RV64IMB-NEXT: addi a0, a0, 1971
228 ; RV64IMB-NEXT: sh1add a1, a0, a0
229 ; RV64IMB-NEXT: slli a0, a0, 5
230 ; RV64IMB-NEXT: sub a0, a0, a1
232 %tmp0 = add i64 %x, 1971
233 %tmp1 = mul i64 %tmp0, 29
237 define i32 @add_mul_combine_reject_c1(i32 %x) {
238 ; RV32IMB-LABEL: add_mul_combine_reject_c1:
240 ; RV32IMB-NEXT: addi a0, a0, 1000
241 ; RV32IMB-NEXT: sh3add a1, a0, a0
242 ; RV32IMB-NEXT: sh3add a0, a1, a0
245 ; RV64IMB-LABEL: add_mul_combine_reject_c1:
247 ; RV64IMB-NEXT: addi a0, a0, 1000
248 ; RV64IMB-NEXT: sh3add a1, a0, a0
249 ; RV64IMB-NEXT: sh3add a0, a1, a0
250 ; RV64IMB-NEXT: sext.w a0, a0
252 %tmp0 = add i32 %x, 1000
253 %tmp1 = mul i32 %tmp0, 73
257 define signext i32 @add_mul_combine_reject_c2(i32 signext %x) {
258 ; RV32IMB-LABEL: add_mul_combine_reject_c2:
260 ; RV32IMB-NEXT: addi a0, a0, 1000
261 ; RV32IMB-NEXT: sh3add a1, a0, a0
262 ; RV32IMB-NEXT: sh3add a0, a1, a0
265 ; RV64IMB-LABEL: add_mul_combine_reject_c2:
267 ; RV64IMB-NEXT: addi a0, a0, 1000
268 ; RV64IMB-NEXT: sh3add a1, a0, a0
269 ; RV64IMB-NEXT: sh3add a0, a1, a0
270 ; RV64IMB-NEXT: sext.w a0, a0
272 %tmp0 = add i32 %x, 1000
273 %tmp1 = mul i32 %tmp0, 73
277 define i64 @add_mul_combine_reject_c3(i64 %x) {
278 ; RV32IMB-LABEL: add_mul_combine_reject_c3:
280 ; RV32IMB-NEXT: li a2, 73
281 ; RV32IMB-NEXT: mulhu a2, a0, a2
282 ; RV32IMB-NEXT: sh3add a3, a1, a1
283 ; RV32IMB-NEXT: sh3add a1, a3, a1
284 ; RV32IMB-NEXT: add a1, a2, a1
285 ; RV32IMB-NEXT: sh3add a2, a0, a0
286 ; RV32IMB-NEXT: sh3add a2, a2, a0
287 ; RV32IMB-NEXT: lui a0, 18
288 ; RV32IMB-NEXT: addi a0, a0, -728
289 ; RV32IMB-NEXT: add a0, a2, a0
290 ; RV32IMB-NEXT: sltu a2, a0, a2
291 ; RV32IMB-NEXT: add a1, a1, a2
294 ; RV64IMB-LABEL: add_mul_combine_reject_c3:
296 ; RV64IMB-NEXT: addi a0, a0, 1000
297 ; RV64IMB-NEXT: sh3add a1, a0, a0
298 ; RV64IMB-NEXT: sh3add a0, a1, a0
300 %tmp0 = add i64 %x, 1000
301 %tmp1 = mul i64 %tmp0, 73
305 define i32 @add_mul_combine_reject_d1(i32 %x) {
306 ; RV32IMB-LABEL: add_mul_combine_reject_d1:
308 ; RV32IMB-NEXT: addi a0, a0, 1000
309 ; RV32IMB-NEXT: sh1add a0, a0, a0
310 ; RV32IMB-NEXT: slli a0, a0, 6
313 ; RV64IMB-LABEL: add_mul_combine_reject_d1:
315 ; RV64IMB-NEXT: addi a0, a0, 1000
316 ; RV64IMB-NEXT: sh1add a0, a0, a0
317 ; RV64IMB-NEXT: slliw a0, a0, 6
319 %tmp0 = add i32 %x, 1000
320 %tmp1 = mul i32 %tmp0, 192
324 define signext i32 @add_mul_combine_reject_d2(i32 signext %x) {
325 ; RV32IMB-LABEL: add_mul_combine_reject_d2:
327 ; RV32IMB-NEXT: addi a0, a0, 1000
328 ; RV32IMB-NEXT: sh1add a0, a0, a0
329 ; RV32IMB-NEXT: slli a0, a0, 6
332 ; RV64IMB-LABEL: add_mul_combine_reject_d2:
334 ; RV64IMB-NEXT: addi a0, a0, 1000
335 ; RV64IMB-NEXT: sh1add a0, a0, a0
336 ; RV64IMB-NEXT: slliw a0, a0, 6
338 %tmp0 = add i32 %x, 1000
339 %tmp1 = mul i32 %tmp0, 192
343 define i64 @add_mul_combine_reject_d3(i64 %x) {
344 ; RV32IMB-LABEL: add_mul_combine_reject_d3:
346 ; RV32IMB-NEXT: li a2, 192
347 ; RV32IMB-NEXT: mulhu a2, a0, a2
348 ; RV32IMB-NEXT: sh1add a1, a1, a1
349 ; RV32IMB-NEXT: slli a1, a1, 6
350 ; RV32IMB-NEXT: add a1, a2, a1
351 ; RV32IMB-NEXT: sh1add a0, a0, a0
352 ; RV32IMB-NEXT: slli a2, a0, 6
353 ; RV32IMB-NEXT: lui a0, 47
354 ; RV32IMB-NEXT: addi a0, a0, -512
355 ; RV32IMB-NEXT: add a0, a2, a0
356 ; RV32IMB-NEXT: sltu a2, a0, a2
357 ; RV32IMB-NEXT: add a1, a1, a2
360 ; RV64IMB-LABEL: add_mul_combine_reject_d3:
362 ; RV64IMB-NEXT: addi a0, a0, 1000
363 ; RV64IMB-NEXT: sh1add a0, a0, a0
364 ; RV64IMB-NEXT: slli a0, a0, 6
366 %tmp0 = add i64 %x, 1000
367 %tmp1 = mul i64 %tmp0, 192
371 define i32 @add_mul_combine_reject_e1(i32 %x) {
372 ; RV32IMB-LABEL: add_mul_combine_reject_e1:
374 ; RV32IMB-NEXT: addi a0, a0, 1971
375 ; RV32IMB-NEXT: sh1add a1, a0, a0
376 ; RV32IMB-NEXT: slli a0, a0, 5
377 ; RV32IMB-NEXT: sub a0, a0, a1
380 ; RV64IMB-LABEL: add_mul_combine_reject_e1:
382 ; RV64IMB-NEXT: addi a0, a0, 1971
383 ; RV64IMB-NEXT: sh1add a1, a0, a0
384 ; RV64IMB-NEXT: slli a0, a0, 5
385 ; RV64IMB-NEXT: subw a0, a0, a1
387 %tmp0 = mul i32 %x, 29
388 %tmp1 = add i32 %tmp0, 57159
392 define signext i32 @add_mul_combine_reject_e2(i32 signext %x) {
393 ; RV32IMB-LABEL: add_mul_combine_reject_e2:
395 ; RV32IMB-NEXT: addi a0, a0, 1971
396 ; RV32IMB-NEXT: sh1add a1, a0, a0
397 ; RV32IMB-NEXT: slli a0, a0, 5
398 ; RV32IMB-NEXT: sub a0, a0, a1
401 ; RV64IMB-LABEL: add_mul_combine_reject_e2:
403 ; RV64IMB-NEXT: addi a0, a0, 1971
404 ; RV64IMB-NEXT: sh1add a1, a0, a0
405 ; RV64IMB-NEXT: slli a0, a0, 5
406 ; RV64IMB-NEXT: subw a0, a0, a1
408 %tmp0 = mul i32 %x, 29
409 %tmp1 = add i32 %tmp0, 57159
413 define i64 @add_mul_combine_reject_e3(i64 %x) {
414 ; RV32IMB-LABEL: add_mul_combine_reject_e3:
416 ; RV32IMB-NEXT: li a2, 29
417 ; RV32IMB-NEXT: mulhu a2, a0, a2
418 ; RV32IMB-NEXT: sh1add a3, a1, a1
419 ; RV32IMB-NEXT: slli a1, a1, 5
420 ; RV32IMB-NEXT: sub a1, a1, a3
421 ; RV32IMB-NEXT: add a1, a2, a1
422 ; RV32IMB-NEXT: sh1add a2, a0, a0
423 ; RV32IMB-NEXT: slli a0, a0, 5
424 ; RV32IMB-NEXT: sub a2, a0, a2
425 ; RV32IMB-NEXT: lui a0, 14
426 ; RV32IMB-NEXT: addi a0, a0, -185
427 ; RV32IMB-NEXT: add a0, a2, a0
428 ; RV32IMB-NEXT: sltu a2, a0, a2
429 ; RV32IMB-NEXT: add a1, a1, a2
432 ; RV64IMB-LABEL: add_mul_combine_reject_e3:
434 ; RV64IMB-NEXT: addi a0, a0, 1971
435 ; RV64IMB-NEXT: sh1add a1, a0, a0
436 ; RV64IMB-NEXT: slli a0, a0, 5
437 ; RV64IMB-NEXT: sub a0, a0, a1
439 %tmp0 = mul i64 %x, 29
440 %tmp1 = add i64 %tmp0, 57159
444 define i32 @add_mul_combine_reject_f1(i32 %x) {
445 ; RV32IMB-LABEL: add_mul_combine_reject_f1:
447 ; RV32IMB-NEXT: addi a0, a0, 1972
448 ; RV32IMB-NEXT: sh1add a1, a0, a0
449 ; RV32IMB-NEXT: slli a0, a0, 5
450 ; RV32IMB-NEXT: sub a0, a0, a1
451 ; RV32IMB-NEXT: addi a0, a0, 11
454 ; RV64IMB-LABEL: add_mul_combine_reject_f1:
456 ; RV64IMB-NEXT: addi a0, a0, 1972
457 ; RV64IMB-NEXT: sh1add a1, a0, a0
458 ; RV64IMB-NEXT: slli a0, a0, 5
459 ; RV64IMB-NEXT: subw a0, a0, a1
460 ; RV64IMB-NEXT: addiw a0, a0, 11
462 %tmp0 = mul i32 %x, 29
463 %tmp1 = add i32 %tmp0, 57199
467 define signext i32 @add_mul_combine_reject_f2(i32 signext %x) {
468 ; RV32IMB-LABEL: add_mul_combine_reject_f2:
470 ; RV32IMB-NEXT: addi a0, a0, 1972
471 ; RV32IMB-NEXT: sh1add a1, a0, a0
472 ; RV32IMB-NEXT: slli a0, a0, 5
473 ; RV32IMB-NEXT: sub a0, a0, a1
474 ; RV32IMB-NEXT: addi a0, a0, 11
477 ; RV64IMB-LABEL: add_mul_combine_reject_f2:
479 ; RV64IMB-NEXT: addi a0, a0, 1972
480 ; RV64IMB-NEXT: sh1add a1, a0, a0
481 ; RV64IMB-NEXT: slli a0, a0, 5
482 ; RV64IMB-NEXT: subw a0, a0, a1
483 ; RV64IMB-NEXT: addiw a0, a0, 11
485 %tmp0 = mul i32 %x, 29
486 %tmp1 = add i32 %tmp0, 57199
490 define i64 @add_mul_combine_reject_f3(i64 %x) {
491 ; RV32IMB-LABEL: add_mul_combine_reject_f3:
493 ; RV32IMB-NEXT: li a2, 29
494 ; RV32IMB-NEXT: mulhu a2, a0, a2
495 ; RV32IMB-NEXT: sh1add a3, a1, a1
496 ; RV32IMB-NEXT: slli a1, a1, 5
497 ; RV32IMB-NEXT: sub a1, a1, a3
498 ; RV32IMB-NEXT: add a1, a2, a1
499 ; RV32IMB-NEXT: sh1add a2, a0, a0
500 ; RV32IMB-NEXT: slli a0, a0, 5
501 ; RV32IMB-NEXT: sub a2, a0, a2
502 ; RV32IMB-NEXT: lui a0, 14
503 ; RV32IMB-NEXT: addi a0, a0, -145
504 ; RV32IMB-NEXT: add a0, a2, a0
505 ; RV32IMB-NEXT: sltu a2, a0, a2
506 ; RV32IMB-NEXT: add a1, a1, a2
509 ; RV64IMB-LABEL: add_mul_combine_reject_f3:
511 ; RV64IMB-NEXT: addi a0, a0, 1972
512 ; RV64IMB-NEXT: sh1add a1, a0, a0
513 ; RV64IMB-NEXT: slli a0, a0, 5
514 ; RV64IMB-NEXT: sub a0, a0, a1
515 ; RV64IMB-NEXT: addi a0, a0, 11
517 %tmp0 = mul i64 %x, 29
518 %tmp1 = add i64 %tmp0, 57199
522 define i32 @add_mul_combine_reject_g1(i32 %x) {
523 ; RV32IMB-LABEL: add_mul_combine_reject_g1:
525 ; RV32IMB-NEXT: addi a0, a0, 100
526 ; RV32IMB-NEXT: sh3add a1, a0, a0
527 ; RV32IMB-NEXT: sh3add a0, a1, a0
528 ; RV32IMB-NEXT: addi a0, a0, 10
531 ; RV64IMB-LABEL: add_mul_combine_reject_g1:
533 ; RV64IMB-NEXT: addi a0, a0, 100
534 ; RV64IMB-NEXT: sh3add a1, a0, a0
535 ; RV64IMB-NEXT: sh3add a0, a1, a0
536 ; RV64IMB-NEXT: addiw a0, a0, 10
538 %tmp0 = mul i32 %x, 73
539 %tmp1 = add i32 %tmp0, 7310
543 define signext i32 @add_mul_combine_reject_g2(i32 signext %x) {
544 ; RV32IMB-LABEL: add_mul_combine_reject_g2:
546 ; RV32IMB-NEXT: addi a0, a0, 100
547 ; RV32IMB-NEXT: sh3add a1, a0, a0
548 ; RV32IMB-NEXT: sh3add a0, a1, a0
549 ; RV32IMB-NEXT: addi a0, a0, 10
552 ; RV64IMB-LABEL: add_mul_combine_reject_g2:
554 ; RV64IMB-NEXT: addi a0, a0, 100
555 ; RV64IMB-NEXT: sh3add a1, a0, a0
556 ; RV64IMB-NEXT: sh3add a0, a1, a0
557 ; RV64IMB-NEXT: addiw a0, a0, 10
559 %tmp0 = mul i32 %x, 73
560 %tmp1 = add i32 %tmp0, 7310
564 define i64 @add_mul_combine_reject_g3(i64 %x) {
565 ; RV32IMB-LABEL: add_mul_combine_reject_g3:
567 ; RV32IMB-NEXT: li a2, 73
568 ; RV32IMB-NEXT: mulhu a2, a0, a2
569 ; RV32IMB-NEXT: sh3add a3, a1, a1
570 ; RV32IMB-NEXT: sh3add a1, a3, a1
571 ; RV32IMB-NEXT: add a1, a2, a1
572 ; RV32IMB-NEXT: sh3add a2, a0, a0
573 ; RV32IMB-NEXT: sh3add a2, a2, a0
574 ; RV32IMB-NEXT: lui a0, 2
575 ; RV32IMB-NEXT: addi a0, a0, -882
576 ; RV32IMB-NEXT: add a0, a2, a0
577 ; RV32IMB-NEXT: sltu a2, a0, a2
578 ; RV32IMB-NEXT: add a1, a1, a2
581 ; RV64IMB-LABEL: add_mul_combine_reject_g3:
583 ; RV64IMB-NEXT: addi a0, a0, 100
584 ; RV64IMB-NEXT: sh3add a1, a0, a0
585 ; RV64IMB-NEXT: sh3add a0, a1, a0
586 ; RV64IMB-NEXT: addi a0, a0, 10
588 %tmp0 = mul i64 %x, 73
589 %tmp1 = add i64 %tmp0, 7310
593 ; This test previously infinite looped in DAG combine.
594 define i64 @add_mul_combine_infinite_loop(i64 %x) {
595 ; RV32IMB-LABEL: add_mul_combine_infinite_loop:
597 ; RV32IMB-NEXT: li a2, 24
598 ; RV32IMB-NEXT: mulhu a2, a0, a2
599 ; RV32IMB-NEXT: sh1add a1, a1, a1
600 ; RV32IMB-NEXT: sh3add a1, a1, a2
601 ; RV32IMB-NEXT: sh1add a0, a0, a0
602 ; RV32IMB-NEXT: slli a2, a0, 3
603 ; RV32IMB-NEXT: li a3, 1
604 ; RV32IMB-NEXT: slli a3, a3, 11
605 ; RV32IMB-NEXT: sh3add a0, a0, a3
606 ; RV32IMB-NEXT: sltu a2, a0, a2
607 ; RV32IMB-NEXT: add a1, a1, a2
610 ; RV64IMB-LABEL: add_mul_combine_infinite_loop:
612 ; RV64IMB-NEXT: addi a0, a0, 86
613 ; RV64IMB-NEXT: sh1add a0, a0, a0
614 ; RV64IMB-NEXT: slli a0, a0, 3
615 ; RV64IMB-NEXT: addi a0, a0, -16
617 %tmp0 = mul i64 %x, 24
618 %tmp1 = add i64 %tmp0, 2048
622 define i32 @mul3000_add8990_a(i32 %x) {
623 ; RV32IMB-LABEL: mul3000_add8990_a:
625 ; RV32IMB-NEXT: addi a0, a0, 3
626 ; RV32IMB-NEXT: lui a1, 1
627 ; RV32IMB-NEXT: addi a1, a1, -1096
628 ; RV32IMB-NEXT: mul a0, a0, a1
629 ; RV32IMB-NEXT: addi a0, a0, -10
632 ; RV64IMB-LABEL: mul3000_add8990_a:
634 ; RV64IMB-NEXT: addi a0, a0, 3
635 ; RV64IMB-NEXT: lui a1, 1
636 ; RV64IMB-NEXT: addi a1, a1, -1096
637 ; RV64IMB-NEXT: mul a0, a0, a1
638 ; RV64IMB-NEXT: addiw a0, a0, -10
640 %tmp0 = mul i32 %x, 3000
641 %tmp1 = add i32 %tmp0, 8990
645 define signext i32 @mul3000_add8990_b(i32 signext %x) {
646 ; RV32IMB-LABEL: mul3000_add8990_b:
648 ; RV32IMB-NEXT: addi a0, a0, 3
649 ; RV32IMB-NEXT: lui a1, 1
650 ; RV32IMB-NEXT: addi a1, a1, -1096
651 ; RV32IMB-NEXT: mul a0, a0, a1
652 ; RV32IMB-NEXT: addi a0, a0, -10
655 ; RV64IMB-LABEL: mul3000_add8990_b:
657 ; RV64IMB-NEXT: addi a0, a0, 3
658 ; RV64IMB-NEXT: lui a1, 1
659 ; RV64IMB-NEXT: addi a1, a1, -1096
660 ; RV64IMB-NEXT: mul a0, a0, a1
661 ; RV64IMB-NEXT: addiw a0, a0, -10
663 %tmp0 = mul i32 %x, 3000
664 %tmp1 = add i32 %tmp0, 8990
668 define i64 @mul3000_add8990_c(i64 %x) {
669 ; RV32IMB-LABEL: mul3000_add8990_c:
671 ; RV32IMB-NEXT: lui a2, 1
672 ; RV32IMB-NEXT: addi a2, a2, -1096
673 ; RV32IMB-NEXT: mul a1, a1, a2
674 ; RV32IMB-NEXT: mulhu a3, a0, a2
675 ; RV32IMB-NEXT: add a1, a3, a1
676 ; RV32IMB-NEXT: mul a2, a0, a2
677 ; RV32IMB-NEXT: lui a0, 2
678 ; RV32IMB-NEXT: addi a0, a0, 798
679 ; RV32IMB-NEXT: add a0, a2, a0
680 ; RV32IMB-NEXT: sltu a2, a0, a2
681 ; RV32IMB-NEXT: add a1, a1, a2
684 ; RV64IMB-LABEL: mul3000_add8990_c:
686 ; RV64IMB-NEXT: addi a0, a0, 3
687 ; RV64IMB-NEXT: lui a1, 1
688 ; RV64IMB-NEXT: addiw a1, a1, -1096
689 ; RV64IMB-NEXT: mul a0, a0, a1
690 ; RV64IMB-NEXT: addi a0, a0, -10
692 %tmp0 = mul i64 %x, 3000
693 %tmp1 = add i64 %tmp0, 8990
697 define i32 @mul3000_sub8990_a(i32 %x) {
698 ; RV32IMB-LABEL: mul3000_sub8990_a:
700 ; RV32IMB-NEXT: addi a0, a0, -3
701 ; RV32IMB-NEXT: lui a1, 1
702 ; RV32IMB-NEXT: addi a1, a1, -1096
703 ; RV32IMB-NEXT: mul a0, a0, a1
704 ; RV32IMB-NEXT: addi a0, a0, 10
707 ; RV64IMB-LABEL: mul3000_sub8990_a:
709 ; RV64IMB-NEXT: addi a0, a0, -3
710 ; RV64IMB-NEXT: lui a1, 1
711 ; RV64IMB-NEXT: addi a1, a1, -1096
712 ; RV64IMB-NEXT: mul a0, a0, a1
713 ; RV64IMB-NEXT: addiw a0, a0, 10
715 %tmp0 = mul i32 %x, 3000
716 %tmp1 = add i32 %tmp0, -8990
720 define signext i32 @mul3000_sub8990_b(i32 signext %x) {
721 ; RV32IMB-LABEL: mul3000_sub8990_b:
723 ; RV32IMB-NEXT: addi a0, a0, -3
724 ; RV32IMB-NEXT: lui a1, 1
725 ; RV32IMB-NEXT: addi a1, a1, -1096
726 ; RV32IMB-NEXT: mul a0, a0, a1
727 ; RV32IMB-NEXT: addi a0, a0, 10
730 ; RV64IMB-LABEL: mul3000_sub8990_b:
732 ; RV64IMB-NEXT: addi a0, a0, -3
733 ; RV64IMB-NEXT: lui a1, 1
734 ; RV64IMB-NEXT: addi a1, a1, -1096
735 ; RV64IMB-NEXT: mul a0, a0, a1
736 ; RV64IMB-NEXT: addiw a0, a0, 10
738 %tmp0 = mul i32 %x, 3000
739 %tmp1 = add i32 %tmp0, -8990
743 define i64 @mul3000_sub8990_c(i64 %x) {
744 ; RV32IMB-LABEL: mul3000_sub8990_c:
746 ; RV32IMB-NEXT: lui a2, 1
747 ; RV32IMB-NEXT: addi a2, a2, -1096
748 ; RV32IMB-NEXT: mul a1, a1, a2
749 ; RV32IMB-NEXT: mulhu a3, a0, a2
750 ; RV32IMB-NEXT: add a1, a3, a1
751 ; RV32IMB-NEXT: mul a2, a0, a2
752 ; RV32IMB-NEXT: lui a0, 1048574
753 ; RV32IMB-NEXT: addi a0, a0, -798
754 ; RV32IMB-NEXT: add a0, a2, a0
755 ; RV32IMB-NEXT: sltu a2, a0, a2
756 ; RV32IMB-NEXT: add a1, a1, a2
757 ; RV32IMB-NEXT: addi a1, a1, -1
760 ; RV64IMB-LABEL: mul3000_sub8990_c:
762 ; RV64IMB-NEXT: addi a0, a0, -3
763 ; RV64IMB-NEXT: lui a1, 1
764 ; RV64IMB-NEXT: addiw a1, a1, -1096
765 ; RV64IMB-NEXT: mul a0, a0, a1
766 ; RV64IMB-NEXT: addi a0, a0, 10
768 %tmp0 = mul i64 %x, 3000
769 %tmp1 = add i64 %tmp0, -8990
773 define i32 @mulneg3000_add8990_a(i32 %x) {
774 ; RV32IMB-LABEL: mulneg3000_add8990_a:
776 ; RV32IMB-NEXT: addi a0, a0, -3
777 ; RV32IMB-NEXT: lui a1, 1048575
778 ; RV32IMB-NEXT: addi a1, a1, 1096
779 ; RV32IMB-NEXT: mul a0, a0, a1
780 ; RV32IMB-NEXT: addi a0, a0, -10
783 ; RV64IMB-LABEL: mulneg3000_add8990_a:
785 ; RV64IMB-NEXT: addi a0, a0, -3
786 ; RV64IMB-NEXT: lui a1, 1048575
787 ; RV64IMB-NEXT: addi a1, a1, 1096
788 ; RV64IMB-NEXT: mul a0, a0, a1
789 ; RV64IMB-NEXT: addiw a0, a0, -10
791 %tmp0 = mul i32 %x, -3000
792 %tmp1 = add i32 %tmp0, 8990
796 define signext i32 @mulneg3000_add8990_b(i32 signext %x) {
797 ; RV32IMB-LABEL: mulneg3000_add8990_b:
799 ; RV32IMB-NEXT: addi a0, a0, -3
800 ; RV32IMB-NEXT: lui a1, 1048575
801 ; RV32IMB-NEXT: addi a1, a1, 1096
802 ; RV32IMB-NEXT: mul a0, a0, a1
803 ; RV32IMB-NEXT: addi a0, a0, -10
806 ; RV64IMB-LABEL: mulneg3000_add8990_b:
808 ; RV64IMB-NEXT: addi a0, a0, -3
809 ; RV64IMB-NEXT: lui a1, 1048575
810 ; RV64IMB-NEXT: addi a1, a1, 1096
811 ; RV64IMB-NEXT: mul a0, a0, a1
812 ; RV64IMB-NEXT: addiw a0, a0, -10
814 %tmp0 = mul i32 %x, -3000
815 %tmp1 = add i32 %tmp0, 8990
819 define i64 @mulneg3000_add8990_c(i64 %x) {
820 ; RV32IMB-LABEL: mulneg3000_add8990_c:
822 ; RV32IMB-NEXT: lui a2, 1048575
823 ; RV32IMB-NEXT: addi a2, a2, 1096
824 ; RV32IMB-NEXT: mul a1, a1, a2
825 ; RV32IMB-NEXT: mulhu a3, a0, a2
826 ; RV32IMB-NEXT: sub a3, a3, a0
827 ; RV32IMB-NEXT: add a1, a3, a1
828 ; RV32IMB-NEXT: mul a2, a0, a2
829 ; RV32IMB-NEXT: lui a0, 2
830 ; RV32IMB-NEXT: addi a0, a0, 798
831 ; RV32IMB-NEXT: add a0, a2, a0
832 ; RV32IMB-NEXT: sltu a2, a0, a2
833 ; RV32IMB-NEXT: add a1, a1, a2
836 ; RV64IMB-LABEL: mulneg3000_add8990_c:
838 ; RV64IMB-NEXT: addi a0, a0, -3
839 ; RV64IMB-NEXT: lui a1, 1048575
840 ; RV64IMB-NEXT: addiw a1, a1, 1096
841 ; RV64IMB-NEXT: mul a0, a0, a1
842 ; RV64IMB-NEXT: addi a0, a0, -10
844 %tmp0 = mul i64 %x, -3000
845 %tmp1 = add i64 %tmp0, 8990
849 define i32 @mulneg3000_sub8990_a(i32 %x) {
850 ; RV32IMB-LABEL: mulneg3000_sub8990_a:
852 ; RV32IMB-NEXT: addi a0, a0, 3
853 ; RV32IMB-NEXT: lui a1, 1048575
854 ; RV32IMB-NEXT: addi a1, a1, 1096
855 ; RV32IMB-NEXT: mul a0, a0, a1
856 ; RV32IMB-NEXT: addi a0, a0, 10
859 ; RV64IMB-LABEL: mulneg3000_sub8990_a:
861 ; RV64IMB-NEXT: addi a0, a0, 3
862 ; RV64IMB-NEXT: lui a1, 1048575
863 ; RV64IMB-NEXT: addi a1, a1, 1096
864 ; RV64IMB-NEXT: mul a0, a0, a1
865 ; RV64IMB-NEXT: addiw a0, a0, 10
867 %tmp0 = mul i32 %x, -3000
868 %tmp1 = add i32 %tmp0, -8990
872 define signext i32 @mulneg3000_sub8990_b(i32 signext %x) {
873 ; RV32IMB-LABEL: mulneg3000_sub8990_b:
875 ; RV32IMB-NEXT: addi a0, a0, 3
876 ; RV32IMB-NEXT: lui a1, 1048575
877 ; RV32IMB-NEXT: addi a1, a1, 1096
878 ; RV32IMB-NEXT: mul a0, a0, a1
879 ; RV32IMB-NEXT: addi a0, a0, 10
882 ; RV64IMB-LABEL: mulneg3000_sub8990_b:
884 ; RV64IMB-NEXT: addi a0, a0, 3
885 ; RV64IMB-NEXT: lui a1, 1048575
886 ; RV64IMB-NEXT: addi a1, a1, 1096
887 ; RV64IMB-NEXT: mul a0, a0, a1
888 ; RV64IMB-NEXT: addiw a0, a0, 10
890 %tmp0 = mul i32 %x, -3000
891 %tmp1 = add i32 %tmp0, -8990
895 define i64 @mulneg3000_sub8990_c(i64 %x) {
896 ; RV32IMB-LABEL: mulneg3000_sub8990_c:
898 ; RV32IMB-NEXT: lui a2, 1048575
899 ; RV32IMB-NEXT: addi a2, a2, 1096
900 ; RV32IMB-NEXT: mul a1, a1, a2
901 ; RV32IMB-NEXT: mulhu a3, a0, a2
902 ; RV32IMB-NEXT: sub a3, a3, a0
903 ; RV32IMB-NEXT: add a1, a3, a1
904 ; RV32IMB-NEXT: mul a2, a0, a2
905 ; RV32IMB-NEXT: lui a0, 1048574
906 ; RV32IMB-NEXT: addi a0, a0, -798
907 ; RV32IMB-NEXT: add a0, a2, a0
908 ; RV32IMB-NEXT: sltu a2, a0, a2
909 ; RV32IMB-NEXT: add a1, a1, a2
910 ; RV32IMB-NEXT: addi a1, a1, -1
913 ; RV64IMB-LABEL: mulneg3000_sub8990_c:
915 ; RV64IMB-NEXT: addi a0, a0, 3
916 ; RV64IMB-NEXT: lui a1, 1048575
917 ; RV64IMB-NEXT: addiw a1, a1, 1096
918 ; RV64IMB-NEXT: mul a0, a0, a1
919 ; RV64IMB-NEXT: addi a0, a0, 10
921 %tmp0 = mul i64 %x, -3000
922 %tmp1 = add i64 %tmp0, -8990
926 ; This test case previously caused an infinite loop between transformations
927 ; performed in RISCVISelLowering;:transformAddImmMulImm and
928 ; DAGCombiner::visitMUL.
929 define i1 @pr53831(i32 %x) {
930 ; RV32IMB-LABEL: pr53831:
932 ; RV32IMB-NEXT: li a0, 0
935 ; RV64IMB-LABEL: pr53831:
937 ; RV64IMB-NEXT: li a0, 0
939 %tmp0 = add i32 %x, 1
940 %tmp1 = mul i32 %tmp0, 24
941 %tmp2 = add i32 %tmp1, 1
942 %tmp3 = mul i32 %x, 24
943 %tmp4 = add i32 %tmp3, 2048
944 %tmp5 = icmp eq i32 %tmp4, %tmp2
948 define i64 @sh2add_uw(i64 signext %0, i32 signext %1) {
949 ; RV32IMB-LABEL: sh2add_uw:
950 ; RV32IMB: # %bb.0: # %entry
951 ; RV32IMB-NEXT: srli a3, a2, 27
952 ; RV32IMB-NEXT: slli a2, a2, 5
953 ; RV32IMB-NEXT: srli a4, a0, 29
954 ; RV32IMB-NEXT: sh3add a1, a1, a4
955 ; RV32IMB-NEXT: sh3add a0, a0, a2
956 ; RV32IMB-NEXT: sltu a2, a0, a2
957 ; RV32IMB-NEXT: add a1, a3, a1
958 ; RV32IMB-NEXT: add a1, a1, a2
961 ; RV64IMB-LABEL: sh2add_uw:
962 ; RV64IMB: # %bb.0: # %entry
963 ; RV64IMB-NEXT: sh2add.uw a0, a1, a0
964 ; RV64IMB-NEXT: slli a0, a0, 3
967 %2 = zext i32 %1 to i64