| blob | b1efe53290e8ee142bf492a1a53a94cdfcbdd961 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m -verify-machineinstrs | FileCheck %s --check-prefix=RV32
3 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m -verify-machineinstrs | FileCheck %s --check-prefix=RV64
4 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zba -verify-machineinstrs | FileCheck %s --check-prefix=RV32ZBA
5 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zba -verify-machineinstrs | FileCheck %s --check-prefix=RV64ZBA
6 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zicond -verify-machineinstrs | FileCheck %s --check-prefix=RV32ZICOND
7 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zicond -verify-machineinstrs | FileCheck %s --check-prefix=RV64ZICOND
9 ;
10 ; Get the actual value of the overflow bit.
11 ;
12 define zeroext i1 @saddo1.i32(i32 signext %v1, i32 signext %v2, ptr %res) {
13 ; RV32-LABEL: saddo1.i32:
14 ; RV32: # %bb.0: # %entry
15 ; RV32-NEXT: add a3, a0, a1
16 ; RV32-NEXT: slt a0, a3, a0
17 ; RV32-NEXT: slti a1, a1, 0
18 ; RV32-NEXT: xor a0, a1, a0
19 ; RV32-NEXT: sw a3, 0(a2)
20 ; RV32-NEXT: ret
21 ;
22 ; RV64-LABEL: saddo1.i32:
23 ; RV64: # %bb.0: # %entry
24 ; RV64-NEXT: add a3, a0, a1
25 ; RV64-NEXT: addw a0, a0, a1
26 ; RV64-NEXT: xor a0, a0, a3
27 ; RV64-NEXT: snez a0, a0
28 ; RV64-NEXT: sw a3, 0(a2)
29 ; RV64-NEXT: ret
30 ;
31 ; RV32ZBA-LABEL: saddo1.i32:
32 ; RV32ZBA: # %bb.0: # %entry
33 ; RV32ZBA-NEXT: add a3, a0, a1
34 ; RV32ZBA-NEXT: slt a0, a3, a0
35 ; RV32ZBA-NEXT: slti a1, a1, 0
36 ; RV32ZBA-NEXT: xor a0, a1, a0
37 ; RV32ZBA-NEXT: sw a3, 0(a2)
38 ; RV32ZBA-NEXT: ret
39 ;
40 ; RV64ZBA-LABEL: saddo1.i32:
41 ; RV64ZBA: # %bb.0: # %entry
42 ; RV64ZBA-NEXT: add a3, a0, a1
43 ; RV64ZBA-NEXT: addw a0, a0, a1
44 ; RV64ZBA-NEXT: xor a0, a0, a3
45 ; RV64ZBA-NEXT: snez a0, a0
46 ; RV64ZBA-NEXT: sw a3, 0(a2)
47 ; RV64ZBA-NEXT: ret
48 ;
49 ; RV32ZICOND-LABEL: saddo1.i32:
50 ; RV32ZICOND: # %bb.0: # %entry
51 ; RV32ZICOND-NEXT: add a3, a0, a1
52 ; RV32ZICOND-NEXT: slt a0, a3, a0
53 ; RV32ZICOND-NEXT: slti a1, a1, 0
54 ; RV32ZICOND-NEXT: xor a0, a1, a0
55 ; RV32ZICOND-NEXT: sw a3, 0(a2)
56 ; RV32ZICOND-NEXT: ret
57 ;
58 ; RV64ZICOND-LABEL: saddo1.i32:
59 ; RV64ZICOND: # %bb.0: # %entry
60 ; RV64ZICOND-NEXT: add a3, a0, a1
61 ; RV64ZICOND-NEXT: addw a0, a0, a1
62 ; RV64ZICOND-NEXT: xor a0, a0, a3
63 ; RV64ZICOND-NEXT: snez a0, a0
64 ; RV64ZICOND-NEXT: sw a3, 0(a2)
65 ; RV64ZICOND-NEXT: ret
66 entry:
67 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
68 %val = extractvalue {i32, i1} %t, 0
69 %obit = extractvalue {i32, i1} %t, 1
70 store i32 %val, ptr %res
71 ret i1 %obit
72 }
74 ; Test the immediate version.
75 define zeroext i1 @saddo2.i32(i32 signext %v1, ptr %res) {
76 ; RV32-LABEL: saddo2.i32:
77 ; RV32: # %bb.0: # %entry
78 ; RV32-NEXT: addi a2, a0, 4
79 ; RV32-NEXT: slt a0, a2, a0
80 ; RV32-NEXT: sw a2, 0(a1)
81 ; RV32-NEXT: ret
82 ;
83 ; RV64-LABEL: saddo2.i32:
84 ; RV64: # %bb.0: # %entry
85 ; RV64-NEXT: addiw a2, a0, 4
86 ; RV64-NEXT: slt a0, a2, a0
87 ; RV64-NEXT: sw a2, 0(a1)
88 ; RV64-NEXT: ret
89 ;
90 ; RV32ZBA-LABEL: saddo2.i32:
91 ; RV32ZBA: # %bb.0: # %entry
92 ; RV32ZBA-NEXT: addi a2, a0, 4
93 ; RV32ZBA-NEXT: slt a0, a2, a0
94 ; RV32ZBA-NEXT: sw a2, 0(a1)
95 ; RV32ZBA-NEXT: ret
96 ;
97 ; RV64ZBA-LABEL: saddo2.i32:
98 ; RV64ZBA: # %bb.0: # %entry
99 ; RV64ZBA-NEXT: addiw a2, a0, 4
100 ; RV64ZBA-NEXT: slt a0, a2, a0
101 ; RV64ZBA-NEXT: sw a2, 0(a1)
102 ; RV64ZBA-NEXT: ret
103 ;
104 ; RV32ZICOND-LABEL: saddo2.i32:
105 ; RV32ZICOND: # %bb.0: # %entry
106 ; RV32ZICOND-NEXT: addi a2, a0, 4
107 ; RV32ZICOND-NEXT: slt a0, a2, a0
108 ; RV32ZICOND-NEXT: sw a2, 0(a1)
109 ; RV32ZICOND-NEXT: ret
110 ;
111 ; RV64ZICOND-LABEL: saddo2.i32:
112 ; RV64ZICOND: # %bb.0: # %entry
113 ; RV64ZICOND-NEXT: addiw a2, a0, 4
114 ; RV64ZICOND-NEXT: slt a0, a2, a0
115 ; RV64ZICOND-NEXT: sw a2, 0(a1)
116 ; RV64ZICOND-NEXT: ret
117 entry:
118 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 4)
119 %val = extractvalue {i32, i1} %t, 0
120 %obit = extractvalue {i32, i1} %t, 1
121 store i32 %val, ptr %res
122 ret i1 %obit
123 }
125 ; Test negative immediates.
126 define zeroext i1 @saddo3.i32(i32 signext %v1, ptr %res) {
127 ; RV32-LABEL: saddo3.i32:
128 ; RV32: # %bb.0: # %entry
129 ; RV32-NEXT: addi a2, a0, -4
130 ; RV32-NEXT: slt a0, a2, a0
131 ; RV32-NEXT: xori a0, a0, 1
132 ; RV32-NEXT: sw a2, 0(a1)
133 ; RV32-NEXT: ret
134 ;
135 ; RV64-LABEL: saddo3.i32:
136 ; RV64: # %bb.0: # %entry
137 ; RV64-NEXT: addiw a2, a0, -4
138 ; RV64-NEXT: slt a0, a2, a0
139 ; RV64-NEXT: xori a0, a0, 1
140 ; RV64-NEXT: sw a2, 0(a1)
141 ; RV64-NEXT: ret
142 ;
143 ; RV32ZBA-LABEL: saddo3.i32:
144 ; RV32ZBA: # %bb.0: # %entry
145 ; RV32ZBA-NEXT: addi a2, a0, -4
146 ; RV32ZBA-NEXT: slt a0, a2, a0
147 ; RV32ZBA-NEXT: xori a0, a0, 1
148 ; RV32ZBA-NEXT: sw a2, 0(a1)
149 ; RV32ZBA-NEXT: ret
150 ;
151 ; RV64ZBA-LABEL: saddo3.i32:
152 ; RV64ZBA: # %bb.0: # %entry
153 ; RV64ZBA-NEXT: addiw a2, a0, -4
154 ; RV64ZBA-NEXT: slt a0, a2, a0
155 ; RV64ZBA-NEXT: xori a0, a0, 1
156 ; RV64ZBA-NEXT: sw a2, 0(a1)
157 ; RV64ZBA-NEXT: ret
158 ;
159 ; RV32ZICOND-LABEL: saddo3.i32:
160 ; RV32ZICOND: # %bb.0: # %entry
161 ; RV32ZICOND-NEXT: addi a2, a0, -4
162 ; RV32ZICOND-NEXT: slt a0, a2, a0
163 ; RV32ZICOND-NEXT: xori a0, a0, 1
164 ; RV32ZICOND-NEXT: sw a2, 0(a1)
165 ; RV32ZICOND-NEXT: ret
166 ;
167 ; RV64ZICOND-LABEL: saddo3.i32:
168 ; RV64ZICOND: # %bb.0: # %entry
169 ; RV64ZICOND-NEXT: addiw a2, a0, -4
170 ; RV64ZICOND-NEXT: slt a0, a2, a0
171 ; RV64ZICOND-NEXT: xori a0, a0, 1
172 ; RV64ZICOND-NEXT: sw a2, 0(a1)
173 ; RV64ZICOND-NEXT: ret
174 entry:
175 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 -4)
176 %val = extractvalue {i32, i1} %t, 0
177 %obit = extractvalue {i32, i1} %t, 1
178 store i32 %val, ptr %res
179 ret i1 %obit
180 }
182 ; Test immediates that are too large to be encoded.
183 define zeroext i1 @saddo4.i32(i32 signext %v1, ptr %res) {
184 ; RV32-LABEL: saddo4.i32:
185 ; RV32: # %bb.0: # %entry
186 ; RV32-NEXT: lui a2, 4096
187 ; RV32-NEXT: addi a2, a2, -1
188 ; RV32-NEXT: add a2, a0, a2
189 ; RV32-NEXT: slt a0, a2, a0
190 ; RV32-NEXT: sw a2, 0(a1)
191 ; RV32-NEXT: ret
192 ;
193 ; RV64-LABEL: saddo4.i32:
194 ; RV64: # %bb.0: # %entry
195 ; RV64-NEXT: lui a2, 4096
196 ; RV64-NEXT: addi a2, a2, -1
197 ; RV64-NEXT: addw a2, a0, a2
198 ; RV64-NEXT: slt a0, a2, a0
199 ; RV64-NEXT: sw a2, 0(a1)
200 ; RV64-NEXT: ret
201 ;
202 ; RV32ZBA-LABEL: saddo4.i32:
203 ; RV32ZBA: # %bb.0: # %entry
204 ; RV32ZBA-NEXT: lui a2, 4096
205 ; RV32ZBA-NEXT: addi a2, a2, -1
206 ; RV32ZBA-NEXT: add a2, a0, a2
207 ; RV32ZBA-NEXT: slt a0, a2, a0
208 ; RV32ZBA-NEXT: sw a2, 0(a1)
209 ; RV32ZBA-NEXT: ret
210 ;
211 ; RV64ZBA-LABEL: saddo4.i32:
212 ; RV64ZBA: # %bb.0: # %entry
213 ; RV64ZBA-NEXT: lui a2, 4096
214 ; RV64ZBA-NEXT: addi a2, a2, -1
215 ; RV64ZBA-NEXT: addw a2, a0, a2
216 ; RV64ZBA-NEXT: slt a0, a2, a0
217 ; RV64ZBA-NEXT: sw a2, 0(a1)
218 ; RV64ZBA-NEXT: ret
219 ;
220 ; RV32ZICOND-LABEL: saddo4.i32:
221 ; RV32ZICOND: # %bb.0: # %entry
222 ; RV32ZICOND-NEXT: lui a2, 4096
223 ; RV32ZICOND-NEXT: addi a2, a2, -1
224 ; RV32ZICOND-NEXT: add a2, a0, a2
225 ; RV32ZICOND-NEXT: slt a0, a2, a0
226 ; RV32ZICOND-NEXT: sw a2, 0(a1)
227 ; RV32ZICOND-NEXT: ret
228 ;
229 ; RV64ZICOND-LABEL: saddo4.i32:
230 ; RV64ZICOND: # %bb.0: # %entry
231 ; RV64ZICOND-NEXT: lui a2, 4096
232 ; RV64ZICOND-NEXT: addi a2, a2, -1
233 ; RV64ZICOND-NEXT: addw a2, a0, a2
234 ; RV64ZICOND-NEXT: slt a0, a2, a0
235 ; RV64ZICOND-NEXT: sw a2, 0(a1)
236 ; RV64ZICOND-NEXT: ret
237 entry:
238 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 16777215)
239 %val = extractvalue {i32, i1} %t, 0
240 %obit = extractvalue {i32, i1} %t, 1
241 store i32 %val, ptr %res
242 ret i1 %obit
243 }
245 define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, ptr %res) {
246 ; RV32-LABEL: saddo1.i64:
247 ; RV32: # %bb.0: # %entry
248 ; RV32-NEXT: add a5, a1, a3
249 ; RV32-NEXT: add a2, a0, a2
250 ; RV32-NEXT: sltu a0, a2, a0
251 ; RV32-NEXT: add a5, a5, a0
252 ; RV32-NEXT: xor a0, a1, a5
253 ; RV32-NEXT: xor a1, a1, a3
254 ; RV32-NEXT: not a1, a1
255 ; RV32-NEXT: and a0, a1, a0
256 ; RV32-NEXT: slti a0, a0, 0
257 ; RV32-NEXT: sw a2, 0(a4)
258 ; RV32-NEXT: sw a5, 4(a4)
259 ; RV32-NEXT: ret
260 ;
261 ; RV64-LABEL: saddo1.i64:
262 ; RV64: # %bb.0: # %entry
263 ; RV64-NEXT: add a3, a0, a1
264 ; RV64-NEXT: slt a0, a3, a0
265 ; RV64-NEXT: slti a1, a1, 0
266 ; RV64-NEXT: xor a0, a1, a0
267 ; RV64-NEXT: sd a3, 0(a2)
268 ; RV64-NEXT: ret
269 ;
270 ; RV32ZBA-LABEL: saddo1.i64:
271 ; RV32ZBA: # %bb.0: # %entry
272 ; RV32ZBA-NEXT: add a5, a1, a3
273 ; RV32ZBA-NEXT: add a2, a0, a2
274 ; RV32ZBA-NEXT: sltu a0, a2, a0
275 ; RV32ZBA-NEXT: add a5, a5, a0
276 ; RV32ZBA-NEXT: xor a0, a1, a5
277 ; RV32ZBA-NEXT: xor a1, a1, a3
278 ; RV32ZBA-NEXT: not a1, a1
279 ; RV32ZBA-NEXT: and a0, a1, a0
280 ; RV32ZBA-NEXT: slti a0, a0, 0
281 ; RV32ZBA-NEXT: sw a2, 0(a4)
282 ; RV32ZBA-NEXT: sw a5, 4(a4)
283 ; RV32ZBA-NEXT: ret
284 ;
285 ; RV64ZBA-LABEL: saddo1.i64:
286 ; RV64ZBA: # %bb.0: # %entry
287 ; RV64ZBA-NEXT: add a3, a0, a1
288 ; RV64ZBA-NEXT: slt a0, a3, a0
289 ; RV64ZBA-NEXT: slti a1, a1, 0
290 ; RV64ZBA-NEXT: xor a0, a1, a0
291 ; RV64ZBA-NEXT: sd a3, 0(a2)
292 ; RV64ZBA-NEXT: ret
293 ;
294 ; RV32ZICOND-LABEL: saddo1.i64:
295 ; RV32ZICOND: # %bb.0: # %entry
296 ; RV32ZICOND-NEXT: add a5, a1, a3
297 ; RV32ZICOND-NEXT: add a2, a0, a2
298 ; RV32ZICOND-NEXT: sltu a0, a2, a0
299 ; RV32ZICOND-NEXT: add a5, a5, a0
300 ; RV32ZICOND-NEXT: xor a0, a1, a5
301 ; RV32ZICOND-NEXT: xor a1, a1, a3
302 ; RV32ZICOND-NEXT: not a1, a1
303 ; RV32ZICOND-NEXT: and a0, a1, a0
304 ; RV32ZICOND-NEXT: slti a0, a0, 0
305 ; RV32ZICOND-NEXT: sw a2, 0(a4)
306 ; RV32ZICOND-NEXT: sw a5, 4(a4)
307 ; RV32ZICOND-NEXT: ret
308 ;
309 ; RV64ZICOND-LABEL: saddo1.i64:
310 ; RV64ZICOND: # %bb.0: # %entry
311 ; RV64ZICOND-NEXT: add a3, a0, a1
312 ; RV64ZICOND-NEXT: slt a0, a3, a0
313 ; RV64ZICOND-NEXT: slti a1, a1, 0
314 ; RV64ZICOND-NEXT: xor a0, a1, a0
315 ; RV64ZICOND-NEXT: sd a3, 0(a2)
316 ; RV64ZICOND-NEXT: ret
317 entry:
318 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
319 %val = extractvalue {i64, i1} %t, 0
320 %obit = extractvalue {i64, i1} %t, 1
321 store i64 %val, ptr %res
322 ret i1 %obit
323 }
325 define zeroext i1 @saddo2.i64(i64 %v1, ptr %res) {
326 ; RV32-LABEL: saddo2.i64:
327 ; RV32: # %bb.0: # %entry
328 ; RV32-NEXT: addi a3, a0, 4
329 ; RV32-NEXT: sltu a0, a3, a0
330 ; RV32-NEXT: add a4, a1, a0
331 ; RV32-NEXT: xor a0, a1, a4
332 ; RV32-NEXT: not a1, a1
333 ; RV32-NEXT: and a0, a1, a0
334 ; RV32-NEXT: slti a0, a0, 0
335 ; RV32-NEXT: sw a3, 0(a2)
336 ; RV32-NEXT: sw a4, 4(a2)
337 ; RV32-NEXT: ret
338 ;
339 ; RV64-LABEL: saddo2.i64:
340 ; RV64: # %bb.0: # %entry
341 ; RV64-NEXT: addi a2, a0, 4
342 ; RV64-NEXT: slt a0, a2, a0
343 ; RV64-NEXT: sd a2, 0(a1)
344 ; RV64-NEXT: ret
345 ;
346 ; RV32ZBA-LABEL: saddo2.i64:
347 ; RV32ZBA: # %bb.0: # %entry
348 ; RV32ZBA-NEXT: addi a3, a0, 4
349 ; RV32ZBA-NEXT: sltu a0, a3, a0
350 ; RV32ZBA-NEXT: add a4, a1, a0
351 ; RV32ZBA-NEXT: xor a0, a1, a4
352 ; RV32ZBA-NEXT: not a1, a1
353 ; RV32ZBA-NEXT: and a0, a1, a0
354 ; RV32ZBA-NEXT: slti a0, a0, 0
355 ; RV32ZBA-NEXT: sw a3, 0(a2)
356 ; RV32ZBA-NEXT: sw a4, 4(a2)
357 ; RV32ZBA-NEXT: ret
358 ;
359 ; RV64ZBA-LABEL: saddo2.i64:
360 ; RV64ZBA: # %bb.0: # %entry
361 ; RV64ZBA-NEXT: addi a2, a0, 4
362 ; RV64ZBA-NEXT: slt a0, a2, a0
363 ; RV64ZBA-NEXT: sd a2, 0(a1)
364 ; RV64ZBA-NEXT: ret
365 ;
366 ; RV32ZICOND-LABEL: saddo2.i64:
367 ; RV32ZICOND: # %bb.0: # %entry
368 ; RV32ZICOND-NEXT: addi a3, a0, 4
369 ; RV32ZICOND-NEXT: sltu a0, a3, a0
370 ; RV32ZICOND-NEXT: add a4, a1, a0
371 ; RV32ZICOND-NEXT: xor a0, a1, a4
372 ; RV32ZICOND-NEXT: not a1, a1
373 ; RV32ZICOND-NEXT: and a0, a1, a0
374 ; RV32ZICOND-NEXT: slti a0, a0, 0
375 ; RV32ZICOND-NEXT: sw a3, 0(a2)
376 ; RV32ZICOND-NEXT: sw a4, 4(a2)
377 ; RV32ZICOND-NEXT: ret
378 ;
379 ; RV64ZICOND-LABEL: saddo2.i64:
380 ; RV64ZICOND: # %bb.0: # %entry
381 ; RV64ZICOND-NEXT: addi a2, a0, 4
382 ; RV64ZICOND-NEXT: slt a0, a2, a0
383 ; RV64ZICOND-NEXT: sd a2, 0(a1)
384 ; RV64ZICOND-NEXT: ret
385 entry:
386 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 4)
387 %val = extractvalue {i64, i1} %t, 0
388 %obit = extractvalue {i64, i1} %t, 1
389 store i64 %val, ptr %res
390 ret i1 %obit
391 }
393 define zeroext i1 @saddo3.i64(i64 %v1, ptr %res) {
394 ; RV32-LABEL: saddo3.i64:
395 ; RV32: # %bb.0: # %entry
396 ; RV32-NEXT: addi a3, a0, -4
397 ; RV32-NEXT: sltu a0, a3, a0
398 ; RV32-NEXT: add a0, a1, a0
399 ; RV32-NEXT: addi a4, a0, -1
400 ; RV32-NEXT: xor a0, a1, a4
401 ; RV32-NEXT: and a0, a1, a0
402 ; RV32-NEXT: slti a0, a0, 0
403 ; RV32-NEXT: sw a3, 0(a2)
404 ; RV32-NEXT: sw a4, 4(a2)
405 ; RV32-NEXT: ret
406 ;
407 ; RV64-LABEL: saddo3.i64:
408 ; RV64: # %bb.0: # %entry
409 ; RV64-NEXT: addi a2, a0, -4
410 ; RV64-NEXT: slt a0, a2, a0
411 ; RV64-NEXT: xori a0, a0, 1
412 ; RV64-NEXT: sd a2, 0(a1)
413 ; RV64-NEXT: ret
414 ;
415 ; RV32ZBA-LABEL: saddo3.i64:
416 ; RV32ZBA: # %bb.0: # %entry
417 ; RV32ZBA-NEXT: addi a3, a0, -4
418 ; RV32ZBA-NEXT: sltu a0, a3, a0
419 ; RV32ZBA-NEXT: add a0, a1, a0
420 ; RV32ZBA-NEXT: addi a4, a0, -1
421 ; RV32ZBA-NEXT: xor a0, a1, a4
422 ; RV32ZBA-NEXT: and a0, a1, a0
423 ; RV32ZBA-NEXT: slti a0, a0, 0
424 ; RV32ZBA-NEXT: sw a3, 0(a2)
425 ; RV32ZBA-NEXT: sw a4, 4(a2)
426 ; RV32ZBA-NEXT: ret
427 ;
428 ; RV64ZBA-LABEL: saddo3.i64:
429 ; RV64ZBA: # %bb.0: # %entry
430 ; RV64ZBA-NEXT: addi a2, a0, -4
431 ; RV64ZBA-NEXT: slt a0, a2, a0
432 ; RV64ZBA-NEXT: xori a0, a0, 1
433 ; RV64ZBA-NEXT: sd a2, 0(a1)
434 ; RV64ZBA-NEXT: ret
435 ;
436 ; RV32ZICOND-LABEL: saddo3.i64:
437 ; RV32ZICOND: # %bb.0: # %entry
438 ; RV32ZICOND-NEXT: addi a3, a0, -4
439 ; RV32ZICOND-NEXT: sltu a0, a3, a0
440 ; RV32ZICOND-NEXT: add a0, a1, a0
441 ; RV32ZICOND-NEXT: addi a4, a0, -1
442 ; RV32ZICOND-NEXT: xor a0, a1, a4
443 ; RV32ZICOND-NEXT: and a0, a1, a0
444 ; RV32ZICOND-NEXT: slti a0, a0, 0
445 ; RV32ZICOND-NEXT: sw a3, 0(a2)
446 ; RV32ZICOND-NEXT: sw a4, 4(a2)
447 ; RV32ZICOND-NEXT: ret
448 ;
449 ; RV64ZICOND-LABEL: saddo3.i64:
450 ; RV64ZICOND: # %bb.0: # %entry
451 ; RV64ZICOND-NEXT: addi a2, a0, -4
452 ; RV64ZICOND-NEXT: slt a0, a2, a0
453 ; RV64ZICOND-NEXT: xori a0, a0, 1
454 ; RV64ZICOND-NEXT: sd a2, 0(a1)
455 ; RV64ZICOND-NEXT: ret
456 entry:
457 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 -4)
458 %val = extractvalue {i64, i1} %t, 0
459 %obit = extractvalue {i64, i1} %t, 1
460 store i64 %val, ptr %res
461 ret i1 %obit
462 }
464 define zeroext i1 @uaddo.i32(i32 signext %v1, i32 signext %v2, ptr %res) {
465 ; RV32-LABEL: uaddo.i32:
466 ; RV32: # %bb.0: # %entry
467 ; RV32-NEXT: add a1, a0, a1
468 ; RV32-NEXT: sltu a0, a1, a0
469 ; RV32-NEXT: sw a1, 0(a2)
470 ; RV32-NEXT: ret
471 ;
472 ; RV64-LABEL: uaddo.i32:
473 ; RV64: # %bb.0: # %entry
474 ; RV64-NEXT: addw a1, a0, a1
475 ; RV64-NEXT: sltu a0, a1, a0
476 ; RV64-NEXT: sw a1, 0(a2)
477 ; RV64-NEXT: ret
478 ;
479 ; RV32ZBA-LABEL: uaddo.i32:
480 ; RV32ZBA: # %bb.0: # %entry
481 ; RV32ZBA-NEXT: add a1, a0, a1
482 ; RV32ZBA-NEXT: sltu a0, a1, a0
483 ; RV32ZBA-NEXT: sw a1, 0(a2)
484 ; RV32ZBA-NEXT: ret
485 ;
486 ; RV64ZBA-LABEL: uaddo.i32:
487 ; RV64ZBA: # %bb.0: # %entry
488 ; RV64ZBA-NEXT: addw a1, a0, a1
489 ; RV64ZBA-NEXT: sltu a0, a1, a0
490 ; RV64ZBA-NEXT: sw a1, 0(a2)
491 ; RV64ZBA-NEXT: ret
492 ;
493 ; RV32ZICOND-LABEL: uaddo.i32:
494 ; RV32ZICOND: # %bb.0: # %entry
495 ; RV32ZICOND-NEXT: add a1, a0, a1
496 ; RV32ZICOND-NEXT: sltu a0, a1, a0
497 ; RV32ZICOND-NEXT: sw a1, 0(a2)
498 ; RV32ZICOND-NEXT: ret
499 ;
500 ; RV64ZICOND-LABEL: uaddo.i32:
501 ; RV64ZICOND: # %bb.0: # %entry
502 ; RV64ZICOND-NEXT: addw a1, a0, a1
503 ; RV64ZICOND-NEXT: sltu a0, a1, a0
504 ; RV64ZICOND-NEXT: sw a1, 0(a2)
505 ; RV64ZICOND-NEXT: ret
506 entry:
507 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
508 %val = extractvalue {i32, i1} %t, 0
509 %obit = extractvalue {i32, i1} %t, 1
510 store i32 %val, ptr %res
511 ret i1 %obit
512 }
514 define zeroext i1 @uaddo.i32.constant(i32 signext %v1, ptr %res) {
515 ; RV32-LABEL: uaddo.i32.constant:
516 ; RV32: # %bb.0: # %entry
517 ; RV32-NEXT: addi a2, a0, -2
518 ; RV32-NEXT: sltu a0, a2, a0
519 ; RV32-NEXT: sw a2, 0(a1)
520 ; RV32-NEXT: ret
521 ;
522 ; RV64-LABEL: uaddo.i32.constant:
523 ; RV64: # %bb.0: # %entry
524 ; RV64-NEXT: addiw a2, a0, -2
525 ; RV64-NEXT: sltu a0, a2, a0
526 ; RV64-NEXT: sw a2, 0(a1)
527 ; RV64-NEXT: ret
528 ;
529 ; RV32ZBA-LABEL: uaddo.i32.constant:
530 ; RV32ZBA: # %bb.0: # %entry
531 ; RV32ZBA-NEXT: addi a2, a0, -2
532 ; RV32ZBA-NEXT: sltu a0, a2, a0
533 ; RV32ZBA-NEXT: sw a2, 0(a1)
534 ; RV32ZBA-NEXT: ret
535 ;
536 ; RV64ZBA-LABEL: uaddo.i32.constant:
537 ; RV64ZBA: # %bb.0: # %entry
538 ; RV64ZBA-NEXT: addiw a2, a0, -2
539 ; RV64ZBA-NEXT: sltu a0, a2, a0
540 ; RV64ZBA-NEXT: sw a2, 0(a1)
541 ; RV64ZBA-NEXT: ret
542 ;
543 ; RV32ZICOND-LABEL: uaddo.i32.constant:
544 ; RV32ZICOND: # %bb.0: # %entry
545 ; RV32ZICOND-NEXT: addi a2, a0, -2
546 ; RV32ZICOND-NEXT: sltu a0, a2, a0
547 ; RV32ZICOND-NEXT: sw a2, 0(a1)
548 ; RV32ZICOND-NEXT: ret
549 ;
550 ; RV64ZICOND-LABEL: uaddo.i32.constant:
551 ; RV64ZICOND: # %bb.0: # %entry
552 ; RV64ZICOND-NEXT: addiw a2, a0, -2
553 ; RV64ZICOND-NEXT: sltu a0, a2, a0
554 ; RV64ZICOND-NEXT: sw a2, 0(a1)
555 ; RV64ZICOND-NEXT: ret
556 entry:
557 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 -2)
558 %val = extractvalue {i32, i1} %t, 0
559 %obit = extractvalue {i32, i1} %t, 1
560 store i32 %val, ptr %res
561 ret i1 %obit
562 }
564 define zeroext i1 @uaddo.i32.constant_one(i32 signext %v1, ptr %res) {
565 ; RV32-LABEL: uaddo.i32.constant_one:
566 ; RV32: # %bb.0: # %entry
567 ; RV32-NEXT: addi a2, a0, 1
568 ; RV32-NEXT: seqz a0, a2
569 ; RV32-NEXT: sw a2, 0(a1)
570 ; RV32-NEXT: ret
571 ;
572 ; RV64-LABEL: uaddo.i32.constant_one:
573 ; RV64: # %bb.0: # %entry
574 ; RV64-NEXT: addiw a2, a0, 1
575 ; RV64-NEXT: seqz a0, a2
576 ; RV64-NEXT: sw a2, 0(a1)
577 ; RV64-NEXT: ret
578 ;
579 ; RV32ZBA-LABEL: uaddo.i32.constant_one:
580 ; RV32ZBA: # %bb.0: # %entry
581 ; RV32ZBA-NEXT: addi a2, a0, 1
582 ; RV32ZBA-NEXT: seqz a0, a2
583 ; RV32ZBA-NEXT: sw a2, 0(a1)
584 ; RV32ZBA-NEXT: ret
585 ;
586 ; RV64ZBA-LABEL: uaddo.i32.constant_one:
587 ; RV64ZBA: # %bb.0: # %entry
588 ; RV64ZBA-NEXT: addiw a2, a0, 1
589 ; RV64ZBA-NEXT: seqz a0, a2
590 ; RV64ZBA-NEXT: sw a2, 0(a1)
591 ; RV64ZBA-NEXT: ret
592 ;
593 ; RV32ZICOND-LABEL: uaddo.i32.constant_one:
594 ; RV32ZICOND: # %bb.0: # %entry
595 ; RV32ZICOND-NEXT: addi a2, a0, 1
596 ; RV32ZICOND-NEXT: seqz a0, a2
597 ; RV32ZICOND-NEXT: sw a2, 0(a1)
598 ; RV32ZICOND-NEXT: ret
599 ;
600 ; RV64ZICOND-LABEL: uaddo.i32.constant_one:
601 ; RV64ZICOND: # %bb.0: # %entry
602 ; RV64ZICOND-NEXT: addiw a2, a0, 1
603 ; RV64ZICOND-NEXT: seqz a0, a2
604 ; RV64ZICOND-NEXT: sw a2, 0(a1)
605 ; RV64ZICOND-NEXT: ret
606 entry:
607 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 1)
608 %val = extractvalue {i32, i1} %t, 0
609 %obit = extractvalue {i32, i1} %t, 1
610 store i32 %val, ptr %res
611 ret i1 %obit
612 }
614 define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, ptr %res) {
615 ; RV32-LABEL: uaddo.i64:
616 ; RV32: # %bb.0: # %entry
617 ; RV32-NEXT: add a3, a1, a3
618 ; RV32-NEXT: add a2, a0, a2
619 ; RV32-NEXT: sltu a0, a2, a0
620 ; RV32-NEXT: add a3, a3, a0
621 ; RV32-NEXT: beq a3, a1, .LBB10_2
622 ; RV32-NEXT: # %bb.1: # %entry
623 ; RV32-NEXT: sltu a0, a3, a1
624 ; RV32-NEXT: .LBB10_2: # %entry
625 ; RV32-NEXT: sw a2, 0(a4)
626 ; RV32-NEXT: sw a3, 4(a4)
627 ; RV32-NEXT: ret
628 ;
629 ; RV64-LABEL: uaddo.i64:
630 ; RV64: # %bb.0: # %entry
631 ; RV64-NEXT: add a1, a0, a1
632 ; RV64-NEXT: sltu a0, a1, a0
633 ; RV64-NEXT: sd a1, 0(a2)
634 ; RV64-NEXT: ret
635 ;
636 ; RV32ZBA-LABEL: uaddo.i64:
637 ; RV32ZBA: # %bb.0: # %entry
638 ; RV32ZBA-NEXT: add a3, a1, a3
639 ; RV32ZBA-NEXT: add a2, a0, a2
640 ; RV32ZBA-NEXT: sltu a0, a2, a0
641 ; RV32ZBA-NEXT: add a3, a3, a0
642 ; RV32ZBA-NEXT: beq a3, a1, .LBB10_2
643 ; RV32ZBA-NEXT: # %bb.1: # %entry
644 ; RV32ZBA-NEXT: sltu a0, a3, a1
645 ; RV32ZBA-NEXT: .LBB10_2: # %entry
646 ; RV32ZBA-NEXT: sw a2, 0(a4)
647 ; RV32ZBA-NEXT: sw a3, 4(a4)
648 ; RV32ZBA-NEXT: ret
649 ;
650 ; RV64ZBA-LABEL: uaddo.i64:
651 ; RV64ZBA: # %bb.0: # %entry
652 ; RV64ZBA-NEXT: add a1, a0, a1
653 ; RV64ZBA-NEXT: sltu a0, a1, a0
654 ; RV64ZBA-NEXT: sd a1, 0(a2)
655 ; RV64ZBA-NEXT: ret
656 ;
657 ; RV32ZICOND-LABEL: uaddo.i64:
658 ; RV32ZICOND: # %bb.0: # %entry
659 ; RV32ZICOND-NEXT: add a3, a1, a3
660 ; RV32ZICOND-NEXT: add a2, a0, a2
661 ; RV32ZICOND-NEXT: sltu a0, a2, a0
662 ; RV32ZICOND-NEXT: add a3, a3, a0
663 ; RV32ZICOND-NEXT: xor a5, a3, a1
664 ; RV32ZICOND-NEXT: sltu a1, a3, a1
665 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a5
666 ; RV32ZICOND-NEXT: czero.nez a0, a0, a5
667 ; RV32ZICOND-NEXT: or a0, a0, a1
668 ; RV32ZICOND-NEXT: sw a2, 0(a4)
669 ; RV32ZICOND-NEXT: sw a3, 4(a4)
670 ; RV32ZICOND-NEXT: ret
671 ;
672 ; RV64ZICOND-LABEL: uaddo.i64:
673 ; RV64ZICOND: # %bb.0: # %entry
674 ; RV64ZICOND-NEXT: add a1, a0, a1
675 ; RV64ZICOND-NEXT: sltu a0, a1, a0
676 ; RV64ZICOND-NEXT: sd a1, 0(a2)
677 ; RV64ZICOND-NEXT: ret
678 entry:
679 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
680 %val = extractvalue {i64, i1} %t, 0
681 %obit = extractvalue {i64, i1} %t, 1
682 store i64 %val, ptr %res
683 ret i1 %obit
684 }
686 define zeroext i1 @uaddo.i64.constant_one(i64 %v1, ptr %res) {
687 ; RV32-LABEL: uaddo.i64.constant_one:
688 ; RV32: # %bb.0: # %entry
689 ; RV32-NEXT: addi a3, a0, 1
690 ; RV32-NEXT: seqz a0, a3
691 ; RV32-NEXT: add a1, a1, a0
692 ; RV32-NEXT: or a0, a3, a1
693 ; RV32-NEXT: seqz a0, a0
694 ; RV32-NEXT: sw a3, 0(a2)
695 ; RV32-NEXT: sw a1, 4(a2)
696 ; RV32-NEXT: ret
697 ;
698 ; RV64-LABEL: uaddo.i64.constant_one:
699 ; RV64: # %bb.0: # %entry
700 ; RV64-NEXT: addi a2, a0, 1
701 ; RV64-NEXT: seqz a0, a2
702 ; RV64-NEXT: sd a2, 0(a1)
703 ; RV64-NEXT: ret
704 ;
705 ; RV32ZBA-LABEL: uaddo.i64.constant_one:
706 ; RV32ZBA: # %bb.0: # %entry
707 ; RV32ZBA-NEXT: addi a3, a0, 1
708 ; RV32ZBA-NEXT: seqz a0, a3
709 ; RV32ZBA-NEXT: add a1, a1, a0
710 ; RV32ZBA-NEXT: or a0, a3, a1
711 ; RV32ZBA-NEXT: seqz a0, a0
712 ; RV32ZBA-NEXT: sw a3, 0(a2)
713 ; RV32ZBA-NEXT: sw a1, 4(a2)
714 ; RV32ZBA-NEXT: ret
715 ;
716 ; RV64ZBA-LABEL: uaddo.i64.constant_one:
717 ; RV64ZBA: # %bb.0: # %entry
718 ; RV64ZBA-NEXT: addi a2, a0, 1
719 ; RV64ZBA-NEXT: seqz a0, a2
720 ; RV64ZBA-NEXT: sd a2, 0(a1)
721 ; RV64ZBA-NEXT: ret
722 ;
723 ; RV32ZICOND-LABEL: uaddo.i64.constant_one:
724 ; RV32ZICOND: # %bb.0: # %entry
725 ; RV32ZICOND-NEXT: addi a3, a0, 1
726 ; RV32ZICOND-NEXT: seqz a0, a3
727 ; RV32ZICOND-NEXT: add a1, a1, a0
728 ; RV32ZICOND-NEXT: or a0, a3, a1
729 ; RV32ZICOND-NEXT: seqz a0, a0
730 ; RV32ZICOND-NEXT: sw a3, 0(a2)
731 ; RV32ZICOND-NEXT: sw a1, 4(a2)
732 ; RV32ZICOND-NEXT: ret
733 ;
734 ; RV64ZICOND-LABEL: uaddo.i64.constant_one:
735 ; RV64ZICOND: # %bb.0: # %entry
736 ; RV64ZICOND-NEXT: addi a2, a0, 1
737 ; RV64ZICOND-NEXT: seqz a0, a2
738 ; RV64ZICOND-NEXT: sd a2, 0(a1)
739 ; RV64ZICOND-NEXT: ret
740 entry:
741 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 1)
742 %val = extractvalue {i64, i1} %t, 0
743 %obit = extractvalue {i64, i1} %t, 1
744 store i64 %val, ptr %res
745 ret i1 %obit
746 }
748 define zeroext i1 @ssubo1.i32(i32 signext %v1, i32 signext %v2, ptr %res) {
749 ; RV32-LABEL: ssubo1.i32:
750 ; RV32: # %bb.0: # %entry
751 ; RV32-NEXT: sgtz a3, a1
752 ; RV32-NEXT: sub a1, a0, a1
753 ; RV32-NEXT: slt a0, a1, a0
754 ; RV32-NEXT: xor a0, a3, a0
755 ; RV32-NEXT: sw a1, 0(a2)
756 ; RV32-NEXT: ret
757 ;
758 ; RV64-LABEL: ssubo1.i32:
759 ; RV64: # %bb.0: # %entry
760 ; RV64-NEXT: sub a3, a0, a1
761 ; RV64-NEXT: subw a0, a0, a1
762 ; RV64-NEXT: xor a0, a0, a3
763 ; RV64-NEXT: snez a0, a0
764 ; RV64-NEXT: sw a3, 0(a2)
765 ; RV64-NEXT: ret
766 ;
767 ; RV32ZBA-LABEL: ssubo1.i32:
768 ; RV32ZBA: # %bb.0: # %entry
769 ; RV32ZBA-NEXT: sgtz a3, a1
770 ; RV32ZBA-NEXT: sub a1, a0, a1
771 ; RV32ZBA-NEXT: slt a0, a1, a0
772 ; RV32ZBA-NEXT: xor a0, a3, a0
773 ; RV32ZBA-NEXT: sw a1, 0(a2)
774 ; RV32ZBA-NEXT: ret
775 ;
776 ; RV64ZBA-LABEL: ssubo1.i32:
777 ; RV64ZBA: # %bb.0: # %entry
778 ; RV64ZBA-NEXT: sub a3, a0, a1
779 ; RV64ZBA-NEXT: subw a0, a0, a1
780 ; RV64ZBA-NEXT: xor a0, a0, a3
781 ; RV64ZBA-NEXT: snez a0, a0
782 ; RV64ZBA-NEXT: sw a3, 0(a2)
783 ; RV64ZBA-NEXT: ret
784 ;
785 ; RV32ZICOND-LABEL: ssubo1.i32:
786 ; RV32ZICOND: # %bb.0: # %entry
787 ; RV32ZICOND-NEXT: sgtz a3, a1
788 ; RV32ZICOND-NEXT: sub a1, a0, a1
789 ; RV32ZICOND-NEXT: slt a0, a1, a0
790 ; RV32ZICOND-NEXT: xor a0, a3, a0
791 ; RV32ZICOND-NEXT: sw a1, 0(a2)
792 ; RV32ZICOND-NEXT: ret
793 ;
794 ; RV64ZICOND-LABEL: ssubo1.i32:
795 ; RV64ZICOND: # %bb.0: # %entry
796 ; RV64ZICOND-NEXT: sub a3, a0, a1
797 ; RV64ZICOND-NEXT: subw a0, a0, a1
798 ; RV64ZICOND-NEXT: xor a0, a0, a3
799 ; RV64ZICOND-NEXT: snez a0, a0
800 ; RV64ZICOND-NEXT: sw a3, 0(a2)
801 ; RV64ZICOND-NEXT: ret
802 entry:
803 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
804 %val = extractvalue {i32, i1} %t, 0
805 %obit = extractvalue {i32, i1} %t, 1
806 store i32 %val, ptr %res
807 ret i1 %obit
808 }
810 define zeroext i1 @ssubo2.i32(i32 signext %v1, ptr %res) {
811 ; RV32-LABEL: ssubo2.i32:
812 ; RV32: # %bb.0: # %entry
813 ; RV32-NEXT: addi a2, a0, 4
814 ; RV32-NEXT: slt a0, a2, a0
815 ; RV32-NEXT: sw a2, 0(a1)
816 ; RV32-NEXT: ret
817 ;
818 ; RV64-LABEL: ssubo2.i32:
819 ; RV64: # %bb.0: # %entry
820 ; RV64-NEXT: addiw a2, a0, 4
821 ; RV64-NEXT: slt a0, a2, a0
822 ; RV64-NEXT: sw a2, 0(a1)
823 ; RV64-NEXT: ret
824 ;
825 ; RV32ZBA-LABEL: ssubo2.i32:
826 ; RV32ZBA: # %bb.0: # %entry
827 ; RV32ZBA-NEXT: addi a2, a0, 4
828 ; RV32ZBA-NEXT: slt a0, a2, a0
829 ; RV32ZBA-NEXT: sw a2, 0(a1)
830 ; RV32ZBA-NEXT: ret
831 ;
832 ; RV64ZBA-LABEL: ssubo2.i32:
833 ; RV64ZBA: # %bb.0: # %entry
834 ; RV64ZBA-NEXT: addiw a2, a0, 4
835 ; RV64ZBA-NEXT: slt a0, a2, a0
836 ; RV64ZBA-NEXT: sw a2, 0(a1)
837 ; RV64ZBA-NEXT: ret
838 ;
839 ; RV32ZICOND-LABEL: ssubo2.i32:
840 ; RV32ZICOND: # %bb.0: # %entry
841 ; RV32ZICOND-NEXT: addi a2, a0, 4
842 ; RV32ZICOND-NEXT: slt a0, a2, a0
843 ; RV32ZICOND-NEXT: sw a2, 0(a1)
844 ; RV32ZICOND-NEXT: ret
845 ;
846 ; RV64ZICOND-LABEL: ssubo2.i32:
847 ; RV64ZICOND: # %bb.0: # %entry
848 ; RV64ZICOND-NEXT: addiw a2, a0, 4
849 ; RV64ZICOND-NEXT: slt a0, a2, a0
850 ; RV64ZICOND-NEXT: sw a2, 0(a1)
851 ; RV64ZICOND-NEXT: ret
852 entry:
853 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 -4)
854 %val = extractvalue {i32, i1} %t, 0
855 %obit = extractvalue {i32, i1} %t, 1
856 store i32 %val, ptr %res
857 ret i1 %obit
858 }
860 define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, ptr %res) {
861 ; RV32-LABEL: ssubo.i64:
862 ; RV32: # %bb.0: # %entry
863 ; RV32-NEXT: sltu a5, a0, a2
864 ; RV32-NEXT: sub a6, a1, a3
865 ; RV32-NEXT: sub a5, a6, a5
866 ; RV32-NEXT: xor a6, a1, a5
867 ; RV32-NEXT: xor a1, a1, a3
868 ; RV32-NEXT: and a1, a1, a6
869 ; RV32-NEXT: slti a1, a1, 0
870 ; RV32-NEXT: sub a0, a0, a2
871 ; RV32-NEXT: sw a0, 0(a4)
872 ; RV32-NEXT: sw a5, 4(a4)
873 ; RV32-NEXT: mv a0, a1
874 ; RV32-NEXT: ret
875 ;
876 ; RV64-LABEL: ssubo.i64:
877 ; RV64: # %bb.0: # %entry
878 ; RV64-NEXT: sgtz a3, a1
879 ; RV64-NEXT: sub a1, a0, a1
880 ; RV64-NEXT: slt a0, a1, a0
881 ; RV64-NEXT: xor a0, a3, a0
882 ; RV64-NEXT: sd a1, 0(a2)
883 ; RV64-NEXT: ret
884 ;
885 ; RV32ZBA-LABEL: ssubo.i64:
886 ; RV32ZBA: # %bb.0: # %entry
887 ; RV32ZBA-NEXT: sltu a5, a0, a2
888 ; RV32ZBA-NEXT: sub a6, a1, a3
889 ; RV32ZBA-NEXT: sub a5, a6, a5
890 ; RV32ZBA-NEXT: xor a6, a1, a5
891 ; RV32ZBA-NEXT: xor a1, a1, a3
892 ; RV32ZBA-NEXT: and a1, a1, a6
893 ; RV32ZBA-NEXT: slti a1, a1, 0
894 ; RV32ZBA-NEXT: sub a0, a0, a2
895 ; RV32ZBA-NEXT: sw a0, 0(a4)
896 ; RV32ZBA-NEXT: sw a5, 4(a4)
897 ; RV32ZBA-NEXT: mv a0, a1
898 ; RV32ZBA-NEXT: ret
899 ;
900 ; RV64ZBA-LABEL: ssubo.i64:
901 ; RV64ZBA: # %bb.0: # %entry
902 ; RV64ZBA-NEXT: sgtz a3, a1
903 ; RV64ZBA-NEXT: sub a1, a0, a1
904 ; RV64ZBA-NEXT: slt a0, a1, a0
905 ; RV64ZBA-NEXT: xor a0, a3, a0
906 ; RV64ZBA-NEXT: sd a1, 0(a2)
907 ; RV64ZBA-NEXT: ret
908 ;
909 ; RV32ZICOND-LABEL: ssubo.i64:
910 ; RV32ZICOND: # %bb.0: # %entry
911 ; RV32ZICOND-NEXT: sltu a5, a0, a2
912 ; RV32ZICOND-NEXT: sub a6, a1, a3
913 ; RV32ZICOND-NEXT: sub a5, a6, a5
914 ; RV32ZICOND-NEXT: xor a6, a1, a5
915 ; RV32ZICOND-NEXT: xor a1, a1, a3
916 ; RV32ZICOND-NEXT: and a1, a1, a6
917 ; RV32ZICOND-NEXT: slti a1, a1, 0
918 ; RV32ZICOND-NEXT: sub a0, a0, a2
919 ; RV32ZICOND-NEXT: sw a0, 0(a4)
920 ; RV32ZICOND-NEXT: sw a5, 4(a4)
921 ; RV32ZICOND-NEXT: mv a0, a1
922 ; RV32ZICOND-NEXT: ret
923 ;
924 ; RV64ZICOND-LABEL: ssubo.i64:
925 ; RV64ZICOND: # %bb.0: # %entry
926 ; RV64ZICOND-NEXT: sgtz a3, a1
927 ; RV64ZICOND-NEXT: sub a1, a0, a1
928 ; RV64ZICOND-NEXT: slt a0, a1, a0
929 ; RV64ZICOND-NEXT: xor a0, a3, a0
930 ; RV64ZICOND-NEXT: sd a1, 0(a2)
931 ; RV64ZICOND-NEXT: ret
932 entry:
933 %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
934 %val = extractvalue {i64, i1} %t, 0
935 %obit = extractvalue {i64, i1} %t, 1
936 store i64 %val, ptr %res
937 ret i1 %obit
938 }
940 define zeroext i1 @usubo.i32(i32 signext %v1, i32 signext %v2, ptr %res) {
941 ; RV32-LABEL: usubo.i32:
942 ; RV32: # %bb.0: # %entry
943 ; RV32-NEXT: sub a1, a0, a1
944 ; RV32-NEXT: sltu a0, a0, a1
945 ; RV32-NEXT: sw a1, 0(a2)
946 ; RV32-NEXT: ret
947 ;
948 ; RV64-LABEL: usubo.i32:
949 ; RV64: # %bb.0: # %entry
950 ; RV64-NEXT: subw a1, a0, a1
951 ; RV64-NEXT: sltu a0, a0, a1
952 ; RV64-NEXT: sw a1, 0(a2)
953 ; RV64-NEXT: ret
954 ;
955 ; RV32ZBA-LABEL: usubo.i32:
956 ; RV32ZBA: # %bb.0: # %entry
957 ; RV32ZBA-NEXT: sub a1, a0, a1
958 ; RV32ZBA-NEXT: sltu a0, a0, a1
959 ; RV32ZBA-NEXT: sw a1, 0(a2)
960 ; RV32ZBA-NEXT: ret
961 ;
962 ; RV64ZBA-LABEL: usubo.i32:
963 ; RV64ZBA: # %bb.0: # %entry
964 ; RV64ZBA-NEXT: subw a1, a0, a1
965 ; RV64ZBA-NEXT: sltu a0, a0, a1
966 ; RV64ZBA-NEXT: sw a1, 0(a2)
967 ; RV64ZBA-NEXT: ret
968 ;
969 ; RV32ZICOND-LABEL: usubo.i32:
970 ; RV32ZICOND: # %bb.0: # %entry
971 ; RV32ZICOND-NEXT: sub a1, a0, a1
972 ; RV32ZICOND-NEXT: sltu a0, a0, a1
973 ; RV32ZICOND-NEXT: sw a1, 0(a2)
974 ; RV32ZICOND-NEXT: ret
975 ;
976 ; RV64ZICOND-LABEL: usubo.i32:
977 ; RV64ZICOND: # %bb.0: # %entry
978 ; RV64ZICOND-NEXT: subw a1, a0, a1
979 ; RV64ZICOND-NEXT: sltu a0, a0, a1
980 ; RV64ZICOND-NEXT: sw a1, 0(a2)
981 ; RV64ZICOND-NEXT: ret
982 entry:
983 %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
984 %val = extractvalue {i32, i1} %t, 0
985 %obit = extractvalue {i32, i1} %t, 1
986 store i32 %val, ptr %res
987 ret i1 %obit
988 }
990 define zeroext i1 @usubo.i32.constant.rhs(i32 signext %v1, ptr %res) {
991 ; RV32-LABEL: usubo.i32.constant.rhs:
992 ; RV32: # %bb.0: # %entry
993 ; RV32-NEXT: addi a2, a0, 2
994 ; RV32-NEXT: sltu a0, a0, a2
995 ; RV32-NEXT: sw a2, 0(a1)
996 ; RV32-NEXT: ret
997 ;
998 ; RV64-LABEL: usubo.i32.constant.rhs:
999 ; RV64: # %bb.0: # %entry
1000 ; RV64-NEXT: addiw a2, a0, 2
1001 ; RV64-NEXT: sltu a0, a0, a2
1002 ; RV64-NEXT: sw a2, 0(a1)
1003 ; RV64-NEXT: ret
1004 ;
1005 ; RV32ZBA-LABEL: usubo.i32.constant.rhs:
1006 ; RV32ZBA: # %bb.0: # %entry
1007 ; RV32ZBA-NEXT: addi a2, a0, 2
1008 ; RV32ZBA-NEXT: sltu a0, a0, a2
1009 ; RV32ZBA-NEXT: sw a2, 0(a1)
1010 ; RV32ZBA-NEXT: ret
1011 ;
1012 ; RV64ZBA-LABEL: usubo.i32.constant.rhs:
1013 ; RV64ZBA: # %bb.0: # %entry
1014 ; RV64ZBA-NEXT: addiw a2, a0, 2
1015 ; RV64ZBA-NEXT: sltu a0, a0, a2
1016 ; RV64ZBA-NEXT: sw a2, 0(a1)
1017 ; RV64ZBA-NEXT: ret
1018 ;
1019 ; RV32ZICOND-LABEL: usubo.i32.constant.rhs:
1020 ; RV32ZICOND: # %bb.0: # %entry
1021 ; RV32ZICOND-NEXT: addi a2, a0, 2
1022 ; RV32ZICOND-NEXT: sltu a0, a0, a2
1023 ; RV32ZICOND-NEXT: sw a2, 0(a1)
1024 ; RV32ZICOND-NEXT: ret
1025 ;
1026 ; RV64ZICOND-LABEL: usubo.i32.constant.rhs:
1027 ; RV64ZICOND: # %bb.0: # %entry
1028 ; RV64ZICOND-NEXT: addiw a2, a0, 2
1029 ; RV64ZICOND-NEXT: sltu a0, a0, a2
1030 ; RV64ZICOND-NEXT: sw a2, 0(a1)
1031 ; RV64ZICOND-NEXT: ret
1032 entry:
1033 %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 -2)
1034 %val = extractvalue {i32, i1} %t, 0
1035 %obit = extractvalue {i32, i1} %t, 1
1036 store i32 %val, ptr %res
1037 ret i1 %obit
1038 }
1040 define zeroext i1 @usubo.i32.constant.lhs(i32 signext %v1, ptr %res) {
1041 ; RV32-LABEL: usubo.i32.constant.lhs:
1042 ; RV32: # %bb.0: # %entry
1043 ; RV32-NEXT: li a2, -2
1044 ; RV32-NEXT: sub a2, a2, a0
1045 ; RV32-NEXT: addi a0, a2, 1
1046 ; RV32-NEXT: seqz a0, a0
1047 ; RV32-NEXT: sw a2, 0(a1)
1048 ; RV32-NEXT: ret
1049 ;
1050 ; RV64-LABEL: usubo.i32.constant.lhs:
1051 ; RV64: # %bb.0: # %entry
1052 ; RV64-NEXT: li a2, -2
1053 ; RV64-NEXT: subw a2, a2, a0
1054 ; RV64-NEXT: addi a0, a2, 1
1055 ; RV64-NEXT: seqz a0, a0
1056 ; RV64-NEXT: sw a2, 0(a1)
1057 ; RV64-NEXT: ret
1058 ;
1059 ; RV32ZBA-LABEL: usubo.i32.constant.lhs:
1060 ; RV32ZBA: # %bb.0: # %entry
1061 ; RV32ZBA-NEXT: li a2, -2
1062 ; RV32ZBA-NEXT: sub a2, a2, a0
1063 ; RV32ZBA-NEXT: addi a0, a2, 1
1064 ; RV32ZBA-NEXT: seqz a0, a0
1065 ; RV32ZBA-NEXT: sw a2, 0(a1)
1066 ; RV32ZBA-NEXT: ret
1067 ;
1068 ; RV64ZBA-LABEL: usubo.i32.constant.lhs:
1069 ; RV64ZBA: # %bb.0: # %entry
1070 ; RV64ZBA-NEXT: li a2, -2
1071 ; RV64ZBA-NEXT: subw a2, a2, a0
1072 ; RV64ZBA-NEXT: addi a0, a2, 1
1073 ; RV64ZBA-NEXT: seqz a0, a0
1074 ; RV64ZBA-NEXT: sw a2, 0(a1)
1075 ; RV64ZBA-NEXT: ret
1076 ;
1077 ; RV32ZICOND-LABEL: usubo.i32.constant.lhs:
1078 ; RV32ZICOND: # %bb.0: # %entry
1079 ; RV32ZICOND-NEXT: li a2, -2
1080 ; RV32ZICOND-NEXT: sub a2, a2, a0
1081 ; RV32ZICOND-NEXT: addi a0, a2, 1
1082 ; RV32ZICOND-NEXT: seqz a0, a0
1083 ; RV32ZICOND-NEXT: sw a2, 0(a1)
1084 ; RV32ZICOND-NEXT: ret
1085 ;
1086 ; RV64ZICOND-LABEL: usubo.i32.constant.lhs:
1087 ; RV64ZICOND: # %bb.0: # %entry
1088 ; RV64ZICOND-NEXT: li a2, -2
1089 ; RV64ZICOND-NEXT: subw a2, a2, a0
1090 ; RV64ZICOND-NEXT: addi a0, a2, 1
1091 ; RV64ZICOND-NEXT: seqz a0, a0
1092 ; RV64ZICOND-NEXT: sw a2, 0(a1)
1093 ; RV64ZICOND-NEXT: ret
1094 entry:
1095 %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 -2, i32 %v1)
1096 %val = extractvalue {i32, i1} %t, 0
1097 %obit = extractvalue {i32, i1} %t, 1
1098 store i32 %val, ptr %res
1099 ret i1 %obit
1100 }
1102 define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, ptr %res) {
1103 ; RV32-LABEL: usubo.i64:
1104 ; RV32: # %bb.0: # %entry
1105 ; RV32-NEXT: sltu a5, a0, a2
1106 ; RV32-NEXT: sub a3, a1, a3
1107 ; RV32-NEXT: sub a3, a3, a5
1108 ; RV32-NEXT: sub a2, a0, a2
1109 ; RV32-NEXT: beq a3, a1, .LBB18_2
1110 ; RV32-NEXT: # %bb.1: # %entry
1111 ; RV32-NEXT: sltu a0, a1, a3
1112 ; RV32-NEXT: j .LBB18_3
1113 ; RV32-NEXT: .LBB18_2:
1114 ; RV32-NEXT: sltu a0, a0, a2
1115 ; RV32-NEXT: .LBB18_3: # %entry
1116 ; RV32-NEXT: sw a2, 0(a4)
1117 ; RV32-NEXT: sw a3, 4(a4)
1118 ; RV32-NEXT: ret
1119 ;
1120 ; RV64-LABEL: usubo.i64:
1121 ; RV64: # %bb.0: # %entry
1122 ; RV64-NEXT: sub a1, a0, a1
1123 ; RV64-NEXT: sltu a0, a0, a1
1124 ; RV64-NEXT: sd a1, 0(a2)
1125 ; RV64-NEXT: ret
1126 ;
1127 ; RV32ZBA-LABEL: usubo.i64:
1128 ; RV32ZBA: # %bb.0: # %entry
1129 ; RV32ZBA-NEXT: sltu a5, a0, a2
1130 ; RV32ZBA-NEXT: sub a3, a1, a3
1131 ; RV32ZBA-NEXT: sub a3, a3, a5
1132 ; RV32ZBA-NEXT: sub a2, a0, a2
1133 ; RV32ZBA-NEXT: beq a3, a1, .LBB18_2
1134 ; RV32ZBA-NEXT: # %bb.1: # %entry
1135 ; RV32ZBA-NEXT: sltu a0, a1, a3
1136 ; RV32ZBA-NEXT: j .LBB18_3
1137 ; RV32ZBA-NEXT: .LBB18_2:
1138 ; RV32ZBA-NEXT: sltu a0, a0, a2
1139 ; RV32ZBA-NEXT: .LBB18_3: # %entry
1140 ; RV32ZBA-NEXT: sw a2, 0(a4)
1141 ; RV32ZBA-NEXT: sw a3, 4(a4)
1142 ; RV32ZBA-NEXT: ret
1143 ;
1144 ; RV64ZBA-LABEL: usubo.i64:
1145 ; RV64ZBA: # %bb.0: # %entry
1146 ; RV64ZBA-NEXT: sub a1, a0, a1
1147 ; RV64ZBA-NEXT: sltu a0, a0, a1
1148 ; RV64ZBA-NEXT: sd a1, 0(a2)
1149 ; RV64ZBA-NEXT: ret
1150 ;
1151 ; RV32ZICOND-LABEL: usubo.i64:
1152 ; RV32ZICOND: # %bb.0: # %entry
1153 ; RV32ZICOND-NEXT: sltu a5, a0, a2
1154 ; RV32ZICOND-NEXT: sub a3, a1, a3
1155 ; RV32ZICOND-NEXT: sub a3, a3, a5
1156 ; RV32ZICOND-NEXT: xor a5, a3, a1
1157 ; RV32ZICOND-NEXT: sltu a1, a1, a3
1158 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a5
1159 ; RV32ZICOND-NEXT: sub a2, a0, a2
1160 ; RV32ZICOND-NEXT: sltu a0, a0, a2
1161 ; RV32ZICOND-NEXT: czero.nez a0, a0, a5
1162 ; RV32ZICOND-NEXT: or a0, a0, a1
1163 ; RV32ZICOND-NEXT: sw a2, 0(a4)
1164 ; RV32ZICOND-NEXT: sw a3, 4(a4)
1165 ; RV32ZICOND-NEXT: ret
1166 ;
1167 ; RV64ZICOND-LABEL: usubo.i64:
1168 ; RV64ZICOND: # %bb.0: # %entry
1169 ; RV64ZICOND-NEXT: sub a1, a0, a1
1170 ; RV64ZICOND-NEXT: sltu a0, a0, a1
1171 ; RV64ZICOND-NEXT: sd a1, 0(a2)
1172 ; RV64ZICOND-NEXT: ret
1173 entry:
1174 %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
1175 %val = extractvalue {i64, i1} %t, 0
1176 %obit = extractvalue {i64, i1} %t, 1
1177 store i64 %val, ptr %res
1178 ret i1 %obit
1179 }
1181 define zeroext i1 @smulo.i32(i32 signext %v1, i32 signext %v2, ptr %res) {
1182 ; RV32-LABEL: smulo.i32:
1183 ; RV32: # %bb.0: # %entry
1184 ; RV32-NEXT: mulh a3, a0, a1
1185 ; RV32-NEXT: mul a1, a0, a1
1186 ; RV32-NEXT: srai a0, a1, 31
1187 ; RV32-NEXT: xor a0, a3, a0
1188 ; RV32-NEXT: snez a0, a0
1189 ; RV32-NEXT: sw a1, 0(a2)
1190 ; RV32-NEXT: ret
1191 ;
1192 ; RV64-LABEL: smulo.i32:
1193 ; RV64: # %bb.0: # %entry
1194 ; RV64-NEXT: mul a3, a0, a1
1195 ; RV64-NEXT: mulw a0, a0, a1
1196 ; RV64-NEXT: xor a0, a0, a3
1197 ; RV64-NEXT: snez a0, a0
1198 ; RV64-NEXT: sw a3, 0(a2)
1199 ; RV64-NEXT: ret
1200 ;
1201 ; RV32ZBA-LABEL: smulo.i32:
1202 ; RV32ZBA: # %bb.0: # %entry
1203 ; RV32ZBA-NEXT: mulh a3, a0, a1
1204 ; RV32ZBA-NEXT: mul a1, a0, a1
1205 ; RV32ZBA-NEXT: srai a0, a1, 31
1206 ; RV32ZBA-NEXT: xor a0, a3, a0
1207 ; RV32ZBA-NEXT: snez a0, a0
1208 ; RV32ZBA-NEXT: sw a1, 0(a2)
1209 ; RV32ZBA-NEXT: ret
1210 ;
1211 ; RV64ZBA-LABEL: smulo.i32:
1212 ; RV64ZBA: # %bb.0: # %entry
1213 ; RV64ZBA-NEXT: mul a3, a0, a1
1214 ; RV64ZBA-NEXT: mulw a0, a0, a1
1215 ; RV64ZBA-NEXT: xor a0, a0, a3
1216 ; RV64ZBA-NEXT: snez a0, a0
1217 ; RV64ZBA-NEXT: sw a3, 0(a2)
1218 ; RV64ZBA-NEXT: ret
1219 ;
1220 ; RV32ZICOND-LABEL: smulo.i32:
1221 ; RV32ZICOND: # %bb.0: # %entry
1222 ; RV32ZICOND-NEXT: mulh a3, a0, a1
1223 ; RV32ZICOND-NEXT: mul a1, a0, a1
1224 ; RV32ZICOND-NEXT: srai a0, a1, 31
1225 ; RV32ZICOND-NEXT: xor a0, a3, a0
1226 ; RV32ZICOND-NEXT: snez a0, a0
1227 ; RV32ZICOND-NEXT: sw a1, 0(a2)
1228 ; RV32ZICOND-NEXT: ret
1229 ;
1230 ; RV64ZICOND-LABEL: smulo.i32:
1231 ; RV64ZICOND: # %bb.0: # %entry
1232 ; RV64ZICOND-NEXT: mul a3, a0, a1
1233 ; RV64ZICOND-NEXT: mulw a0, a0, a1
1234 ; RV64ZICOND-NEXT: xor a0, a0, a3
1235 ; RV64ZICOND-NEXT: snez a0, a0
1236 ; RV64ZICOND-NEXT: sw a3, 0(a2)
1237 ; RV64ZICOND-NEXT: ret
1238 entry:
1239 %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
1240 %val = extractvalue {i32, i1} %t, 0
1241 %obit = extractvalue {i32, i1} %t, 1
1242 store i32 %val, ptr %res
1243 ret i1 %obit
1244 }
1246 define zeroext i1 @smulo2.i32(i32 signext %v1, ptr %res) {
1247 ; RV32-LABEL: smulo2.i32:
1248 ; RV32: # %bb.0: # %entry
1249 ; RV32-NEXT: li a2, 13
1250 ; RV32-NEXT: mulh a3, a0, a2
1251 ; RV32-NEXT: mul a2, a0, a2
1252 ; RV32-NEXT: srai a0, a2, 31
1253 ; RV32-NEXT: xor a0, a3, a0
1254 ; RV32-NEXT: snez a0, a0
1255 ; RV32-NEXT: sw a2, 0(a1)
1256 ; RV32-NEXT: ret
1257 ;
1258 ; RV64-LABEL: smulo2.i32:
1259 ; RV64: # %bb.0: # %entry
1260 ; RV64-NEXT: li a2, 13
1261 ; RV64-NEXT: mul a3, a0, a2
1262 ; RV64-NEXT: mulw a0, a0, a2
1263 ; RV64-NEXT: xor a0, a0, a3
1264 ; RV64-NEXT: snez a0, a0
1265 ; RV64-NEXT: sw a3, 0(a1)
1266 ; RV64-NEXT: ret
1267 ;
1268 ; RV32ZBA-LABEL: smulo2.i32:
1269 ; RV32ZBA: # %bb.0: # %entry
1270 ; RV32ZBA-NEXT: li a2, 13
1271 ; RV32ZBA-NEXT: mulh a2, a0, a2
1272 ; RV32ZBA-NEXT: sh1add a3, a0, a0
1273 ; RV32ZBA-NEXT: sh2add a3, a3, a0
1274 ; RV32ZBA-NEXT: srai a0, a3, 31
1275 ; RV32ZBA-NEXT: xor a0, a2, a0
1276 ; RV32ZBA-NEXT: snez a0, a0
1277 ; RV32ZBA-NEXT: sw a3, 0(a1)
1278 ; RV32ZBA-NEXT: ret
1279 ;
1280 ; RV64ZBA-LABEL: smulo2.i32:
1281 ; RV64ZBA: # %bb.0: # %entry
1282 ; RV64ZBA-NEXT: sh1add a2, a0, a0
1283 ; RV64ZBA-NEXT: sh2add a2, a2, a0
1284 ; RV64ZBA-NEXT: sext.w a0, a2
1285 ; RV64ZBA-NEXT: xor a0, a0, a2
1286 ; RV64ZBA-NEXT: snez a0, a0
1287 ; RV64ZBA-NEXT: sw a2, 0(a1)
1288 ; RV64ZBA-NEXT: ret
1289 ;
1290 ; RV32ZICOND-LABEL: smulo2.i32:
1291 ; RV32ZICOND: # %bb.0: # %entry
1292 ; RV32ZICOND-NEXT: li a2, 13
1293 ; RV32ZICOND-NEXT: mulh a3, a0, a2
1294 ; RV32ZICOND-NEXT: mul a2, a0, a2
1295 ; RV32ZICOND-NEXT: srai a0, a2, 31
1296 ; RV32ZICOND-NEXT: xor a0, a3, a0
1297 ; RV32ZICOND-NEXT: snez a0, a0
1298 ; RV32ZICOND-NEXT: sw a2, 0(a1)
1299 ; RV32ZICOND-NEXT: ret
1300 ;
1301 ; RV64ZICOND-LABEL: smulo2.i32:
1302 ; RV64ZICOND: # %bb.0: # %entry
1303 ; RV64ZICOND-NEXT: li a2, 13
1304 ; RV64ZICOND-NEXT: mul a3, a0, a2
1305 ; RV64ZICOND-NEXT: mulw a0, a0, a2
1306 ; RV64ZICOND-NEXT: xor a0, a0, a3
1307 ; RV64ZICOND-NEXT: snez a0, a0
1308 ; RV64ZICOND-NEXT: sw a3, 0(a1)
1309 ; RV64ZICOND-NEXT: ret
1310 entry:
1311 %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 13)
1312 %val = extractvalue {i32, i1} %t, 0
1313 %obit = extractvalue {i32, i1} %t, 1
1314 store i32 %val, ptr %res
1315 ret i1 %obit
1316 }
1318 define zeroext i1 @smulo.i64(i64 %v1, i64 %v2, ptr %res) {
1319 ; RV32-LABEL: smulo.i64:
1320 ; RV32: # %bb.0: # %entry
1321 ; RV32-NEXT: addi sp, sp, -16
1322 ; RV32-NEXT: .cfi_def_cfa_offset 16
1323 ; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
1324 ; RV32-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
1325 ; RV32-NEXT: .cfi_offset s0, -4
1326 ; RV32-NEXT: .cfi_offset s1, -8
1327 ; RV32-NEXT: mulhu a5, a0, a2
1328 ; RV32-NEXT: mul a6, a1, a2
1329 ; RV32-NEXT: add a5, a6, a5
1330 ; RV32-NEXT: sltu a6, a5, a6
1331 ; RV32-NEXT: mulhu a7, a1, a2
1332 ; RV32-NEXT: add a6, a7, a6
1333 ; RV32-NEXT: mul a7, a0, a3
1334 ; RV32-NEXT: add a5, a7, a5
1335 ; RV32-NEXT: sltu a7, a5, a7
1336 ; RV32-NEXT: mulhu t0, a0, a3
1337 ; RV32-NEXT: add a7, t0, a7
1338 ; RV32-NEXT: add a7, a6, a7
1339 ; RV32-NEXT: mul t0, a1, a3
1340 ; RV32-NEXT: add t1, t0, a7
1341 ; RV32-NEXT: srai t2, a1, 31
1342 ; RV32-NEXT: mul t3, a2, t2
1343 ; RV32-NEXT: srai t4, a3, 31
1344 ; RV32-NEXT: mul t5, t4, a0
1345 ; RV32-NEXT: add t6, t5, t3
1346 ; RV32-NEXT: add s0, t1, t6
1347 ; RV32-NEXT: sltu s1, s0, t1
1348 ; RV32-NEXT: sltu t0, t1, t0
1349 ; RV32-NEXT: sltu a6, a7, a6
1350 ; RV32-NEXT: mulhu a7, a1, a3
1351 ; RV32-NEXT: add a6, a7, a6
1352 ; RV32-NEXT: add a6, a6, t0
1353 ; RV32-NEXT: mulhu a7, a2, t2
1354 ; RV32-NEXT: add a7, a7, t3
1355 ; RV32-NEXT: mul a3, a3, t2
1356 ; RV32-NEXT: add a3, a7, a3
1357 ; RV32-NEXT: mul a1, t4, a1
1358 ; RV32-NEXT: mulhu a7, t4, a0
1359 ; RV32-NEXT: add a1, a7, a1
1360 ; RV32-NEXT: add a1, a1, t5
1361 ; RV32-NEXT: add a1, a1, a3
1362 ; RV32-NEXT: sltu a3, t6, t5
1363 ; RV32-NEXT: add a1, a1, a3
1364 ; RV32-NEXT: add a1, a6, a1
1365 ; RV32-NEXT: add a1, a1, s1
1366 ; RV32-NEXT: srai a3, a5, 31
1367 ; RV32-NEXT: xor a1, a1, a3
1368 ; RV32-NEXT: xor a3, s0, a3
1369 ; RV32-NEXT: or a1, a3, a1
1370 ; RV32-NEXT: snez a1, a1
1371 ; RV32-NEXT: mul a0, a0, a2
1372 ; RV32-NEXT: sw a0, 0(a4)
1373 ; RV32-NEXT: sw a5, 4(a4)
1374 ; RV32-NEXT: mv a0, a1
1375 ; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
1376 ; RV32-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
1377 ; RV32-NEXT: addi sp, sp, 16
1378 ; RV32-NEXT: ret
1379 ;
1380 ; RV64-LABEL: smulo.i64:
1381 ; RV64: # %bb.0: # %entry
1382 ; RV64-NEXT: mulh a3, a0, a1
1383 ; RV64-NEXT: mul a1, a0, a1
1384 ; RV64-NEXT: srai a0, a1, 63
1385 ; RV64-NEXT: xor a0, a3, a0
1386 ; RV64-NEXT: snez a0, a0
1387 ; RV64-NEXT: sd a1, 0(a2)
1388 ; RV64-NEXT: ret
1389 ;
1390 ; RV32ZBA-LABEL: smulo.i64:
1391 ; RV32ZBA: # %bb.0: # %entry
1392 ; RV32ZBA-NEXT: addi sp, sp, -16
1393 ; RV32ZBA-NEXT: .cfi_def_cfa_offset 16
1394 ; RV32ZBA-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
1395 ; RV32ZBA-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
1396 ; RV32ZBA-NEXT: .cfi_offset s0, -4
1397 ; RV32ZBA-NEXT: .cfi_offset s1, -8
1398 ; RV32ZBA-NEXT: mulhu a5, a0, a2
1399 ; RV32ZBA-NEXT: mul a6, a1, a2
1400 ; RV32ZBA-NEXT: add a5, a6, a5
1401 ; RV32ZBA-NEXT: sltu a6, a5, a6
1402 ; RV32ZBA-NEXT: mulhu a7, a1, a2
1403 ; RV32ZBA-NEXT: add a6, a7, a6
1404 ; RV32ZBA-NEXT: mul a7, a0, a3
1405 ; RV32ZBA-NEXT: add a5, a7, a5
1406 ; RV32ZBA-NEXT: sltu a7, a5, a7
1407 ; RV32ZBA-NEXT: mulhu t0, a0, a3
1408 ; RV32ZBA-NEXT: add a7, t0, a7
1409 ; RV32ZBA-NEXT: add a7, a6, a7
1410 ; RV32ZBA-NEXT: mul t0, a1, a3
1411 ; RV32ZBA-NEXT: add t1, t0, a7
1412 ; RV32ZBA-NEXT: srai t2, a1, 31
1413 ; RV32ZBA-NEXT: mul t3, a2, t2
1414 ; RV32ZBA-NEXT: srai t4, a3, 31
1415 ; RV32ZBA-NEXT: mul t5, t4, a0
1416 ; RV32ZBA-NEXT: add t6, t5, t3
1417 ; RV32ZBA-NEXT: add s0, t1, t6
1418 ; RV32ZBA-NEXT: sltu s1, s0, t1
1419 ; RV32ZBA-NEXT: sltu t0, t1, t0
1420 ; RV32ZBA-NEXT: sltu a6, a7, a6
1421 ; RV32ZBA-NEXT: mulhu a7, a1, a3
1422 ; RV32ZBA-NEXT: add a6, a7, a6
1423 ; RV32ZBA-NEXT: add a6, a6, t0
1424 ; RV32ZBA-NEXT: mulhu a7, a2, t2
1425 ; RV32ZBA-NEXT: add a7, a7, t3
1426 ; RV32ZBA-NEXT: mul a3, a3, t2
1427 ; RV32ZBA-NEXT: add a3, a7, a3
1428 ; RV32ZBA-NEXT: mul a1, t4, a1
1429 ; RV32ZBA-NEXT: mulhu a7, t4, a0
1430 ; RV32ZBA-NEXT: add a1, a7, a1
1431 ; RV32ZBA-NEXT: add a1, a1, t5
1432 ; RV32ZBA-NEXT: add a1, a1, a3
1433 ; RV32ZBA-NEXT: sltu a3, t6, t5
1434 ; RV32ZBA-NEXT: add a1, a1, a3
1435 ; RV32ZBA-NEXT: add a1, a6, a1
1436 ; RV32ZBA-NEXT: add a1, a1, s1
1437 ; RV32ZBA-NEXT: srai a3, a5, 31
1438 ; RV32ZBA-NEXT: xor a1, a1, a3
1439 ; RV32ZBA-NEXT: xor a3, s0, a3
1440 ; RV32ZBA-NEXT: or a1, a3, a1
1441 ; RV32ZBA-NEXT: snez a1, a1
1442 ; RV32ZBA-NEXT: mul a0, a0, a2
1443 ; RV32ZBA-NEXT: sw a0, 0(a4)
1444 ; RV32ZBA-NEXT: sw a5, 4(a4)
1445 ; RV32ZBA-NEXT: mv a0, a1
1446 ; RV32ZBA-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
1447 ; RV32ZBA-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
1448 ; RV32ZBA-NEXT: addi sp, sp, 16
1449 ; RV32ZBA-NEXT: ret
1450 ;
1451 ; RV64ZBA-LABEL: smulo.i64:
1452 ; RV64ZBA: # %bb.0: # %entry
1453 ; RV64ZBA-NEXT: mulh a3, a0, a1
1454 ; RV64ZBA-NEXT: mul a1, a0, a1
1455 ; RV64ZBA-NEXT: srai a0, a1, 63
1456 ; RV64ZBA-NEXT: xor a0, a3, a0
1457 ; RV64ZBA-NEXT: snez a0, a0
1458 ; RV64ZBA-NEXT: sd a1, 0(a2)
1459 ; RV64ZBA-NEXT: ret
1460 ;
1461 ; RV32ZICOND-LABEL: smulo.i64:
1462 ; RV32ZICOND: # %bb.0: # %entry
1463 ; RV32ZICOND-NEXT: addi sp, sp, -16
1464 ; RV32ZICOND-NEXT: .cfi_def_cfa_offset 16
1465 ; RV32ZICOND-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
1466 ; RV32ZICOND-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
1467 ; RV32ZICOND-NEXT: .cfi_offset s0, -4
1468 ; RV32ZICOND-NEXT: .cfi_offset s1, -8
1469 ; RV32ZICOND-NEXT: mulhu a5, a0, a2
1470 ; RV32ZICOND-NEXT: mul a6, a1, a2
1471 ; RV32ZICOND-NEXT: add a5, a6, a5
1472 ; RV32ZICOND-NEXT: sltu a6, a5, a6
1473 ; RV32ZICOND-NEXT: mulhu a7, a1, a2
1474 ; RV32ZICOND-NEXT: add a6, a7, a6
1475 ; RV32ZICOND-NEXT: mul a7, a0, a3
1476 ; RV32ZICOND-NEXT: add a5, a7, a5
1477 ; RV32ZICOND-NEXT: sltu a7, a5, a7
1478 ; RV32ZICOND-NEXT: mulhu t0, a0, a3
1479 ; RV32ZICOND-NEXT: add a7, t0, a7
1480 ; RV32ZICOND-NEXT: add a7, a6, a7
1481 ; RV32ZICOND-NEXT: mul t0, a1, a3
1482 ; RV32ZICOND-NEXT: add t1, t0, a7
1483 ; RV32ZICOND-NEXT: srai t2, a1, 31
1484 ; RV32ZICOND-NEXT: mul t3, a2, t2
1485 ; RV32ZICOND-NEXT: srai t4, a3, 31
1486 ; RV32ZICOND-NEXT: mul t5, t4, a0
1487 ; RV32ZICOND-NEXT: add t6, t5, t3
1488 ; RV32ZICOND-NEXT: add s0, t1, t6
1489 ; RV32ZICOND-NEXT: sltu s1, s0, t1
1490 ; RV32ZICOND-NEXT: sltu t0, t1, t0
1491 ; RV32ZICOND-NEXT: sltu a6, a7, a6
1492 ; RV32ZICOND-NEXT: mulhu a7, a1, a3
1493 ; RV32ZICOND-NEXT: add a6, a7, a6
1494 ; RV32ZICOND-NEXT: add a6, a6, t0
1495 ; RV32ZICOND-NEXT: mulhu a7, a2, t2
1496 ; RV32ZICOND-NEXT: add a7, a7, t3
1497 ; RV32ZICOND-NEXT: mul a3, a3, t2
1498 ; RV32ZICOND-NEXT: add a3, a7, a3
1499 ; RV32ZICOND-NEXT: mul a1, t4, a1
1500 ; RV32ZICOND-NEXT: mulhu a7, t4, a0
1501 ; RV32ZICOND-NEXT: add a1, a7, a1
1502 ; RV32ZICOND-NEXT: add a1, a1, t5
1503 ; RV32ZICOND-NEXT: add a1, a1, a3
1504 ; RV32ZICOND-NEXT: sltu a3, t6, t5
1505 ; RV32ZICOND-NEXT: add a1, a1, a3
1506 ; RV32ZICOND-NEXT: add a1, a6, a1
1507 ; RV32ZICOND-NEXT: add a1, a1, s1
1508 ; RV32ZICOND-NEXT: srai a3, a5, 31
1509 ; RV32ZICOND-NEXT: xor a1, a1, a3
1510 ; RV32ZICOND-NEXT: xor a3, s0, a3
1511 ; RV32ZICOND-NEXT: or a1, a3, a1
1512 ; RV32ZICOND-NEXT: snez a1, a1
1513 ; RV32ZICOND-NEXT: mul a0, a0, a2
1514 ; RV32ZICOND-NEXT: sw a0, 0(a4)
1515 ; RV32ZICOND-NEXT: sw a5, 4(a4)
1516 ; RV32ZICOND-NEXT: mv a0, a1
1517 ; RV32ZICOND-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
1518 ; RV32ZICOND-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
1519 ; RV32ZICOND-NEXT: addi sp, sp, 16
1520 ; RV32ZICOND-NEXT: ret
1521 ;
1522 ; RV64ZICOND-LABEL: smulo.i64:
1523 ; RV64ZICOND: # %bb.0: # %entry
1524 ; RV64ZICOND-NEXT: mulh a3, a0, a1
1525 ; RV64ZICOND-NEXT: mul a1, a0, a1
1526 ; RV64ZICOND-NEXT: srai a0, a1, 63
1527 ; RV64ZICOND-NEXT: xor a0, a3, a0
1528 ; RV64ZICOND-NEXT: snez a0, a0
1529 ; RV64ZICOND-NEXT: sd a1, 0(a2)
1530 ; RV64ZICOND-NEXT: ret
1531 entry:
1532 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
1533 %val = extractvalue {i64, i1} %t, 0
1534 %obit = extractvalue {i64, i1} %t, 1
1535 store i64 %val, ptr %res
1536 ret i1 %obit
1537 }
1539 define zeroext i1 @smulo2.i64(i64 %v1, ptr %res) {
1540 ; RV32-LABEL: smulo2.i64:
1541 ; RV32: # %bb.0: # %entry
1542 ; RV32-NEXT: li a3, 13
1543 ; RV32-NEXT: mulhu a4, a0, a3
1544 ; RV32-NEXT: mul a5, a1, a3
1545 ; RV32-NEXT: add a4, a5, a4
1546 ; RV32-NEXT: sltu a5, a4, a5
1547 ; RV32-NEXT: mulhu a6, a1, a3
1548 ; RV32-NEXT: add a5, a6, a5
1549 ; RV32-NEXT: srai a1, a1, 31
1550 ; RV32-NEXT: mul a6, a1, a3
1551 ; RV32-NEXT: add a6, a5, a6
1552 ; RV32-NEXT: srai a7, a4, 31
1553 ; RV32-NEXT: xor t0, a6, a7
1554 ; RV32-NEXT: sltu a5, a6, a5
1555 ; RV32-NEXT: mulh a1, a1, a3
1556 ; RV32-NEXT: add a1, a1, a5
1557 ; RV32-NEXT: xor a1, a1, a7
1558 ; RV32-NEXT: or a1, t0, a1
1559 ; RV32-NEXT: snez a1, a1
1560 ; RV32-NEXT: mul a0, a0, a3
1561 ; RV32-NEXT: sw a0, 0(a2)
1562 ; RV32-NEXT: sw a4, 4(a2)
1563 ; RV32-NEXT: mv a0, a1
1564 ; RV32-NEXT: ret
1565 ;
1566 ; RV64-LABEL: smulo2.i64:
1567 ; RV64: # %bb.0: # %entry
1568 ; RV64-NEXT: li a2, 13
1569 ; RV64-NEXT: mulh a3, a0, a2
1570 ; RV64-NEXT: mul a2, a0, a2
1571 ; RV64-NEXT: srai a0, a2, 63
1572 ; RV64-NEXT: xor a0, a3, a0
1573 ; RV64-NEXT: snez a0, a0
1574 ; RV64-NEXT: sd a2, 0(a1)
1575 ; RV64-NEXT: ret
1576 ;
1577 ; RV32ZBA-LABEL: smulo2.i64:
1578 ; RV32ZBA: # %bb.0: # %entry
1579 ; RV32ZBA-NEXT: li a3, 13
1580 ; RV32ZBA-NEXT: mulhu a4, a0, a3
1581 ; RV32ZBA-NEXT: sh1add a5, a1, a1
1582 ; RV32ZBA-NEXT: sh2add a5, a5, a1
1583 ; RV32ZBA-NEXT: add a4, a5, a4
1584 ; RV32ZBA-NEXT: sltu a5, a4, a5
1585 ; RV32ZBA-NEXT: mulhu a6, a1, a3
1586 ; RV32ZBA-NEXT: add a5, a6, a5
1587 ; RV32ZBA-NEXT: srai a1, a1, 31
1588 ; RV32ZBA-NEXT: sh1add a6, a1, a1
1589 ; RV32ZBA-NEXT: sh2add a6, a6, a1
1590 ; RV32ZBA-NEXT: add a6, a5, a6
1591 ; RV32ZBA-NEXT: srai a7, a4, 31
1592 ; RV32ZBA-NEXT: xor t0, a6, a7
1593 ; RV32ZBA-NEXT: sltu a5, a6, a5
1594 ; RV32ZBA-NEXT: mulh a1, a1, a3
1595 ; RV32ZBA-NEXT: add a1, a1, a5
1596 ; RV32ZBA-NEXT: xor a1, a1, a7
1597 ; RV32ZBA-NEXT: or a1, t0, a1
1598 ; RV32ZBA-NEXT: snez a1, a1
1599 ; RV32ZBA-NEXT: sh1add a3, a0, a0
1600 ; RV32ZBA-NEXT: sh2add a0, a3, a0
1601 ; RV32ZBA-NEXT: sw a0, 0(a2)
1602 ; RV32ZBA-NEXT: sw a4, 4(a2)
1603 ; RV32ZBA-NEXT: mv a0, a1
1604 ; RV32ZBA-NEXT: ret
1605 ;
1606 ; RV64ZBA-LABEL: smulo2.i64:
1607 ; RV64ZBA: # %bb.0: # %entry
1608 ; RV64ZBA-NEXT: li a2, 13
1609 ; RV64ZBA-NEXT: mulh a2, a0, a2
1610 ; RV64ZBA-NEXT: sh1add a3, a0, a0
1611 ; RV64ZBA-NEXT: sh2add a3, a3, a0
1612 ; RV64ZBA-NEXT: srai a0, a3, 63
1613 ; RV64ZBA-NEXT: xor a0, a2, a0
1614 ; RV64ZBA-NEXT: snez a0, a0
1615 ; RV64ZBA-NEXT: sd a3, 0(a1)
1616 ; RV64ZBA-NEXT: ret
1617 ;
1618 ; RV32ZICOND-LABEL: smulo2.i64:
1619 ; RV32ZICOND: # %bb.0: # %entry
1620 ; RV32ZICOND-NEXT: li a3, 13
1621 ; RV32ZICOND-NEXT: mulhu a4, a0, a3
1622 ; RV32ZICOND-NEXT: mul a5, a1, a3
1623 ; RV32ZICOND-NEXT: add a4, a5, a4
1624 ; RV32ZICOND-NEXT: sltu a5, a4, a5
1625 ; RV32ZICOND-NEXT: mulhu a6, a1, a3
1626 ; RV32ZICOND-NEXT: add a5, a6, a5
1627 ; RV32ZICOND-NEXT: srai a1, a1, 31
1628 ; RV32ZICOND-NEXT: mul a6, a1, a3
1629 ; RV32ZICOND-NEXT: add a6, a5, a6
1630 ; RV32ZICOND-NEXT: srai a7, a4, 31
1631 ; RV32ZICOND-NEXT: xor t0, a6, a7
1632 ; RV32ZICOND-NEXT: sltu a5, a6, a5
1633 ; RV32ZICOND-NEXT: mulh a1, a1, a3
1634 ; RV32ZICOND-NEXT: add a1, a1, a5
1635 ; RV32ZICOND-NEXT: xor a1, a1, a7
1636 ; RV32ZICOND-NEXT: or a1, t0, a1
1637 ; RV32ZICOND-NEXT: snez a1, a1
1638 ; RV32ZICOND-NEXT: mul a0, a0, a3
1639 ; RV32ZICOND-NEXT: sw a0, 0(a2)
1640 ; RV32ZICOND-NEXT: sw a4, 4(a2)
1641 ; RV32ZICOND-NEXT: mv a0, a1
1642 ; RV32ZICOND-NEXT: ret
1643 ;
1644 ; RV64ZICOND-LABEL: smulo2.i64:
1645 ; RV64ZICOND: # %bb.0: # %entry
1646 ; RV64ZICOND-NEXT: li a2, 13
1647 ; RV64ZICOND-NEXT: mulh a3, a0, a2
1648 ; RV64ZICOND-NEXT: mul a2, a0, a2
1649 ; RV64ZICOND-NEXT: srai a0, a2, 63
1650 ; RV64ZICOND-NEXT: xor a0, a3, a0
1651 ; RV64ZICOND-NEXT: snez a0, a0
1652 ; RV64ZICOND-NEXT: sd a2, 0(a1)
1653 ; RV64ZICOND-NEXT: ret
1654 entry:
1655 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 13)
1656 %val = extractvalue {i64, i1} %t, 0
1657 %obit = extractvalue {i64, i1} %t, 1
1658 store i64 %val, ptr %res
1659 ret i1 %obit
1660 }
1662 define zeroext i1 @umulo.i32(i32 signext %v1, i32 signext %v2, ptr %res) {
1663 ; RV32-LABEL: umulo.i32:
1664 ; RV32: # %bb.0: # %entry
1665 ; RV32-NEXT: mulhu a3, a0, a1
1666 ; RV32-NEXT: snez a3, a3
1667 ; RV32-NEXT: mul a0, a0, a1
1668 ; RV32-NEXT: sw a0, 0(a2)
1669 ; RV32-NEXT: mv a0, a3
1670 ; RV32-NEXT: ret
1671 ;
1672 ; RV64-LABEL: umulo.i32:
1673 ; RV64: # %bb.0: # %entry
1674 ; RV64-NEXT: slli a1, a1, 32
1675 ; RV64-NEXT: slli a0, a0, 32
1676 ; RV64-NEXT: mulhu a1, a0, a1
1677 ; RV64-NEXT: srli a0, a1, 32
1678 ; RV64-NEXT: snez a0, a0
1679 ; RV64-NEXT: sw a1, 0(a2)
1680 ; RV64-NEXT: ret
1681 ;
1682 ; RV32ZBA-LABEL: umulo.i32:
1683 ; RV32ZBA: # %bb.0: # %entry
1684 ; RV32ZBA-NEXT: mulhu a3, a0, a1
1685 ; RV32ZBA-NEXT: snez a3, a3
1686 ; RV32ZBA-NEXT: mul a0, a0, a1
1687 ; RV32ZBA-NEXT: sw a0, 0(a2)
1688 ; RV32ZBA-NEXT: mv a0, a3
1689 ; RV32ZBA-NEXT: ret
1690 ;
1691 ; RV64ZBA-LABEL: umulo.i32:
1692 ; RV64ZBA: # %bb.0: # %entry
1693 ; RV64ZBA-NEXT: zext.w a1, a1
1694 ; RV64ZBA-NEXT: zext.w a0, a0
1695 ; RV64ZBA-NEXT: mul a1, a0, a1
1696 ; RV64ZBA-NEXT: srli a0, a1, 32
1697 ; RV64ZBA-NEXT: snez a0, a0
1698 ; RV64ZBA-NEXT: sw a1, 0(a2)
1699 ; RV64ZBA-NEXT: ret
1700 ;
1701 ; RV32ZICOND-LABEL: umulo.i32:
1702 ; RV32ZICOND: # %bb.0: # %entry
1703 ; RV32ZICOND-NEXT: mulhu a3, a0, a1
1704 ; RV32ZICOND-NEXT: snez a3, a3
1705 ; RV32ZICOND-NEXT: mul a0, a0, a1
1706 ; RV32ZICOND-NEXT: sw a0, 0(a2)
1707 ; RV32ZICOND-NEXT: mv a0, a3
1708 ; RV32ZICOND-NEXT: ret
1709 ;
1710 ; RV64ZICOND-LABEL: umulo.i32:
1711 ; RV64ZICOND: # %bb.0: # %entry
1712 ; RV64ZICOND-NEXT: slli a1, a1, 32
1713 ; RV64ZICOND-NEXT: slli a0, a0, 32
1714 ; RV64ZICOND-NEXT: mulhu a1, a0, a1
1715 ; RV64ZICOND-NEXT: srli a0, a1, 32
1716 ; RV64ZICOND-NEXT: snez a0, a0
1717 ; RV64ZICOND-NEXT: sw a1, 0(a2)
1718 ; RV64ZICOND-NEXT: ret
1719 entry:
1720 %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
1721 %val = extractvalue {i32, i1} %t, 0
1722 %obit = extractvalue {i32, i1} %t, 1
1723 store i32 %val, ptr %res
1724 ret i1 %obit
1725 }
1727 define zeroext i1 @umulo2.i32(i32 signext %v1, ptr %res) {
1728 ; RV32-LABEL: umulo2.i32:
1729 ; RV32: # %bb.0: # %entry
1730 ; RV32-NEXT: li a3, 13
1731 ; RV32-NEXT: mulhu a2, a0, a3
1732 ; RV32-NEXT: snez a2, a2
1733 ; RV32-NEXT: mul a0, a0, a3
1734 ; RV32-NEXT: sw a0, 0(a1)
1735 ; RV32-NEXT: mv a0, a2
1736 ; RV32-NEXT: ret
1737 ;
1738 ; RV64-LABEL: umulo2.i32:
1739 ; RV64: # %bb.0: # %entry
1740 ; RV64-NEXT: li a2, 13
1741 ; RV64-NEXT: slli a2, a2, 32
1742 ; RV64-NEXT: slli a0, a0, 32
1743 ; RV64-NEXT: mulhu a2, a0, a2
1744 ; RV64-NEXT: srli a0, a2, 32
1745 ; RV64-NEXT: snez a0, a0
1746 ; RV64-NEXT: sw a2, 0(a1)
1747 ; RV64-NEXT: ret
1748 ;
1749 ; RV32ZBA-LABEL: umulo2.i32:
1750 ; RV32ZBA: # %bb.0: # %entry
1751 ; RV32ZBA-NEXT: li a2, 13
1752 ; RV32ZBA-NEXT: mulhu a2, a0, a2
1753 ; RV32ZBA-NEXT: snez a2, a2
1754 ; RV32ZBA-NEXT: sh1add a3, a0, a0
1755 ; RV32ZBA-NEXT: sh2add a0, a3, a0
1756 ; RV32ZBA-NEXT: sw a0, 0(a1)
1757 ; RV32ZBA-NEXT: mv a0, a2
1758 ; RV32ZBA-NEXT: ret
1759 ;
1760 ; RV64ZBA-LABEL: umulo2.i32:
1761 ; RV64ZBA: # %bb.0: # %entry
1762 ; RV64ZBA-NEXT: zext.w a2, a0
1763 ; RV64ZBA-NEXT: sh1add.uw a0, a0, a2
1764 ; RV64ZBA-NEXT: sh2add a2, a0, a2
1765 ; RV64ZBA-NEXT: srli a0, a2, 32
1766 ; RV64ZBA-NEXT: snez a0, a0
1767 ; RV64ZBA-NEXT: sw a2, 0(a1)
1768 ; RV64ZBA-NEXT: ret
1769 ;
1770 ; RV32ZICOND-LABEL: umulo2.i32:
1771 ; RV32ZICOND: # %bb.0: # %entry
1772 ; RV32ZICOND-NEXT: li a3, 13
1773 ; RV32ZICOND-NEXT: mulhu a2, a0, a3
1774 ; RV32ZICOND-NEXT: snez a2, a2
1775 ; RV32ZICOND-NEXT: mul a0, a0, a3
1776 ; RV32ZICOND-NEXT: sw a0, 0(a1)
1777 ; RV32ZICOND-NEXT: mv a0, a2
1778 ; RV32ZICOND-NEXT: ret
1779 ;
1780 ; RV64ZICOND-LABEL: umulo2.i32:
1781 ; RV64ZICOND: # %bb.0: # %entry
1782 ; RV64ZICOND-NEXT: li a2, 13
1783 ; RV64ZICOND-NEXT: slli a2, a2, 32
1784 ; RV64ZICOND-NEXT: slli a0, a0, 32
1785 ; RV64ZICOND-NEXT: mulhu a2, a0, a2
1786 ; RV64ZICOND-NEXT: srli a0, a2, 32
1787 ; RV64ZICOND-NEXT: snez a0, a0
1788 ; RV64ZICOND-NEXT: sw a2, 0(a1)
1789 ; RV64ZICOND-NEXT: ret
1790 entry:
1791 %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 13)
1792 %val = extractvalue {i32, i1} %t, 0
1793 %obit = extractvalue {i32, i1} %t, 1
1794 store i32 %val, ptr %res
1795 ret i1 %obit
1796 }
1798 ; Similar to umulo.i32, but storing the overflow and returning the result.
1799 define signext i32 @umulo3.i32(i32 signext %0, i32 signext %1, ptr %2) {
1800 ; RV32-LABEL: umulo3.i32:
1801 ; RV32: # %bb.0:
1802 ; RV32-NEXT: mul a3, a0, a1
1803 ; RV32-NEXT: mulhu a0, a0, a1
1804 ; RV32-NEXT: snez a0, a0
1805 ; RV32-NEXT: sw a0, 0(a2)
1806 ; RV32-NEXT: mv a0, a3
1807 ; RV32-NEXT: ret
1808 ;
1809 ; RV64-LABEL: umulo3.i32:
1810 ; RV64: # %bb.0:
1811 ; RV64-NEXT: slli a1, a1, 32
1812 ; RV64-NEXT: slli a0, a0, 32
1813 ; RV64-NEXT: mulhu a0, a0, a1
1814 ; RV64-NEXT: srli a1, a0, 32
1815 ; RV64-NEXT: snez a1, a1
1816 ; RV64-NEXT: sext.w a0, a0
1817 ; RV64-NEXT: sw a1, 0(a2)
1818 ; RV64-NEXT: ret
1819 ;
1820 ; RV32ZBA-LABEL: umulo3.i32:
1821 ; RV32ZBA: # %bb.0:
1822 ; RV32ZBA-NEXT: mul a3, a0, a1
1823 ; RV32ZBA-NEXT: mulhu a0, a0, a1
1824 ; RV32ZBA-NEXT: snez a0, a0
1825 ; RV32ZBA-NEXT: sw a0, 0(a2)
1826 ; RV32ZBA-NEXT: mv a0, a3
1827 ; RV32ZBA-NEXT: ret
1828 ;
1829 ; RV64ZBA-LABEL: umulo3.i32:
1830 ; RV64ZBA: # %bb.0:
1831 ; RV64ZBA-NEXT: zext.w a1, a1
1832 ; RV64ZBA-NEXT: zext.w a0, a0
1833 ; RV64ZBA-NEXT: mul a3, a0, a1
1834 ; RV64ZBA-NEXT: srli a3, a3, 32
1835 ; RV64ZBA-NEXT: snez a3, a3
1836 ; RV64ZBA-NEXT: mulw a0, a0, a1
1837 ; RV64ZBA-NEXT: sw a3, 0(a2)
1838 ; RV64ZBA-NEXT: ret
1839 ;
1840 ; RV32ZICOND-LABEL: umulo3.i32:
1841 ; RV32ZICOND: # %bb.0:
1842 ; RV32ZICOND-NEXT: mul a3, a0, a1
1843 ; RV32ZICOND-NEXT: mulhu a0, a0, a1
1844 ; RV32ZICOND-NEXT: snez a0, a0
1845 ; RV32ZICOND-NEXT: sw a0, 0(a2)
1846 ; RV32ZICOND-NEXT: mv a0, a3
1847 ; RV32ZICOND-NEXT: ret
1848 ;
1849 ; RV64ZICOND-LABEL: umulo3.i32:
1850 ; RV64ZICOND: # %bb.0:
1851 ; RV64ZICOND-NEXT: slli a1, a1, 32
1852 ; RV64ZICOND-NEXT: slli a0, a0, 32
1853 ; RV64ZICOND-NEXT: mulhu a0, a0, a1
1854 ; RV64ZICOND-NEXT: srli a1, a0, 32
1855 ; RV64ZICOND-NEXT: snez a1, a1
1856 ; RV64ZICOND-NEXT: sext.w a0, a0
1857 ; RV64ZICOND-NEXT: sw a1, 0(a2)
1858 ; RV64ZICOND-NEXT: ret
1859 %4 = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %0, i32 %1)
1860 %5 = extractvalue { i32, i1 } %4, 1
1861 %6 = extractvalue { i32, i1 } %4, 0
1862 %7 = zext i1 %5 to i32
1863 store i32 %7, ptr %2, align 4
1864 ret i32 %6
1865 }
1867 define zeroext i1 @umulo.i64(i64 %v1, i64 %v2, ptr %res) {
1868 ; RV32-LABEL: umulo.i64:
1869 ; RV32: # %bb.0: # %entry
1870 ; RV32-NEXT: mul a5, a3, a0
1871 ; RV32-NEXT: mul a6, a1, a2
1872 ; RV32-NEXT: add a5, a6, a5
1873 ; RV32-NEXT: mulhu a6, a0, a2
1874 ; RV32-NEXT: add a5, a6, a5
1875 ; RV32-NEXT: sltu a6, a5, a6
1876 ; RV32-NEXT: snez a7, a3
1877 ; RV32-NEXT: snez t0, a1
1878 ; RV32-NEXT: and a7, t0, a7
1879 ; RV32-NEXT: mulhu a1, a1, a2
1880 ; RV32-NEXT: snez a1, a1
1881 ; RV32-NEXT: or a1, a7, a1
1882 ; RV32-NEXT: mulhu a3, a3, a0
1883 ; RV32-NEXT: snez a3, a3
1884 ; RV32-NEXT: or a1, a1, a3
1885 ; RV32-NEXT: or a1, a1, a6
1886 ; RV32-NEXT: mul a0, a0, a2
1887 ; RV32-NEXT: sw a0, 0(a4)
1888 ; RV32-NEXT: sw a5, 4(a4)
1889 ; RV32-NEXT: mv a0, a1
1890 ; RV32-NEXT: ret
1891 ;
1892 ; RV64-LABEL: umulo.i64:
1893 ; RV64: # %bb.0: # %entry
1894 ; RV64-NEXT: mulhu a3, a0, a1
1895 ; RV64-NEXT: snez a3, a3
1896 ; RV64-NEXT: mul a0, a0, a1
1897 ; RV64-NEXT: sd a0, 0(a2)
1898 ; RV64-NEXT: mv a0, a3
1899 ; RV64-NEXT: ret
1900 ;
1901 ; RV32ZBA-LABEL: umulo.i64:
1902 ; RV32ZBA: # %bb.0: # %entry
1903 ; RV32ZBA-NEXT: mul a5, a3, a0
1904 ; RV32ZBA-NEXT: mul a6, a1, a2
1905 ; RV32ZBA-NEXT: add a5, a6, a5
1906 ; RV32ZBA-NEXT: mulhu a6, a0, a2
1907 ; RV32ZBA-NEXT: add a5, a6, a5
1908 ; RV32ZBA-NEXT: sltu a6, a5, a6
1909 ; RV32ZBA-NEXT: snez a7, a3
1910 ; RV32ZBA-NEXT: snez t0, a1
1911 ; RV32ZBA-NEXT: and a7, t0, a7
1912 ; RV32ZBA-NEXT: mulhu a1, a1, a2
1913 ; RV32ZBA-NEXT: snez a1, a1
1914 ; RV32ZBA-NEXT: or a1, a7, a1
1915 ; RV32ZBA-NEXT: mulhu a3, a3, a0
1916 ; RV32ZBA-NEXT: snez a3, a3
1917 ; RV32ZBA-NEXT: or a1, a1, a3
1918 ; RV32ZBA-NEXT: or a1, a1, a6
1919 ; RV32ZBA-NEXT: mul a0, a0, a2
1920 ; RV32ZBA-NEXT: sw a0, 0(a4)
1921 ; RV32ZBA-NEXT: sw a5, 4(a4)
1922 ; RV32ZBA-NEXT: mv a0, a1
1923 ; RV32ZBA-NEXT: ret
1924 ;
1925 ; RV64ZBA-LABEL: umulo.i64:
1926 ; RV64ZBA: # %bb.0: # %entry
1927 ; RV64ZBA-NEXT: mulhu a3, a0, a1
1928 ; RV64ZBA-NEXT: snez a3, a3
1929 ; RV64ZBA-NEXT: mul a0, a0, a1
1930 ; RV64ZBA-NEXT: sd a0, 0(a2)
1931 ; RV64ZBA-NEXT: mv a0, a3
1932 ; RV64ZBA-NEXT: ret
1933 ;
1934 ; RV32ZICOND-LABEL: umulo.i64:
1935 ; RV32ZICOND: # %bb.0: # %entry
1936 ; RV32ZICOND-NEXT: mul a5, a3, a0
1937 ; RV32ZICOND-NEXT: mul a6, a1, a2
1938 ; RV32ZICOND-NEXT: add a5, a6, a5
1939 ; RV32ZICOND-NEXT: mulhu a6, a0, a2
1940 ; RV32ZICOND-NEXT: add a5, a6, a5
1941 ; RV32ZICOND-NEXT: sltu a6, a5, a6
1942 ; RV32ZICOND-NEXT: snez a7, a3
1943 ; RV32ZICOND-NEXT: snez t0, a1
1944 ; RV32ZICOND-NEXT: and a7, t0, a7
1945 ; RV32ZICOND-NEXT: mulhu a1, a1, a2
1946 ; RV32ZICOND-NEXT: snez a1, a1
1947 ; RV32ZICOND-NEXT: or a1, a7, a1
1948 ; RV32ZICOND-NEXT: mulhu a3, a3, a0
1949 ; RV32ZICOND-NEXT: snez a3, a3
1950 ; RV32ZICOND-NEXT: or a1, a1, a3
1951 ; RV32ZICOND-NEXT: or a1, a1, a6
1952 ; RV32ZICOND-NEXT: mul a0, a0, a2
1953 ; RV32ZICOND-NEXT: sw a0, 0(a4)
1954 ; RV32ZICOND-NEXT: sw a5, 4(a4)
1955 ; RV32ZICOND-NEXT: mv a0, a1
1956 ; RV32ZICOND-NEXT: ret
1957 ;
1958 ; RV64ZICOND-LABEL: umulo.i64:
1959 ; RV64ZICOND: # %bb.0: # %entry
1960 ; RV64ZICOND-NEXT: mulhu a3, a0, a1
1961 ; RV64ZICOND-NEXT: snez a3, a3
1962 ; RV64ZICOND-NEXT: mul a0, a0, a1
1963 ; RV64ZICOND-NEXT: sd a0, 0(a2)
1964 ; RV64ZICOND-NEXT: mv a0, a3
1965 ; RV64ZICOND-NEXT: ret
1966 entry:
1967 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
1968 %val = extractvalue {i64, i1} %t, 0
1969 %obit = extractvalue {i64, i1} %t, 1
1970 store i64 %val, ptr %res
1971 ret i1 %obit
1972 }
1974 define zeroext i1 @umulo2.i64(i64 %v1, ptr %res) {
1975 ; RV32-LABEL: umulo2.i64:
1976 ; RV32: # %bb.0: # %entry
1977 ; RV32-NEXT: li a3, 13
1978 ; RV32-NEXT: mul a4, a1, a3
1979 ; RV32-NEXT: mulhu a5, a0, a3
1980 ; RV32-NEXT: add a4, a5, a4
1981 ; RV32-NEXT: sltu a5, a4, a5
1982 ; RV32-NEXT: mulhu a1, a1, a3
1983 ; RV32-NEXT: snez a1, a1
1984 ; RV32-NEXT: or a1, a1, a5
1985 ; RV32-NEXT: mul a0, a0, a3
1986 ; RV32-NEXT: sw a0, 0(a2)
1987 ; RV32-NEXT: sw a4, 4(a2)
1988 ; RV32-NEXT: mv a0, a1
1989 ; RV32-NEXT: ret
1990 ;
1991 ; RV64-LABEL: umulo2.i64:
1992 ; RV64: # %bb.0: # %entry
1993 ; RV64-NEXT: li a3, 13
1994 ; RV64-NEXT: mulhu a2, a0, a3
1995 ; RV64-NEXT: snez a2, a2
1996 ; RV64-NEXT: mul a0, a0, a3
1997 ; RV64-NEXT: sd a0, 0(a1)
1998 ; RV64-NEXT: mv a0, a2
1999 ; RV64-NEXT: ret
2000 ;
2001 ; RV32ZBA-LABEL: umulo2.i64:
2002 ; RV32ZBA: # %bb.0: # %entry
2003 ; RV32ZBA-NEXT: li a3, 13
2004 ; RV32ZBA-NEXT: mulhu a4, a0, a3
2005 ; RV32ZBA-NEXT: sh1add a5, a1, a1
2006 ; RV32ZBA-NEXT: sh2add a5, a5, a1
2007 ; RV32ZBA-NEXT: add a5, a4, a5
2008 ; RV32ZBA-NEXT: sltu a4, a5, a4
2009 ; RV32ZBA-NEXT: mulhu a1, a1, a3
2010 ; RV32ZBA-NEXT: snez a1, a1
2011 ; RV32ZBA-NEXT: or a1, a1, a4
2012 ; RV32ZBA-NEXT: sh1add a3, a0, a0
2013 ; RV32ZBA-NEXT: sh2add a0, a3, a0
2014 ; RV32ZBA-NEXT: sw a0, 0(a2)
2015 ; RV32ZBA-NEXT: sw a5, 4(a2)
2016 ; RV32ZBA-NEXT: mv a0, a1
2017 ; RV32ZBA-NEXT: ret
2018 ;
2019 ; RV64ZBA-LABEL: umulo2.i64:
2020 ; RV64ZBA: # %bb.0: # %entry
2021 ; RV64ZBA-NEXT: li a2, 13
2022 ; RV64ZBA-NEXT: mulhu a2, a0, a2
2023 ; RV64ZBA-NEXT: snez a2, a2
2024 ; RV64ZBA-NEXT: sh1add a3, a0, a0
2025 ; RV64ZBA-NEXT: sh2add a0, a3, a0
2026 ; RV64ZBA-NEXT: sd a0, 0(a1)
2027 ; RV64ZBA-NEXT: mv a0, a2
2028 ; RV64ZBA-NEXT: ret
2029 ;
2030 ; RV32ZICOND-LABEL: umulo2.i64:
2031 ; RV32ZICOND: # %bb.0: # %entry
2032 ; RV32ZICOND-NEXT: li a3, 13
2033 ; RV32ZICOND-NEXT: mul a4, a1, a3
2034 ; RV32ZICOND-NEXT: mulhu a5, a0, a3
2035 ; RV32ZICOND-NEXT: add a4, a5, a4
2036 ; RV32ZICOND-NEXT: sltu a5, a4, a5
2037 ; RV32ZICOND-NEXT: mulhu a1, a1, a3
2038 ; RV32ZICOND-NEXT: snez a1, a1
2039 ; RV32ZICOND-NEXT: or a1, a1, a5
2040 ; RV32ZICOND-NEXT: mul a0, a0, a3
2041 ; RV32ZICOND-NEXT: sw a0, 0(a2)
2042 ; RV32ZICOND-NEXT: sw a4, 4(a2)
2043 ; RV32ZICOND-NEXT: mv a0, a1
2044 ; RV32ZICOND-NEXT: ret
2045 ;
2046 ; RV64ZICOND-LABEL: umulo2.i64:
2047 ; RV64ZICOND: # %bb.0: # %entry
2048 ; RV64ZICOND-NEXT: li a3, 13
2049 ; RV64ZICOND-NEXT: mulhu a2, a0, a3
2050 ; RV64ZICOND-NEXT: snez a2, a2
2051 ; RV64ZICOND-NEXT: mul a0, a0, a3
2052 ; RV64ZICOND-NEXT: sd a0, 0(a1)
2053 ; RV64ZICOND-NEXT: mv a0, a2
2054 ; RV64ZICOND-NEXT: ret
2055 entry:
2056 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 13)
2057 %val = extractvalue {i64, i1} %t, 0
2058 %obit = extractvalue {i64, i1} %t, 1
2059 store i64 %val, ptr %res
2060 ret i1 %obit
2061 }
2064 ;
2065 ; Check the use of the overflow bit in combination with a select instruction.
2066 ;
2067 define i32 @saddo.select.i32(i32 signext %v1, i32 signext %v2) {
2068 ; RV32-LABEL: saddo.select.i32:
2069 ; RV32: # %bb.0: # %entry
2070 ; RV32-NEXT: add a2, a0, a1
2071 ; RV32-NEXT: slt a2, a2, a0
2072 ; RV32-NEXT: slti a3, a1, 0
2073 ; RV32-NEXT: bne a3, a2, .LBB28_2
2074 ; RV32-NEXT: # %bb.1: # %entry
2075 ; RV32-NEXT: mv a0, a1
2076 ; RV32-NEXT: .LBB28_2: # %entry
2077 ; RV32-NEXT: ret
2078 ;
2079 ; RV64-LABEL: saddo.select.i32:
2080 ; RV64: # %bb.0: # %entry
2081 ; RV64-NEXT: add a2, a0, a1
2082 ; RV64-NEXT: addw a3, a0, a1
2083 ; RV64-NEXT: bne a3, a2, .LBB28_2
2084 ; RV64-NEXT: # %bb.1: # %entry
2085 ; RV64-NEXT: mv a0, a1
2086 ; RV64-NEXT: .LBB28_2: # %entry
2087 ; RV64-NEXT: ret
2088 ;
2089 ; RV32ZBA-LABEL: saddo.select.i32:
2090 ; RV32ZBA: # %bb.0: # %entry
2091 ; RV32ZBA-NEXT: add a2, a0, a1
2092 ; RV32ZBA-NEXT: slt a2, a2, a0
2093 ; RV32ZBA-NEXT: slti a3, a1, 0
2094 ; RV32ZBA-NEXT: bne a3, a2, .LBB28_2
2095 ; RV32ZBA-NEXT: # %bb.1: # %entry
2096 ; RV32ZBA-NEXT: mv a0, a1
2097 ; RV32ZBA-NEXT: .LBB28_2: # %entry
2098 ; RV32ZBA-NEXT: ret
2099 ;
2100 ; RV64ZBA-LABEL: saddo.select.i32:
2101 ; RV64ZBA: # %bb.0: # %entry
2102 ; RV64ZBA-NEXT: add a2, a0, a1
2103 ; RV64ZBA-NEXT: addw a3, a0, a1
2104 ; RV64ZBA-NEXT: bne a3, a2, .LBB28_2
2105 ; RV64ZBA-NEXT: # %bb.1: # %entry
2106 ; RV64ZBA-NEXT: mv a0, a1
2107 ; RV64ZBA-NEXT: .LBB28_2: # %entry
2108 ; RV64ZBA-NEXT: ret
2109 ;
2110 ; RV32ZICOND-LABEL: saddo.select.i32:
2111 ; RV32ZICOND: # %bb.0: # %entry
2112 ; RV32ZICOND-NEXT: add a2, a0, a1
2113 ; RV32ZICOND-NEXT: slt a2, a2, a0
2114 ; RV32ZICOND-NEXT: slti a3, a1, 0
2115 ; RV32ZICOND-NEXT: xor a2, a3, a2
2116 ; RV32ZICOND-NEXT: czero.nez a1, a1, a2
2117 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a2
2118 ; RV32ZICOND-NEXT: or a0, a0, a1
2119 ; RV32ZICOND-NEXT: ret
2120 ;
2121 ; RV64ZICOND-LABEL: saddo.select.i32:
2122 ; RV64ZICOND: # %bb.0: # %entry
2123 ; RV64ZICOND-NEXT: add a2, a0, a1
2124 ; RV64ZICOND-NEXT: addw a3, a0, a1
2125 ; RV64ZICOND-NEXT: xor a2, a3, a2
2126 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2
2127 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
2128 ; RV64ZICOND-NEXT: or a0, a0, a1
2129 ; RV64ZICOND-NEXT: ret
2130 entry:
2131 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
2132 %obit = extractvalue {i32, i1} %t, 1
2133 %ret = select i1 %obit, i32 %v1, i32 %v2
2134 ret i32 %ret
2135 }
2137 define i1 @saddo.not.i32(i32 signext %v1, i32 signext %v2) {
2138 ; RV32-LABEL: saddo.not.i32:
2139 ; RV32: # %bb.0: # %entry
2140 ; RV32-NEXT: add a2, a0, a1
2141 ; RV32-NEXT: slt a0, a2, a0
2142 ; RV32-NEXT: slti a1, a1, 0
2143 ; RV32-NEXT: xor a0, a1, a0
2144 ; RV32-NEXT: xori a0, a0, 1
2145 ; RV32-NEXT: ret
2146 ;
2147 ; RV64-LABEL: saddo.not.i32:
2148 ; RV64: # %bb.0: # %entry
2149 ; RV64-NEXT: add a2, a0, a1
2150 ; RV64-NEXT: addw a0, a0, a1
2151 ; RV64-NEXT: xor a0, a0, a2
2152 ; RV64-NEXT: seqz a0, a0
2153 ; RV64-NEXT: ret
2154 ;
2155 ; RV32ZBA-LABEL: saddo.not.i32:
2156 ; RV32ZBA: # %bb.0: # %entry
2157 ; RV32ZBA-NEXT: add a2, a0, a1
2158 ; RV32ZBA-NEXT: slt a0, a2, a0
2159 ; RV32ZBA-NEXT: slti a1, a1, 0
2160 ; RV32ZBA-NEXT: xor a0, a1, a0
2161 ; RV32ZBA-NEXT: xori a0, a0, 1
2162 ; RV32ZBA-NEXT: ret
2163 ;
2164 ; RV64ZBA-LABEL: saddo.not.i32:
2165 ; RV64ZBA: # %bb.0: # %entry
2166 ; RV64ZBA-NEXT: add a2, a0, a1
2167 ; RV64ZBA-NEXT: addw a0, a0, a1
2168 ; RV64ZBA-NEXT: xor a0, a0, a2
2169 ; RV64ZBA-NEXT: seqz a0, a0
2170 ; RV64ZBA-NEXT: ret
2171 ;
2172 ; RV32ZICOND-LABEL: saddo.not.i32:
2173 ; RV32ZICOND: # %bb.0: # %entry
2174 ; RV32ZICOND-NEXT: add a2, a0, a1
2175 ; RV32ZICOND-NEXT: slt a0, a2, a0
2176 ; RV32ZICOND-NEXT: slti a1, a1, 0
2177 ; RV32ZICOND-NEXT: xor a0, a1, a0
2178 ; RV32ZICOND-NEXT: xori a0, a0, 1
2179 ; RV32ZICOND-NEXT: ret
2180 ;
2181 ; RV64ZICOND-LABEL: saddo.not.i32:
2182 ; RV64ZICOND: # %bb.0: # %entry
2183 ; RV64ZICOND-NEXT: add a2, a0, a1
2184 ; RV64ZICOND-NEXT: addw a0, a0, a1
2185 ; RV64ZICOND-NEXT: xor a0, a0, a2
2186 ; RV64ZICOND-NEXT: seqz a0, a0
2187 ; RV64ZICOND-NEXT: ret
2188 entry:
2189 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
2190 %obit = extractvalue {i32, i1} %t, 1
2191 %ret = xor i1 %obit, true
2192 ret i1 %ret
2193 }
2195 define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
2196 ; RV32-LABEL: saddo.select.i64:
2197 ; RV32: # %bb.0: # %entry
2198 ; RV32-NEXT: add a4, a1, a3
2199 ; RV32-NEXT: add a5, a0, a2
2200 ; RV32-NEXT: sltu a5, a5, a0
2201 ; RV32-NEXT: add a4, a4, a5
2202 ; RV32-NEXT: xor a4, a1, a4
2203 ; RV32-NEXT: xor a5, a1, a3
2204 ; RV32-NEXT: not a5, a5
2205 ; RV32-NEXT: and a4, a5, a4
2206 ; RV32-NEXT: bltz a4, .LBB30_2
2207 ; RV32-NEXT: # %bb.1: # %entry
2208 ; RV32-NEXT: mv a0, a2
2209 ; RV32-NEXT: mv a1, a3
2210 ; RV32-NEXT: .LBB30_2: # %entry
2211 ; RV32-NEXT: ret
2212 ;
2213 ; RV64-LABEL: saddo.select.i64:
2214 ; RV64: # %bb.0: # %entry
2215 ; RV64-NEXT: add a2, a0, a1
2216 ; RV64-NEXT: slt a2, a2, a0
2217 ; RV64-NEXT: slti a3, a1, 0
2218 ; RV64-NEXT: bne a3, a2, .LBB30_2
2219 ; RV64-NEXT: # %bb.1: # %entry
2220 ; RV64-NEXT: mv a0, a1
2221 ; RV64-NEXT: .LBB30_2: # %entry
2222 ; RV64-NEXT: ret
2223 ;
2224 ; RV32ZBA-LABEL: saddo.select.i64:
2225 ; RV32ZBA: # %bb.0: # %entry
2226 ; RV32ZBA-NEXT: add a4, a1, a3
2227 ; RV32ZBA-NEXT: add a5, a0, a2
2228 ; RV32ZBA-NEXT: sltu a5, a5, a0
2229 ; RV32ZBA-NEXT: add a4, a4, a5
2230 ; RV32ZBA-NEXT: xor a4, a1, a4
2231 ; RV32ZBA-NEXT: xor a5, a1, a3
2232 ; RV32ZBA-NEXT: not a5, a5
2233 ; RV32ZBA-NEXT: and a4, a5, a4
2234 ; RV32ZBA-NEXT: bltz a4, .LBB30_2
2235 ; RV32ZBA-NEXT: # %bb.1: # %entry
2236 ; RV32ZBA-NEXT: mv a0, a2
2237 ; RV32ZBA-NEXT: mv a1, a3
2238 ; RV32ZBA-NEXT: .LBB30_2: # %entry
2239 ; RV32ZBA-NEXT: ret
2240 ;
2241 ; RV64ZBA-LABEL: saddo.select.i64:
2242 ; RV64ZBA: # %bb.0: # %entry
2243 ; RV64ZBA-NEXT: add a2, a0, a1
2244 ; RV64ZBA-NEXT: slt a2, a2, a0
2245 ; RV64ZBA-NEXT: slti a3, a1, 0
2246 ; RV64ZBA-NEXT: bne a3, a2, .LBB30_2
2247 ; RV64ZBA-NEXT: # %bb.1: # %entry
2248 ; RV64ZBA-NEXT: mv a0, a1
2249 ; RV64ZBA-NEXT: .LBB30_2: # %entry
2250 ; RV64ZBA-NEXT: ret
2251 ;
2252 ; RV32ZICOND-LABEL: saddo.select.i64:
2253 ; RV32ZICOND: # %bb.0: # %entry
2254 ; RV32ZICOND-NEXT: add a4, a1, a3
2255 ; RV32ZICOND-NEXT: add a5, a0, a2
2256 ; RV32ZICOND-NEXT: sltu a5, a5, a0
2257 ; RV32ZICOND-NEXT: add a4, a4, a5
2258 ; RV32ZICOND-NEXT: xor a4, a1, a4
2259 ; RV32ZICOND-NEXT: xor a5, a1, a3
2260 ; RV32ZICOND-NEXT: not a5, a5
2261 ; RV32ZICOND-NEXT: and a4, a5, a4
2262 ; RV32ZICOND-NEXT: slti a4, a4, 0
2263 ; RV32ZICOND-NEXT: czero.nez a2, a2, a4
2264 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a4
2265 ; RV32ZICOND-NEXT: or a0, a0, a2
2266 ; RV32ZICOND-NEXT: czero.nez a2, a3, a4
2267 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a4
2268 ; RV32ZICOND-NEXT: or a1, a1, a2
2269 ; RV32ZICOND-NEXT: ret
2270 ;
2271 ; RV64ZICOND-LABEL: saddo.select.i64:
2272 ; RV64ZICOND: # %bb.0: # %entry
2273 ; RV64ZICOND-NEXT: add a2, a0, a1
2274 ; RV64ZICOND-NEXT: slt a2, a2, a0
2275 ; RV64ZICOND-NEXT: slti a3, a1, 0
2276 ; RV64ZICOND-NEXT: xor a2, a3, a2
2277 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2
2278 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
2279 ; RV64ZICOND-NEXT: or a0, a0, a1
2280 ; RV64ZICOND-NEXT: ret
2281 entry:
2282 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
2283 %obit = extractvalue {i64, i1} %t, 1
2284 %ret = select i1 %obit, i64 %v1, i64 %v2
2285 ret i64 %ret
2286 }
2288 define i1 @saddo.not.i64(i64 %v1, i64 %v2) {
2289 ; RV32-LABEL: saddo.not.i64:
2290 ; RV32: # %bb.0: # %entry
2291 ; RV32-NEXT: add a4, a1, a3
2292 ; RV32-NEXT: add a2, a0, a2
2293 ; RV32-NEXT: sltu a0, a2, a0
2294 ; RV32-NEXT: add a0, a4, a0
2295 ; RV32-NEXT: xor a0, a1, a0
2296 ; RV32-NEXT: xor a1, a1, a3
2297 ; RV32-NEXT: not a1, a1
2298 ; RV32-NEXT: and a0, a1, a0
2299 ; RV32-NEXT: slti a0, a0, 0
2300 ; RV32-NEXT: xori a0, a0, 1
2301 ; RV32-NEXT: ret
2302 ;
2303 ; RV64-LABEL: saddo.not.i64:
2304 ; RV64: # %bb.0: # %entry
2305 ; RV64-NEXT: add a2, a0, a1
2306 ; RV64-NEXT: slt a0, a2, a0
2307 ; RV64-NEXT: slti a1, a1, 0
2308 ; RV64-NEXT: xor a0, a1, a0
2309 ; RV64-NEXT: xori a0, a0, 1
2310 ; RV64-NEXT: ret
2311 ;
2312 ; RV32ZBA-LABEL: saddo.not.i64:
2313 ; RV32ZBA: # %bb.0: # %entry
2314 ; RV32ZBA-NEXT: add a4, a1, a3
2315 ; RV32ZBA-NEXT: add a2, a0, a2
2316 ; RV32ZBA-NEXT: sltu a0, a2, a0
2317 ; RV32ZBA-NEXT: add a0, a4, a0
2318 ; RV32ZBA-NEXT: xor a0, a1, a0
2319 ; RV32ZBA-NEXT: xor a1, a1, a3
2320 ; RV32ZBA-NEXT: not a1, a1
2321 ; RV32ZBA-NEXT: and a0, a1, a0
2322 ; RV32ZBA-NEXT: slti a0, a0, 0
2323 ; RV32ZBA-NEXT: xori a0, a0, 1
2324 ; RV32ZBA-NEXT: ret
2325 ;
2326 ; RV64ZBA-LABEL: saddo.not.i64:
2327 ; RV64ZBA: # %bb.0: # %entry
2328 ; RV64ZBA-NEXT: add a2, a0, a1
2329 ; RV64ZBA-NEXT: slt a0, a2, a0
2330 ; RV64ZBA-NEXT: slti a1, a1, 0
2331 ; RV64ZBA-NEXT: xor a0, a1, a0
2332 ; RV64ZBA-NEXT: xori a0, a0, 1
2333 ; RV64ZBA-NEXT: ret
2334 ;
2335 ; RV32ZICOND-LABEL: saddo.not.i64:
2336 ; RV32ZICOND: # %bb.0: # %entry
2337 ; RV32ZICOND-NEXT: add a4, a1, a3
2338 ; RV32ZICOND-NEXT: add a2, a0, a2
2339 ; RV32ZICOND-NEXT: sltu a0, a2, a0
2340 ; RV32ZICOND-NEXT: add a0, a4, a0
2341 ; RV32ZICOND-NEXT: xor a0, a1, a0
2342 ; RV32ZICOND-NEXT: xor a1, a1, a3
2343 ; RV32ZICOND-NEXT: not a1, a1
2344 ; RV32ZICOND-NEXT: and a0, a1, a0
2345 ; RV32ZICOND-NEXT: slti a0, a0, 0
2346 ; RV32ZICOND-NEXT: xori a0, a0, 1
2347 ; RV32ZICOND-NEXT: ret
2348 ;
2349 ; RV64ZICOND-LABEL: saddo.not.i64:
2350 ; RV64ZICOND: # %bb.0: # %entry
2351 ; RV64ZICOND-NEXT: add a2, a0, a1
2352 ; RV64ZICOND-NEXT: slt a0, a2, a0
2353 ; RV64ZICOND-NEXT: slti a1, a1, 0
2354 ; RV64ZICOND-NEXT: xor a0, a1, a0
2355 ; RV64ZICOND-NEXT: xori a0, a0, 1
2356 ; RV64ZICOND-NEXT: ret
2357 entry:
2358 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
2359 %obit = extractvalue {i64, i1} %t, 1
2360 %ret = xor i1 %obit, true
2361 ret i1 %ret
2362 }
2364 define i32 @uaddo.select.i32(i32 signext %v1, i32 signext %v2) {
2365 ; RV32-LABEL: uaddo.select.i32:
2366 ; RV32: # %bb.0: # %entry
2367 ; RV32-NEXT: add a2, a0, a1
2368 ; RV32-NEXT: bltu a2, a0, .LBB32_2
2369 ; RV32-NEXT: # %bb.1: # %entry
2370 ; RV32-NEXT: mv a0, a1
2371 ; RV32-NEXT: .LBB32_2: # %entry
2372 ; RV32-NEXT: ret
2373 ;
2374 ; RV64-LABEL: uaddo.select.i32:
2375 ; RV64: # %bb.0: # %entry
2376 ; RV64-NEXT: addw a2, a0, a1
2377 ; RV64-NEXT: bltu a2, a0, .LBB32_2
2378 ; RV64-NEXT: # %bb.1: # %entry
2379 ; RV64-NEXT: mv a0, a1
2380 ; RV64-NEXT: .LBB32_2: # %entry
2381 ; RV64-NEXT: ret
2382 ;
2383 ; RV32ZBA-LABEL: uaddo.select.i32:
2384 ; RV32ZBA: # %bb.0: # %entry
2385 ; RV32ZBA-NEXT: add a2, a0, a1
2386 ; RV32ZBA-NEXT: bltu a2, a0, .LBB32_2
2387 ; RV32ZBA-NEXT: # %bb.1: # %entry
2388 ; RV32ZBA-NEXT: mv a0, a1
2389 ; RV32ZBA-NEXT: .LBB32_2: # %entry
2390 ; RV32ZBA-NEXT: ret
2391 ;
2392 ; RV64ZBA-LABEL: uaddo.select.i32:
2393 ; RV64ZBA: # %bb.0: # %entry
2394 ; RV64ZBA-NEXT: addw a2, a0, a1
2395 ; RV64ZBA-NEXT: bltu a2, a0, .LBB32_2
2396 ; RV64ZBA-NEXT: # %bb.1: # %entry
2397 ; RV64ZBA-NEXT: mv a0, a1
2398 ; RV64ZBA-NEXT: .LBB32_2: # %entry
2399 ; RV64ZBA-NEXT: ret
2400 ;
2401 ; RV32ZICOND-LABEL: uaddo.select.i32:
2402 ; RV32ZICOND: # %bb.0: # %entry
2403 ; RV32ZICOND-NEXT: add a2, a0, a1
2404 ; RV32ZICOND-NEXT: sltu a2, a2, a0
2405 ; RV32ZICOND-NEXT: czero.nez a1, a1, a2
2406 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a2
2407 ; RV32ZICOND-NEXT: or a0, a0, a1
2408 ; RV32ZICOND-NEXT: ret
2409 ;
2410 ; RV64ZICOND-LABEL: uaddo.select.i32:
2411 ; RV64ZICOND: # %bb.0: # %entry
2412 ; RV64ZICOND-NEXT: addw a2, a0, a1
2413 ; RV64ZICOND-NEXT: sltu a2, a2, a0
2414 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2
2415 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
2416 ; RV64ZICOND-NEXT: or a0, a0, a1
2417 ; RV64ZICOND-NEXT: ret
2418 entry:
2419 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
2420 %obit = extractvalue {i32, i1} %t, 1
2421 %ret = select i1 %obit, i32 %v1, i32 %v2
2422 ret i32 %ret
2423 }
2425 define i1 @uaddo.not.i32(i32 signext %v1, i32 signext %v2) {
2426 ; RV32-LABEL: uaddo.not.i32:
2427 ; RV32: # %bb.0: # %entry
2428 ; RV32-NEXT: add a1, a0, a1
2429 ; RV32-NEXT: sltu a0, a1, a0
2430 ; RV32-NEXT: xori a0, a0, 1
2431 ; RV32-NEXT: ret
2432 ;
2433 ; RV64-LABEL: uaddo.not.i32:
2434 ; RV64: # %bb.0: # %entry
2435 ; RV64-NEXT: addw a1, a0, a1
2436 ; RV64-NEXT: sltu a0, a1, a0
2437 ; RV64-NEXT: xori a0, a0, 1
2438 ; RV64-NEXT: ret
2439 ;
2440 ; RV32ZBA-LABEL: uaddo.not.i32:
2441 ; RV32ZBA: # %bb.0: # %entry
2442 ; RV32ZBA-NEXT: add a1, a0, a1
2443 ; RV32ZBA-NEXT: sltu a0, a1, a0
2444 ; RV32ZBA-NEXT: xori a0, a0, 1
2445 ; RV32ZBA-NEXT: ret
2446 ;
2447 ; RV64ZBA-LABEL: uaddo.not.i32:
2448 ; RV64ZBA: # %bb.0: # %entry
2449 ; RV64ZBA-NEXT: addw a1, a0, a1
2450 ; RV64ZBA-NEXT: sltu a0, a1, a0
2451 ; RV64ZBA-NEXT: xori a0, a0, 1
2452 ; RV64ZBA-NEXT: ret
2453 ;
2454 ; RV32ZICOND-LABEL: uaddo.not.i32:
2455 ; RV32ZICOND: # %bb.0: # %entry
2456 ; RV32ZICOND-NEXT: add a1, a0, a1
2457 ; RV32ZICOND-NEXT: sltu a0, a1, a0
2458 ; RV32ZICOND-NEXT: xori a0, a0, 1
2459 ; RV32ZICOND-NEXT: ret
2460 ;
2461 ; RV64ZICOND-LABEL: uaddo.not.i32:
2462 ; RV64ZICOND: # %bb.0: # %entry
2463 ; RV64ZICOND-NEXT: addw a1, a0, a1
2464 ; RV64ZICOND-NEXT: sltu a0, a1, a0
2465 ; RV64ZICOND-NEXT: xori a0, a0, 1
2466 ; RV64ZICOND-NEXT: ret
2467 entry:
2468 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
2469 %obit = extractvalue {i32, i1} %t, 1
2470 %ret = xor i1 %obit, true
2471 ret i1 %ret
2472 }
2474 define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
2475 ; RV32-LABEL: uaddo.select.i64:
2476 ; RV32: # %bb.0: # %entry
2477 ; RV32-NEXT: add a5, a1, a3
2478 ; RV32-NEXT: add a4, a0, a2
2479 ; RV32-NEXT: sltu a4, a4, a0
2480 ; RV32-NEXT: add a5, a5, a4
2481 ; RV32-NEXT: bne a5, a1, .LBB34_3
2482 ; RV32-NEXT: # %bb.1: # %entry
2483 ; RV32-NEXT: beqz a4, .LBB34_4
2484 ; RV32-NEXT: .LBB34_2: # %entry
2485 ; RV32-NEXT: ret
2486 ; RV32-NEXT: .LBB34_3: # %entry
2487 ; RV32-NEXT: sltu a4, a5, a1
2488 ; RV32-NEXT: bnez a4, .LBB34_2
2489 ; RV32-NEXT: .LBB34_4: # %entry
2490 ; RV32-NEXT: mv a0, a2
2491 ; RV32-NEXT: mv a1, a3
2492 ; RV32-NEXT: ret
2493 ;
2494 ; RV64-LABEL: uaddo.select.i64:
2495 ; RV64: # %bb.0: # %entry
2496 ; RV64-NEXT: add a2, a0, a1
2497 ; RV64-NEXT: bltu a2, a0, .LBB34_2
2498 ; RV64-NEXT: # %bb.1: # %entry
2499 ; RV64-NEXT: mv a0, a1
2500 ; RV64-NEXT: .LBB34_2: # %entry
2501 ; RV64-NEXT: ret
2502 ;
2503 ; RV32ZBA-LABEL: uaddo.select.i64:
2504 ; RV32ZBA: # %bb.0: # %entry
2505 ; RV32ZBA-NEXT: add a5, a1, a3
2506 ; RV32ZBA-NEXT: add a4, a0, a2
2507 ; RV32ZBA-NEXT: sltu a4, a4, a0
2508 ; RV32ZBA-NEXT: add a5, a5, a4
2509 ; RV32ZBA-NEXT: bne a5, a1, .LBB34_3
2510 ; RV32ZBA-NEXT: # %bb.1: # %entry
2511 ; RV32ZBA-NEXT: beqz a4, .LBB34_4
2512 ; RV32ZBA-NEXT: .LBB34_2: # %entry
2513 ; RV32ZBA-NEXT: ret
2514 ; RV32ZBA-NEXT: .LBB34_3: # %entry
2515 ; RV32ZBA-NEXT: sltu a4, a5, a1
2516 ; RV32ZBA-NEXT: bnez a4, .LBB34_2
2517 ; RV32ZBA-NEXT: .LBB34_4: # %entry
2518 ; RV32ZBA-NEXT: mv a0, a2
2519 ; RV32ZBA-NEXT: mv a1, a3
2520 ; RV32ZBA-NEXT: ret
2521 ;
2522 ; RV64ZBA-LABEL: uaddo.select.i64:
2523 ; RV64ZBA: # %bb.0: # %entry
2524 ; RV64ZBA-NEXT: add a2, a0, a1
2525 ; RV64ZBA-NEXT: bltu a2, a0, .LBB34_2
2526 ; RV64ZBA-NEXT: # %bb.1: # %entry
2527 ; RV64ZBA-NEXT: mv a0, a1
2528 ; RV64ZBA-NEXT: .LBB34_2: # %entry
2529 ; RV64ZBA-NEXT: ret
2530 ;
2531 ; RV32ZICOND-LABEL: uaddo.select.i64:
2532 ; RV32ZICOND: # %bb.0: # %entry
2533 ; RV32ZICOND-NEXT: add a4, a1, a3
2534 ; RV32ZICOND-NEXT: add a5, a0, a2
2535 ; RV32ZICOND-NEXT: sltu a5, a5, a0
2536 ; RV32ZICOND-NEXT: add a4, a4, a5
2537 ; RV32ZICOND-NEXT: xor a6, a4, a1
2538 ; RV32ZICOND-NEXT: sltu a4, a4, a1
2539 ; RV32ZICOND-NEXT: czero.eqz a4, a4, a6
2540 ; RV32ZICOND-NEXT: czero.nez a5, a5, a6
2541 ; RV32ZICOND-NEXT: or a4, a5, a4
2542 ; RV32ZICOND-NEXT: czero.nez a2, a2, a4
2543 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a4
2544 ; RV32ZICOND-NEXT: or a0, a0, a2
2545 ; RV32ZICOND-NEXT: czero.nez a2, a3, a4
2546 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a4
2547 ; RV32ZICOND-NEXT: or a1, a1, a2
2548 ; RV32ZICOND-NEXT: ret
2549 ;
2550 ; RV64ZICOND-LABEL: uaddo.select.i64:
2551 ; RV64ZICOND: # %bb.0: # %entry
2552 ; RV64ZICOND-NEXT: add a2, a0, a1
2553 ; RV64ZICOND-NEXT: sltu a2, a2, a0
2554 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2
2555 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
2556 ; RV64ZICOND-NEXT: or a0, a0, a1
2557 ; RV64ZICOND-NEXT: ret
2558 entry:
2559 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
2560 %obit = extractvalue {i64, i1} %t, 1
2561 %ret = select i1 %obit, i64 %v1, i64 %v2
2562 ret i64 %ret
2563 }
2565 define i1 @uaddo.not.i64(i64 %v1, i64 %v2) {
2566 ; RV32-LABEL: uaddo.not.i64:
2567 ; RV32: # %bb.0: # %entry
2568 ; RV32-NEXT: add a3, a1, a3
2569 ; RV32-NEXT: add a2, a0, a2
2570 ; RV32-NEXT: sltu a0, a2, a0
2571 ; RV32-NEXT: add a2, a3, a0
2572 ; RV32-NEXT: beq a2, a1, .LBB35_2
2573 ; RV32-NEXT: # %bb.1: # %entry
2574 ; RV32-NEXT: sltu a0, a2, a1
2575 ; RV32-NEXT: .LBB35_2: # %entry
2576 ; RV32-NEXT: xori a0, a0, 1
2577 ; RV32-NEXT: ret
2578 ;
2579 ; RV64-LABEL: uaddo.not.i64:
2580 ; RV64: # %bb.0: # %entry
2581 ; RV64-NEXT: add a1, a0, a1
2582 ; RV64-NEXT: sltu a0, a1, a0
2583 ; RV64-NEXT: xori a0, a0, 1
2584 ; RV64-NEXT: ret
2585 ;
2586 ; RV32ZBA-LABEL: uaddo.not.i64:
2587 ; RV32ZBA: # %bb.0: # %entry
2588 ; RV32ZBA-NEXT: add a3, a1, a3
2589 ; RV32ZBA-NEXT: add a2, a0, a2
2590 ; RV32ZBA-NEXT: sltu a0, a2, a0
2591 ; RV32ZBA-NEXT: add a2, a3, a0
2592 ; RV32ZBA-NEXT: beq a2, a1, .LBB35_2
2593 ; RV32ZBA-NEXT: # %bb.1: # %entry
2594 ; RV32ZBA-NEXT: sltu a0, a2, a1
2595 ; RV32ZBA-NEXT: .LBB35_2: # %entry
2596 ; RV32ZBA-NEXT: xori a0, a0, 1
2597 ; RV32ZBA-NEXT: ret
2598 ;
2599 ; RV64ZBA-LABEL: uaddo.not.i64:
2600 ; RV64ZBA: # %bb.0: # %entry
2601 ; RV64ZBA-NEXT: add a1, a0, a1
2602 ; RV64ZBA-NEXT: sltu a0, a1, a0
2603 ; RV64ZBA-NEXT: xori a0, a0, 1
2604 ; RV64ZBA-NEXT: ret
2605 ;
2606 ; RV32ZICOND-LABEL: uaddo.not.i64:
2607 ; RV32ZICOND: # %bb.0: # %entry
2608 ; RV32ZICOND-NEXT: add a3, a1, a3
2609 ; RV32ZICOND-NEXT: add a2, a0, a2
2610 ; RV32ZICOND-NEXT: sltu a0, a2, a0
2611 ; RV32ZICOND-NEXT: add a3, a3, a0
2612 ; RV32ZICOND-NEXT: xor a2, a3, a1
2613 ; RV32ZICOND-NEXT: sltu a1, a3, a1
2614 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a2
2615 ; RV32ZICOND-NEXT: czero.nez a0, a0, a2
2616 ; RV32ZICOND-NEXT: or a0, a0, a1
2617 ; RV32ZICOND-NEXT: xori a0, a0, 1
2618 ; RV32ZICOND-NEXT: ret
2619 ;
2620 ; RV64ZICOND-LABEL: uaddo.not.i64:
2621 ; RV64ZICOND: # %bb.0: # %entry
2622 ; RV64ZICOND-NEXT: add a1, a0, a1
2623 ; RV64ZICOND-NEXT: sltu a0, a1, a0
2624 ; RV64ZICOND-NEXT: xori a0, a0, 1
2625 ; RV64ZICOND-NEXT: ret
2626 entry:
2627 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
2628 %obit = extractvalue {i64, i1} %t, 1
2629 %ret = xor i1 %obit, true
2630 ret i1 %ret
2631 }
2633 define i32 @ssubo.select.i32(i32 signext %v1, i32 signext %v2) {
2634 ; RV32-LABEL: ssubo.select.i32:
2635 ; RV32: # %bb.0: # %entry
2636 ; RV32-NEXT: sgtz a2, a1
2637 ; RV32-NEXT: sub a3, a0, a1
2638 ; RV32-NEXT: slt a3, a3, a0
2639 ; RV32-NEXT: bne a2, a3, .LBB36_2
2640 ; RV32-NEXT: # %bb.1: # %entry
2641 ; RV32-NEXT: mv a0, a1
2642 ; RV32-NEXT: .LBB36_2: # %entry
2643 ; RV32-NEXT: ret
2644 ;
2645 ; RV64-LABEL: ssubo.select.i32:
2646 ; RV64: # %bb.0: # %entry
2647 ; RV64-NEXT: sub a2, a0, a1
2648 ; RV64-NEXT: subw a3, a0, a1
2649 ; RV64-NEXT: bne a3, a2, .LBB36_2
2650 ; RV64-NEXT: # %bb.1: # %entry
2651 ; RV64-NEXT: mv a0, a1
2652 ; RV64-NEXT: .LBB36_2: # %entry
2653 ; RV64-NEXT: ret
2654 ;
2655 ; RV32ZBA-LABEL: ssubo.select.i32:
2656 ; RV32ZBA: # %bb.0: # %entry
2657 ; RV32ZBA-NEXT: sgtz a2, a1
2658 ; RV32ZBA-NEXT: sub a3, a0, a1
2659 ; RV32ZBA-NEXT: slt a3, a3, a0
2660 ; RV32ZBA-NEXT: bne a2, a3, .LBB36_2
2661 ; RV32ZBA-NEXT: # %bb.1: # %entry
2662 ; RV32ZBA-NEXT: mv a0, a1
2663 ; RV32ZBA-NEXT: .LBB36_2: # %entry
2664 ; RV32ZBA-NEXT: ret
2665 ;
2666 ; RV64ZBA-LABEL: ssubo.select.i32:
2667 ; RV64ZBA: # %bb.0: # %entry
2668 ; RV64ZBA-NEXT: sub a2, a0, a1
2669 ; RV64ZBA-NEXT: subw a3, a0, a1
2670 ; RV64ZBA-NEXT: bne a3, a2, .LBB36_2
2671 ; RV64ZBA-NEXT: # %bb.1: # %entry
2672 ; RV64ZBA-NEXT: mv a0, a1
2673 ; RV64ZBA-NEXT: .LBB36_2: # %entry
2674 ; RV64ZBA-NEXT: ret
2675 ;
2676 ; RV32ZICOND-LABEL: ssubo.select.i32:
2677 ; RV32ZICOND: # %bb.0: # %entry
2678 ; RV32ZICOND-NEXT: sgtz a2, a1
2679 ; RV32ZICOND-NEXT: sub a3, a0, a1
2680 ; RV32ZICOND-NEXT: slt a3, a3, a0
2681 ; RV32ZICOND-NEXT: xor a2, a2, a3
2682 ; RV32ZICOND-NEXT: czero.nez a1, a1, a2
2683 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a2
2684 ; RV32ZICOND-NEXT: or a0, a0, a1
2685 ; RV32ZICOND-NEXT: ret
2686 ;
2687 ; RV64ZICOND-LABEL: ssubo.select.i32:
2688 ; RV64ZICOND: # %bb.0: # %entry
2689 ; RV64ZICOND-NEXT: sub a2, a0, a1
2690 ; RV64ZICOND-NEXT: subw a3, a0, a1
2691 ; RV64ZICOND-NEXT: xor a2, a3, a2
2692 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2
2693 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
2694 ; RV64ZICOND-NEXT: or a0, a0, a1
2695 ; RV64ZICOND-NEXT: ret
2696 entry:
2697 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
2698 %obit = extractvalue {i32, i1} %t, 1
2699 %ret = select i1 %obit, i32 %v1, i32 %v2
2700 ret i32 %ret
2701 }
2703 define i1 @ssubo.not.i32(i32 signext %v1, i32 signext %v2) {
2704 ; RV32-LABEL: ssubo.not.i32:
2705 ; RV32: # %bb.0: # %entry
2706 ; RV32-NEXT: sgtz a2, a1
2707 ; RV32-NEXT: sub a1, a0, a1
2708 ; RV32-NEXT: slt a0, a1, a0
2709 ; RV32-NEXT: xor a0, a2, a0
2710 ; RV32-NEXT: xori a0, a0, 1
2711 ; RV32-NEXT: ret
2712 ;
2713 ; RV64-LABEL: ssubo.not.i32:
2714 ; RV64: # %bb.0: # %entry
2715 ; RV64-NEXT: sub a2, a0, a1
2716 ; RV64-NEXT: subw a0, a0, a1
2717 ; RV64-NEXT: xor a0, a0, a2
2718 ; RV64-NEXT: seqz a0, a0
2719 ; RV64-NEXT: ret
2720 ;
2721 ; RV32ZBA-LABEL: ssubo.not.i32:
2722 ; RV32ZBA: # %bb.0: # %entry
2723 ; RV32ZBA-NEXT: sgtz a2, a1
2724 ; RV32ZBA-NEXT: sub a1, a0, a1
2725 ; RV32ZBA-NEXT: slt a0, a1, a0
2726 ; RV32ZBA-NEXT: xor a0, a2, a0
2727 ; RV32ZBA-NEXT: xori a0, a0, 1
2728 ; RV32ZBA-NEXT: ret
2729 ;
2730 ; RV64ZBA-LABEL: ssubo.not.i32:
2731 ; RV64ZBA: # %bb.0: # %entry
2732 ; RV64ZBA-NEXT: sub a2, a0, a1
2733 ; RV64ZBA-NEXT: subw a0, a0, a1
2734 ; RV64ZBA-NEXT: xor a0, a0, a2
2735 ; RV64ZBA-NEXT: seqz a0, a0
2736 ; RV64ZBA-NEXT: ret
2737 ;
2738 ; RV32ZICOND-LABEL: ssubo.not.i32:
2739 ; RV32ZICOND: # %bb.0: # %entry
2740 ; RV32ZICOND-NEXT: sgtz a2, a1
2741 ; RV32ZICOND-NEXT: sub a1, a0, a1
2742 ; RV32ZICOND-NEXT: slt a0, a1, a0
2743 ; RV32ZICOND-NEXT: xor a0, a2, a0
2744 ; RV32ZICOND-NEXT: xori a0, a0, 1
2745 ; RV32ZICOND-NEXT: ret
2746 ;
2747 ; RV64ZICOND-LABEL: ssubo.not.i32:
2748 ; RV64ZICOND: # %bb.0: # %entry
2749 ; RV64ZICOND-NEXT: sub a2, a0, a1
2750 ; RV64ZICOND-NEXT: subw a0, a0, a1
2751 ; RV64ZICOND-NEXT: xor a0, a0, a2
2752 ; RV64ZICOND-NEXT: seqz a0, a0
2753 ; RV64ZICOND-NEXT: ret
2754 entry:
2755 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
2756 %obit = extractvalue {i32, i1} %t, 1
2757 %ret = xor i1 %obit, true
2758 ret i1 %ret
2759 }
2761 define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
2762 ; RV32-LABEL: ssubo.select.i64:
2763 ; RV32: # %bb.0: # %entry
2764 ; RV32-NEXT: sltu a4, a0, a2
2765 ; RV32-NEXT: sub a5, a1, a3
2766 ; RV32-NEXT: sub a5, a5, a4
2767 ; RV32-NEXT: xor a5, a1, a5
2768 ; RV32-NEXT: xor a4, a1, a3
2769 ; RV32-NEXT: and a4, a4, a5
2770 ; RV32-NEXT: bltz a4, .LBB38_2
2771 ; RV32-NEXT: # %bb.1: # %entry
2772 ; RV32-NEXT: mv a0, a2
2773 ; RV32-NEXT: mv a1, a3
2774 ; RV32-NEXT: .LBB38_2: # %entry
2775 ; RV32-NEXT: ret
2776 ;
2777 ; RV64-LABEL: ssubo.select.i64:
2778 ; RV64: # %bb.0: # %entry
2779 ; RV64-NEXT: sgtz a2, a1
2780 ; RV64-NEXT: sub a3, a0, a1
2781 ; RV64-NEXT: slt a3, a3, a0
2782 ; RV64-NEXT: bne a2, a3, .LBB38_2
2783 ; RV64-NEXT: # %bb.1: # %entry
2784 ; RV64-NEXT: mv a0, a1
2785 ; RV64-NEXT: .LBB38_2: # %entry
2786 ; RV64-NEXT: ret
2787 ;
2788 ; RV32ZBA-LABEL: ssubo.select.i64:
2789 ; RV32ZBA: # %bb.0: # %entry
2790 ; RV32ZBA-NEXT: sltu a4, a0, a2
2791 ; RV32ZBA-NEXT: sub a5, a1, a3
2792 ; RV32ZBA-NEXT: sub a5, a5, a4
2793 ; RV32ZBA-NEXT: xor a5, a1, a5
2794 ; RV32ZBA-NEXT: xor a4, a1, a3
2795 ; RV32ZBA-NEXT: and a4, a4, a5
2796 ; RV32ZBA-NEXT: bltz a4, .LBB38_2
2797 ; RV32ZBA-NEXT: # %bb.1: # %entry
2798 ; RV32ZBA-NEXT: mv a0, a2
2799 ; RV32ZBA-NEXT: mv a1, a3
2800 ; RV32ZBA-NEXT: .LBB38_2: # %entry
2801 ; RV32ZBA-NEXT: ret
2802 ;
2803 ; RV64ZBA-LABEL: ssubo.select.i64:
2804 ; RV64ZBA: # %bb.0: # %entry
2805 ; RV64ZBA-NEXT: sgtz a2, a1
2806 ; RV64ZBA-NEXT: sub a3, a0, a1
2807 ; RV64ZBA-NEXT: slt a3, a3, a0
2808 ; RV64ZBA-NEXT: bne a2, a3, .LBB38_2
2809 ; RV64ZBA-NEXT: # %bb.1: # %entry
2810 ; RV64ZBA-NEXT: mv a0, a1
2811 ; RV64ZBA-NEXT: .LBB38_2: # %entry
2812 ; RV64ZBA-NEXT: ret
2813 ;
2814 ; RV32ZICOND-LABEL: ssubo.select.i64:
2815 ; RV32ZICOND: # %bb.0: # %entry
2816 ; RV32ZICOND-NEXT: sltu a4, a0, a2
2817 ; RV32ZICOND-NEXT: sub a5, a1, a3
2818 ; RV32ZICOND-NEXT: sub a5, a5, a4
2819 ; RV32ZICOND-NEXT: xor a5, a1, a5
2820 ; RV32ZICOND-NEXT: xor a4, a1, a3
2821 ; RV32ZICOND-NEXT: and a4, a4, a5
2822 ; RV32ZICOND-NEXT: slti a4, a4, 0
2823 ; RV32ZICOND-NEXT: czero.nez a2, a2, a4
2824 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a4
2825 ; RV32ZICOND-NEXT: or a0, a0, a2
2826 ; RV32ZICOND-NEXT: czero.nez a2, a3, a4
2827 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a4
2828 ; RV32ZICOND-NEXT: or a1, a1, a2
2829 ; RV32ZICOND-NEXT: ret
2830 ;
2831 ; RV64ZICOND-LABEL: ssubo.select.i64:
2832 ; RV64ZICOND: # %bb.0: # %entry
2833 ; RV64ZICOND-NEXT: sgtz a2, a1
2834 ; RV64ZICOND-NEXT: sub a3, a0, a1
2835 ; RV64ZICOND-NEXT: slt a3, a3, a0
2836 ; RV64ZICOND-NEXT: xor a2, a2, a3
2837 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2
2838 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
2839 ; RV64ZICOND-NEXT: or a0, a0, a1
2840 ; RV64ZICOND-NEXT: ret
2841 entry:
2842 %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
2843 %obit = extractvalue {i64, i1} %t, 1
2844 %ret = select i1 %obit, i64 %v1, i64 %v2
2845 ret i64 %ret
2846 }
2848 define i1 @ssub.not.i64(i64 %v1, i64 %v2) {
2849 ; RV32-LABEL: ssub.not.i64:
2850 ; RV32: # %bb.0: # %entry
2851 ; RV32-NEXT: sltu a0, a0, a2
2852 ; RV32-NEXT: sub a2, a1, a3
2853 ; RV32-NEXT: sub a2, a2, a0
2854 ; RV32-NEXT: xor a2, a1, a2
2855 ; RV32-NEXT: xor a1, a1, a3
2856 ; RV32-NEXT: and a1, a1, a2
2857 ; RV32-NEXT: slti a0, a1, 0
2858 ; RV32-NEXT: xori a0, a0, 1
2859 ; RV32-NEXT: ret
2860 ;
2861 ; RV64-LABEL: ssub.not.i64:
2862 ; RV64: # %bb.0: # %entry
2863 ; RV64-NEXT: sgtz a2, a1
2864 ; RV64-NEXT: sub a1, a0, a1
2865 ; RV64-NEXT: slt a0, a1, a0
2866 ; RV64-NEXT: xor a0, a2, a0
2867 ; RV64-NEXT: xori a0, a0, 1
2868 ; RV64-NEXT: ret
2869 ;
2870 ; RV32ZBA-LABEL: ssub.not.i64:
2871 ; RV32ZBA: # %bb.0: # %entry
2872 ; RV32ZBA-NEXT: sltu a0, a0, a2
2873 ; RV32ZBA-NEXT: sub a2, a1, a3
2874 ; RV32ZBA-NEXT: sub a2, a2, a0
2875 ; RV32ZBA-NEXT: xor a2, a1, a2
2876 ; RV32ZBA-NEXT: xor a1, a1, a3
2877 ; RV32ZBA-NEXT: and a1, a1, a2
2878 ; RV32ZBA-NEXT: slti a0, a1, 0
2879 ; RV32ZBA-NEXT: xori a0, a0, 1
2880 ; RV32ZBA-NEXT: ret
2881 ;
2882 ; RV64ZBA-LABEL: ssub.not.i64:
2883 ; RV64ZBA: # %bb.0: # %entry
2884 ; RV64ZBA-NEXT: sgtz a2, a1
2885 ; RV64ZBA-NEXT: sub a1, a0, a1
2886 ; RV64ZBA-NEXT: slt a0, a1, a0
2887 ; RV64ZBA-NEXT: xor a0, a2, a0
2888 ; RV64ZBA-NEXT: xori a0, a0, 1
2889 ; RV64ZBA-NEXT: ret
2890 ;
2891 ; RV32ZICOND-LABEL: ssub.not.i64:
2892 ; RV32ZICOND: # %bb.0: # %entry
2893 ; RV32ZICOND-NEXT: sltu a0, a0, a2
2894 ; RV32ZICOND-NEXT: sub a2, a1, a3
2895 ; RV32ZICOND-NEXT: sub a2, a2, a0
2896 ; RV32ZICOND-NEXT: xor a2, a1, a2
2897 ; RV32ZICOND-NEXT: xor a1, a1, a3
2898 ; RV32ZICOND-NEXT: and a1, a1, a2
2899 ; RV32ZICOND-NEXT: slti a0, a1, 0
2900 ; RV32ZICOND-NEXT: xori a0, a0, 1
2901 ; RV32ZICOND-NEXT: ret
2902 ;
2903 ; RV64ZICOND-LABEL: ssub.not.i64:
2904 ; RV64ZICOND: # %bb.0: # %entry
2905 ; RV64ZICOND-NEXT: sgtz a2, a1
2906 ; RV64ZICOND-NEXT: sub a1, a0, a1
2907 ; RV64ZICOND-NEXT: slt a0, a1, a0
2908 ; RV64ZICOND-NEXT: xor a0, a2, a0
2909 ; RV64ZICOND-NEXT: xori a0, a0, 1
2910 ; RV64ZICOND-NEXT: ret
2911 entry:
2912 %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
2913 %obit = extractvalue {i64, i1} %t, 1
2914 %ret = xor i1 %obit, true
2915 ret i1 %ret
2916 }
2918 define i32 @usubo.select.i32(i32 signext %v1, i32 signext %v2) {
2919 ; RV32-LABEL: usubo.select.i32:
2920 ; RV32: # %bb.0: # %entry
2921 ; RV32-NEXT: sub a2, a0, a1
2922 ; RV32-NEXT: bltu a0, a2, .LBB40_2
2923 ; RV32-NEXT: # %bb.1: # %entry
2924 ; RV32-NEXT: mv a0, a1
2925 ; RV32-NEXT: .LBB40_2: # %entry
2926 ; RV32-NEXT: ret
2927 ;
2928 ; RV64-LABEL: usubo.select.i32:
2929 ; RV64: # %bb.0: # %entry
2930 ; RV64-NEXT: subw a2, a0, a1
2931 ; RV64-NEXT: bltu a0, a2, .LBB40_2
2932 ; RV64-NEXT: # %bb.1: # %entry
2933 ; RV64-NEXT: mv a0, a1
2934 ; RV64-NEXT: .LBB40_2: # %entry
2935 ; RV64-NEXT: ret
2936 ;
2937 ; RV32ZBA-LABEL: usubo.select.i32:
2938 ; RV32ZBA: # %bb.0: # %entry
2939 ; RV32ZBA-NEXT: sub a2, a0, a1
2940 ; RV32ZBA-NEXT: bltu a0, a2, .LBB40_2
2941 ; RV32ZBA-NEXT: # %bb.1: # %entry
2942 ; RV32ZBA-NEXT: mv a0, a1
2943 ; RV32ZBA-NEXT: .LBB40_2: # %entry
2944 ; RV32ZBA-NEXT: ret
2945 ;
2946 ; RV64ZBA-LABEL: usubo.select.i32:
2947 ; RV64ZBA: # %bb.0: # %entry
2948 ; RV64ZBA-NEXT: subw a2, a0, a1
2949 ; RV64ZBA-NEXT: bltu a0, a2, .LBB40_2
2950 ; RV64ZBA-NEXT: # %bb.1: # %entry
2951 ; RV64ZBA-NEXT: mv a0, a1
2952 ; RV64ZBA-NEXT: .LBB40_2: # %entry
2953 ; RV64ZBA-NEXT: ret
2954 ;
2955 ; RV32ZICOND-LABEL: usubo.select.i32:
2956 ; RV32ZICOND: # %bb.0: # %entry
2957 ; RV32ZICOND-NEXT: sub a2, a0, a1
2958 ; RV32ZICOND-NEXT: sltu a2, a0, a2
2959 ; RV32ZICOND-NEXT: czero.nez a1, a1, a2
2960 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a2
2961 ; RV32ZICOND-NEXT: or a0, a0, a1
2962 ; RV32ZICOND-NEXT: ret
2963 ;
2964 ; RV64ZICOND-LABEL: usubo.select.i32:
2965 ; RV64ZICOND: # %bb.0: # %entry
2966 ; RV64ZICOND-NEXT: subw a2, a0, a1
2967 ; RV64ZICOND-NEXT: sltu a2, a0, a2
2968 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2
2969 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
2970 ; RV64ZICOND-NEXT: or a0, a0, a1
2971 ; RV64ZICOND-NEXT: ret
2972 entry:
2973 %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
2974 %obit = extractvalue {i32, i1} %t, 1
2975 %ret = select i1 %obit, i32 %v1, i32 %v2
2976 ret i32 %ret
2977 }
2979 define i1 @usubo.not.i32(i32 signext %v1, i32 signext %v2) {
2980 ; RV32-LABEL: usubo.not.i32:
2981 ; RV32: # %bb.0: # %entry
2982 ; RV32-NEXT: sub a1, a0, a1
2983 ; RV32-NEXT: sltu a0, a0, a1
2984 ; RV32-NEXT: xori a0, a0, 1
2985 ; RV32-NEXT: ret
2986 ;
2987 ; RV64-LABEL: usubo.not.i32:
2988 ; RV64: # %bb.0: # %entry
2989 ; RV64-NEXT: subw a1, a0, a1
2990 ; RV64-NEXT: sltu a0, a0, a1
2991 ; RV64-NEXT: xori a0, a0, 1
2992 ; RV64-NEXT: ret
2993 ;
2994 ; RV32ZBA-LABEL: usubo.not.i32:
2995 ; RV32ZBA: # %bb.0: # %entry
2996 ; RV32ZBA-NEXT: sub a1, a0, a1
2997 ; RV32ZBA-NEXT: sltu a0, a0, a1
2998 ; RV32ZBA-NEXT: xori a0, a0, 1
2999 ; RV32ZBA-NEXT: ret
3000 ;
3001 ; RV64ZBA-LABEL: usubo.not.i32:
3002 ; RV64ZBA: # %bb.0: # %entry
3003 ; RV64ZBA-NEXT: subw a1, a0, a1
3004 ; RV64ZBA-NEXT: sltu a0, a0, a1
3005 ; RV64ZBA-NEXT: xori a0, a0, 1
3006 ; RV64ZBA-NEXT: ret
3007 ;
3008 ; RV32ZICOND-LABEL: usubo.not.i32:
3009 ; RV32ZICOND: # %bb.0: # %entry
3010 ; RV32ZICOND-NEXT: sub a1, a0, a1
3011 ; RV32ZICOND-NEXT: sltu a0, a0, a1
3012 ; RV32ZICOND-NEXT: xori a0, a0, 1
3013 ; RV32ZICOND-NEXT: ret
3014 ;
3015 ; RV64ZICOND-LABEL: usubo.not.i32:
3016 ; RV64ZICOND: # %bb.0: # %entry
3017 ; RV64ZICOND-NEXT: subw a1, a0, a1
3018 ; RV64ZICOND-NEXT: sltu a0, a0, a1
3019 ; RV64ZICOND-NEXT: xori a0, a0, 1
3020 ; RV64ZICOND-NEXT: ret
3021 entry:
3022 %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
3023 %obit = extractvalue {i32, i1} %t, 1
3024 %ret = xor i1 %obit, true
3025 ret i1 %ret
3026 }
3028 define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
3029 ; RV32-LABEL: usubo.select.i64:
3030 ; RV32: # %bb.0: # %entry
3031 ; RV32-NEXT: sltu a4, a0, a2
3032 ; RV32-NEXT: sub a5, a1, a3
3033 ; RV32-NEXT: sub a4, a5, a4
3034 ; RV32-NEXT: beq a4, a1, .LBB42_2
3035 ; RV32-NEXT: # %bb.1: # %entry
3036 ; RV32-NEXT: sltu a4, a1, a4
3037 ; RV32-NEXT: beqz a4, .LBB42_3
3038 ; RV32-NEXT: j .LBB42_4
3039 ; RV32-NEXT: .LBB42_2:
3040 ; RV32-NEXT: sub a4, a0, a2
3041 ; RV32-NEXT: sltu a4, a0, a4
3042 ; RV32-NEXT: bnez a4, .LBB42_4
3043 ; RV32-NEXT: .LBB42_3: # %entry
3044 ; RV32-NEXT: mv a0, a2
3045 ; RV32-NEXT: mv a1, a3
3046 ; RV32-NEXT: .LBB42_4: # %entry
3047 ; RV32-NEXT: ret
3048 ;
3049 ; RV64-LABEL: usubo.select.i64:
3050 ; RV64: # %bb.0: # %entry
3051 ; RV64-NEXT: sub a2, a0, a1
3052 ; RV64-NEXT: bltu a0, a2, .LBB42_2
3053 ; RV64-NEXT: # %bb.1: # %entry
3054 ; RV64-NEXT: mv a0, a1
3055 ; RV64-NEXT: .LBB42_2: # %entry
3056 ; RV64-NEXT: ret
3057 ;
3058 ; RV32ZBA-LABEL: usubo.select.i64:
3059 ; RV32ZBA: # %bb.0: # %entry
3060 ; RV32ZBA-NEXT: sltu a4, a0, a2
3061 ; RV32ZBA-NEXT: sub a5, a1, a3
3062 ; RV32ZBA-NEXT: sub a4, a5, a4
3063 ; RV32ZBA-NEXT: beq a4, a1, .LBB42_2
3064 ; RV32ZBA-NEXT: # %bb.1: # %entry
3065 ; RV32ZBA-NEXT: sltu a4, a1, a4
3066 ; RV32ZBA-NEXT: beqz a4, .LBB42_3
3067 ; RV32ZBA-NEXT: j .LBB42_4
3068 ; RV32ZBA-NEXT: .LBB42_2:
3069 ; RV32ZBA-NEXT: sub a4, a0, a2
3070 ; RV32ZBA-NEXT: sltu a4, a0, a4
3071 ; RV32ZBA-NEXT: bnez a4, .LBB42_4
3072 ; RV32ZBA-NEXT: .LBB42_3: # %entry
3073 ; RV32ZBA-NEXT: mv a0, a2
3074 ; RV32ZBA-NEXT: mv a1, a3
3075 ; RV32ZBA-NEXT: .LBB42_4: # %entry
3076 ; RV32ZBA-NEXT: ret
3077 ;
3078 ; RV64ZBA-LABEL: usubo.select.i64:
3079 ; RV64ZBA: # %bb.0: # %entry
3080 ; RV64ZBA-NEXT: sub a2, a0, a1
3081 ; RV64ZBA-NEXT: bltu a0, a2, .LBB42_2
3082 ; RV64ZBA-NEXT: # %bb.1: # %entry
3083 ; RV64ZBA-NEXT: mv a0, a1
3084 ; RV64ZBA-NEXT: .LBB42_2: # %entry
3085 ; RV64ZBA-NEXT: ret
3086 ;
3087 ; RV32ZICOND-LABEL: usubo.select.i64:
3088 ; RV32ZICOND: # %bb.0: # %entry
3089 ; RV32ZICOND-NEXT: sltu a4, a0, a2
3090 ; RV32ZICOND-NEXT: sub a5, a1, a3
3091 ; RV32ZICOND-NEXT: sub a5, a5, a4
3092 ; RV32ZICOND-NEXT: xor a4, a5, a1
3093 ; RV32ZICOND-NEXT: sltu a5, a1, a5
3094 ; RV32ZICOND-NEXT: czero.eqz a5, a5, a4
3095 ; RV32ZICOND-NEXT: sub a6, a0, a2
3096 ; RV32ZICOND-NEXT: sltu a6, a0, a6
3097 ; RV32ZICOND-NEXT: czero.nez a4, a6, a4
3098 ; RV32ZICOND-NEXT: or a4, a4, a5
3099 ; RV32ZICOND-NEXT: czero.nez a2, a2, a4
3100 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a4
3101 ; RV32ZICOND-NEXT: or a0, a0, a2
3102 ; RV32ZICOND-NEXT: czero.nez a2, a3, a4
3103 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a4
3104 ; RV32ZICOND-NEXT: or a1, a1, a2
3105 ; RV32ZICOND-NEXT: ret
3106 ;
3107 ; RV64ZICOND-LABEL: usubo.select.i64:
3108 ; RV64ZICOND: # %bb.0: # %entry
3109 ; RV64ZICOND-NEXT: sub a2, a0, a1
3110 ; RV64ZICOND-NEXT: sltu a2, a0, a2
3111 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2
3112 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
3113 ; RV64ZICOND-NEXT: or a0, a0, a1
3114 ; RV64ZICOND-NEXT: ret
3115 entry:
3116 %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
3117 %obit = extractvalue {i64, i1} %t, 1
3118 %ret = select i1 %obit, i64 %v1, i64 %v2
3119 ret i64 %ret
3120 }
3122 define i1 @usubo.not.i64(i64 %v1, i64 %v2) {
3123 ; RV32-LABEL: usubo.not.i64:
3124 ; RV32: # %bb.0: # %entry
3125 ; RV32-NEXT: sltu a4, a0, a2
3126 ; RV32-NEXT: sub a3, a1, a3
3127 ; RV32-NEXT: sub a3, a3, a4
3128 ; RV32-NEXT: beq a3, a1, .LBB43_2
3129 ; RV32-NEXT: # %bb.1: # %entry
3130 ; RV32-NEXT: sltu a0, a1, a3
3131 ; RV32-NEXT: xori a0, a0, 1
3132 ; RV32-NEXT: ret
3133 ; RV32-NEXT: .LBB43_2:
3134 ; RV32-NEXT: sub a1, a0, a2
3135 ; RV32-NEXT: sltu a0, a0, a1
3136 ; RV32-NEXT: xori a0, a0, 1
3137 ; RV32-NEXT: ret
3138 ;
3139 ; RV64-LABEL: usubo.not.i64:
3140 ; RV64: # %bb.0: # %entry
3141 ; RV64-NEXT: sub a1, a0, a1
3142 ; RV64-NEXT: sltu a0, a0, a1
3143 ; RV64-NEXT: xori a0, a0, 1
3144 ; RV64-NEXT: ret
3145 ;
3146 ; RV32ZBA-LABEL: usubo.not.i64:
3147 ; RV32ZBA: # %bb.0: # %entry
3148 ; RV32ZBA-NEXT: sltu a4, a0, a2
3149 ; RV32ZBA-NEXT: sub a3, a1, a3
3150 ; RV32ZBA-NEXT: sub a3, a3, a4
3151 ; RV32ZBA-NEXT: beq a3, a1, .LBB43_2
3152 ; RV32ZBA-NEXT: # %bb.1: # %entry
3153 ; RV32ZBA-NEXT: sltu a0, a1, a3
3154 ; RV32ZBA-NEXT: xori a0, a0, 1
3155 ; RV32ZBA-NEXT: ret
3156 ; RV32ZBA-NEXT: .LBB43_2:
3157 ; RV32ZBA-NEXT: sub a1, a0, a2
3158 ; RV32ZBA-NEXT: sltu a0, a0, a1
3159 ; RV32ZBA-NEXT: xori a0, a0, 1
3160 ; RV32ZBA-NEXT: ret
3161 ;
3162 ; RV64ZBA-LABEL: usubo.not.i64:
3163 ; RV64ZBA: # %bb.0: # %entry
3164 ; RV64ZBA-NEXT: sub a1, a0, a1
3165 ; RV64ZBA-NEXT: sltu a0, a0, a1
3166 ; RV64ZBA-NEXT: xori a0, a0, 1
3167 ; RV64ZBA-NEXT: ret
3168 ;
3169 ; RV32ZICOND-LABEL: usubo.not.i64:
3170 ; RV32ZICOND: # %bb.0: # %entry
3171 ; RV32ZICOND-NEXT: sltu a4, a0, a2
3172 ; RV32ZICOND-NEXT: sub a3, a1, a3
3173 ; RV32ZICOND-NEXT: sub a3, a3, a4
3174 ; RV32ZICOND-NEXT: xor a4, a3, a1
3175 ; RV32ZICOND-NEXT: sltu a1, a1, a3
3176 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a4
3177 ; RV32ZICOND-NEXT: sub a2, a0, a2
3178 ; RV32ZICOND-NEXT: sltu a0, a0, a2
3179 ; RV32ZICOND-NEXT: czero.nez a0, a0, a4
3180 ; RV32ZICOND-NEXT: or a0, a0, a1
3181 ; RV32ZICOND-NEXT: xori a0, a0, 1
3182 ; RV32ZICOND-NEXT: ret
3183 ;
3184 ; RV64ZICOND-LABEL: usubo.not.i64:
3185 ; RV64ZICOND: # %bb.0: # %entry
3186 ; RV64ZICOND-NEXT: sub a1, a0, a1
3187 ; RV64ZICOND-NEXT: sltu a0, a0, a1
3188 ; RV64ZICOND-NEXT: xori a0, a0, 1
3189 ; RV64ZICOND-NEXT: ret
3190 entry:
3191 %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
3192 %obit = extractvalue {i64, i1} %t, 1
3193 %ret = xor i1 %obit, true
3194 ret i1 %ret
3195 }
3197 define i32 @smulo.select.i32(i32 signext %v1, i32 signext %v2) {
3198 ; RV32-LABEL: smulo.select.i32:
3199 ; RV32: # %bb.0: # %entry
3200 ; RV32-NEXT: mulh a2, a0, a1
3201 ; RV32-NEXT: mul a3, a0, a1
3202 ; RV32-NEXT: srai a3, a3, 31
3203 ; RV32-NEXT: bne a2, a3, .LBB44_2
3204 ; RV32-NEXT: # %bb.1: # %entry
3205 ; RV32-NEXT: mv a0, a1
3206 ; RV32-NEXT: .LBB44_2: # %entry
3207 ; RV32-NEXT: ret
3208 ;
3209 ; RV64-LABEL: smulo.select.i32:
3210 ; RV64: # %bb.0: # %entry
3211 ; RV64-NEXT: mul a2, a0, a1
3212 ; RV64-NEXT: mulw a3, a0, a1
3213 ; RV64-NEXT: bne a3, a2, .LBB44_2
3214 ; RV64-NEXT: # %bb.1: # %entry
3215 ; RV64-NEXT: mv a0, a1
3216 ; RV64-NEXT: .LBB44_2: # %entry
3217 ; RV64-NEXT: ret
3218 ;
3219 ; RV32ZBA-LABEL: smulo.select.i32:
3220 ; RV32ZBA: # %bb.0: # %entry
3221 ; RV32ZBA-NEXT: mulh a2, a0, a1
3222 ; RV32ZBA-NEXT: mul a3, a0, a1
3223 ; RV32ZBA-NEXT: srai a3, a3, 31
3224 ; RV32ZBA-NEXT: bne a2, a3, .LBB44_2
3225 ; RV32ZBA-NEXT: # %bb.1: # %entry
3226 ; RV32ZBA-NEXT: mv a0, a1
3227 ; RV32ZBA-NEXT: .LBB44_2: # %entry
3228 ; RV32ZBA-NEXT: ret
3229 ;
3230 ; RV64ZBA-LABEL: smulo.select.i32:
3231 ; RV64ZBA: # %bb.0: # %entry
3232 ; RV64ZBA-NEXT: mul a2, a0, a1
3233 ; RV64ZBA-NEXT: mulw a3, a0, a1
3234 ; RV64ZBA-NEXT: bne a3, a2, .LBB44_2
3235 ; RV64ZBA-NEXT: # %bb.1: # %entry
3236 ; RV64ZBA-NEXT: mv a0, a1
3237 ; RV64ZBA-NEXT: .LBB44_2: # %entry
3238 ; RV64ZBA-NEXT: ret
3239 ;
3240 ; RV32ZICOND-LABEL: smulo.select.i32:
3241 ; RV32ZICOND: # %bb.0: # %entry
3242 ; RV32ZICOND-NEXT: mulh a2, a0, a1
3243 ; RV32ZICOND-NEXT: mul a3, a0, a1
3244 ; RV32ZICOND-NEXT: srai a3, a3, 31
3245 ; RV32ZICOND-NEXT: xor a2, a2, a3
3246 ; RV32ZICOND-NEXT: czero.nez a1, a1, a2
3247 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a2
3248 ; RV32ZICOND-NEXT: or a0, a0, a1
3249 ; RV32ZICOND-NEXT: ret
3250 ;
3251 ; RV64ZICOND-LABEL: smulo.select.i32:
3252 ; RV64ZICOND: # %bb.0: # %entry
3253 ; RV64ZICOND-NEXT: mul a2, a0, a1
3254 ; RV64ZICOND-NEXT: mulw a3, a0, a1
3255 ; RV64ZICOND-NEXT: xor a2, a3, a2
3256 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2
3257 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
3258 ; RV64ZICOND-NEXT: or a0, a0, a1
3259 ; RV64ZICOND-NEXT: ret
3260 entry:
3261 %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
3262 %obit = extractvalue {i32, i1} %t, 1
3263 %ret = select i1 %obit, i32 %v1, i32 %v2
3264 ret i32 %ret
3265 }
3267 define i1 @smulo.not.i32(i32 signext %v1, i32 signext %v2) {
3268 ; RV32-LABEL: smulo.not.i32:
3269 ; RV32: # %bb.0: # %entry
3270 ; RV32-NEXT: mulh a2, a0, a1
3271 ; RV32-NEXT: mul a0, a0, a1
3272 ; RV32-NEXT: srai a0, a0, 31
3273 ; RV32-NEXT: xor a0, a2, a0
3274 ; RV32-NEXT: seqz a0, a0
3275 ; RV32-NEXT: ret
3276 ;
3277 ; RV64-LABEL: smulo.not.i32:
3278 ; RV64: # %bb.0: # %entry
3279 ; RV64-NEXT: mul a2, a0, a1
3280 ; RV64-NEXT: mulw a0, a0, a1
3281 ; RV64-NEXT: xor a0, a0, a2
3282 ; RV64-NEXT: seqz a0, a0
3283 ; RV64-NEXT: ret
3284 ;
3285 ; RV32ZBA-LABEL: smulo.not.i32:
3286 ; RV32ZBA: # %bb.0: # %entry
3287 ; RV32ZBA-NEXT: mulh a2, a0, a1
3288 ; RV32ZBA-NEXT: mul a0, a0, a1
3289 ; RV32ZBA-NEXT: srai a0, a0, 31
3290 ; RV32ZBA-NEXT: xor a0, a2, a0
3291 ; RV32ZBA-NEXT: seqz a0, a0
3292 ; RV32ZBA-NEXT: ret
3293 ;
3294 ; RV64ZBA-LABEL: smulo.not.i32:
3295 ; RV64ZBA: # %bb.0: # %entry
3296 ; RV64ZBA-NEXT: mul a2, a0, a1
3297 ; RV64ZBA-NEXT: mulw a0, a0, a1
3298 ; RV64ZBA-NEXT: xor a0, a0, a2
3299 ; RV64ZBA-NEXT: seqz a0, a0
3300 ; RV64ZBA-NEXT: ret
3301 ;
3302 ; RV32ZICOND-LABEL: smulo.not.i32:
3303 ; RV32ZICOND: # %bb.0: # %entry
3304 ; RV32ZICOND-NEXT: mulh a2, a0, a1
3305 ; RV32ZICOND-NEXT: mul a0, a0, a1
3306 ; RV32ZICOND-NEXT: srai a0, a0, 31
3307 ; RV32ZICOND-NEXT: xor a0, a2, a0
3308 ; RV32ZICOND-NEXT: seqz a0, a0
3309 ; RV32ZICOND-NEXT: ret
3310 ;
3311 ; RV64ZICOND-LABEL: smulo.not.i32:
3312 ; RV64ZICOND: # %bb.0: # %entry
3313 ; RV64ZICOND-NEXT: mul a2, a0, a1
3314 ; RV64ZICOND-NEXT: mulw a0, a0, a1
3315 ; RV64ZICOND-NEXT: xor a0, a0, a2
3316 ; RV64ZICOND-NEXT: seqz a0, a0
3317 ; RV64ZICOND-NEXT: ret
3318 entry:
3319 %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
3320 %obit = extractvalue {i32, i1} %t, 1
3321 %ret = xor i1 %obit, true
3322 ret i1 %ret
3323 }
3325 define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
3326 ; RV32-LABEL: smulo.select.i64:
3327 ; RV32: # %bb.0: # %entry
3328 ; RV32-NEXT: addi sp, sp, -16
3329 ; RV32-NEXT: .cfi_def_cfa_offset 16
3330 ; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
3331 ; RV32-NEXT: .cfi_offset s0, -4
3332 ; RV32-NEXT: mulhu a4, a0, a2
3333 ; RV32-NEXT: mul a5, a1, a2
3334 ; RV32-NEXT: add a4, a5, a4
3335 ; RV32-NEXT: sltu a5, a4, a5
3336 ; RV32-NEXT: mulhu a6, a1, a2
3337 ; RV32-NEXT: add a5, a6, a5
3338 ; RV32-NEXT: mul a6, a0, a3
3339 ; RV32-NEXT: add a4, a6, a4
3340 ; RV32-NEXT: sltu a6, a4, a6
3341 ; RV32-NEXT: mulhu a7, a0, a3
3342 ; RV32-NEXT: add a6, a7, a6
3343 ; RV32-NEXT: add a6, a5, a6
3344 ; RV32-NEXT: mul a7, a1, a3
3345 ; RV32-NEXT: add t0, a7, a6
3346 ; RV32-NEXT: srai t1, a1, 31
3347 ; RV32-NEXT: mul t2, a2, t1
3348 ; RV32-NEXT: srai t3, a3, 31
3349 ; RV32-NEXT: mul t4, t3, a0
3350 ; RV32-NEXT: add t5, t4, t2
3351 ; RV32-NEXT: add t6, t0, t5
3352 ; RV32-NEXT: sltu s0, t6, t0
3353 ; RV32-NEXT: sltu a7, t0, a7
3354 ; RV32-NEXT: sltu a5, a6, a5
3355 ; RV32-NEXT: mulhu a6, a1, a3
3356 ; RV32-NEXT: add a5, a6, a5
3357 ; RV32-NEXT: add a5, a5, a7
3358 ; RV32-NEXT: mulhu a6, a2, t1
3359 ; RV32-NEXT: add a6, a6, t2
3360 ; RV32-NEXT: mul a7, a3, t1
3361 ; RV32-NEXT: add a6, a6, a7
3362 ; RV32-NEXT: mul a7, t3, a1
3363 ; RV32-NEXT: mulhu t0, t3, a0
3364 ; RV32-NEXT: add a7, t0, a7
3365 ; RV32-NEXT: add a7, a7, t4
3366 ; RV32-NEXT: add a6, a7, a6
3367 ; RV32-NEXT: sltu a7, t5, t4
3368 ; RV32-NEXT: add a6, a6, a7
3369 ; RV32-NEXT: add a5, a5, a6
3370 ; RV32-NEXT: add a5, a5, s0
3371 ; RV32-NEXT: srai a4, a4, 31
3372 ; RV32-NEXT: xor a5, a5, a4
3373 ; RV32-NEXT: xor a4, t6, a4
3374 ; RV32-NEXT: or a4, a4, a5
3375 ; RV32-NEXT: bnez a4, .LBB46_2
3376 ; RV32-NEXT: # %bb.1: # %entry
3377 ; RV32-NEXT: mv a0, a2
3378 ; RV32-NEXT: mv a1, a3
3379 ; RV32-NEXT: .LBB46_2: # %entry
3380 ; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
3381 ; RV32-NEXT: addi sp, sp, 16
3382 ; RV32-NEXT: ret
3383 ;
3384 ; RV64-LABEL: smulo.select.i64:
3385 ; RV64: # %bb.0: # %entry
3386 ; RV64-NEXT: mulh a2, a0, a1
3387 ; RV64-NEXT: mul a3, a0, a1
3388 ; RV64-NEXT: srai a3, a3, 63
3389 ; RV64-NEXT: bne a2, a3, .LBB46_2
3390 ; RV64-NEXT: # %bb.1: # %entry
3391 ; RV64-NEXT: mv a0, a1
3392 ; RV64-NEXT: .LBB46_2: # %entry
3393 ; RV64-NEXT: ret
3394 ;
3395 ; RV32ZBA-LABEL: smulo.select.i64:
3396 ; RV32ZBA: # %bb.0: # %entry
3397 ; RV32ZBA-NEXT: addi sp, sp, -16
3398 ; RV32ZBA-NEXT: .cfi_def_cfa_offset 16
3399 ; RV32ZBA-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
3400 ; RV32ZBA-NEXT: .cfi_offset s0, -4
3401 ; RV32ZBA-NEXT: mulhu a4, a0, a2
3402 ; RV32ZBA-NEXT: mul a5, a1, a2
3403 ; RV32ZBA-NEXT: add a4, a5, a4
3404 ; RV32ZBA-NEXT: sltu a5, a4, a5
3405 ; RV32ZBA-NEXT: mulhu a6, a1, a2
3406 ; RV32ZBA-NEXT: add a5, a6, a5
3407 ; RV32ZBA-NEXT: mul a6, a0, a3
3408 ; RV32ZBA-NEXT: add a4, a6, a4
3409 ; RV32ZBA-NEXT: sltu a6, a4, a6
3410 ; RV32ZBA-NEXT: mulhu a7, a0, a3
3411 ; RV32ZBA-NEXT: add a6, a7, a6
3412 ; RV32ZBA-NEXT: add a6, a5, a6
3413 ; RV32ZBA-NEXT: mul a7, a1, a3
3414 ; RV32ZBA-NEXT: add t0, a7, a6
3415 ; RV32ZBA-NEXT: srai t1, a1, 31
3416 ; RV32ZBA-NEXT: mul t2, a2, t1
3417 ; RV32ZBA-NEXT: srai t3, a3, 31
3418 ; RV32ZBA-NEXT: mul t4, t3, a0
3419 ; RV32ZBA-NEXT: add t5, t4, t2
3420 ; RV32ZBA-NEXT: add t6, t0, t5
3421 ; RV32ZBA-NEXT: sltu s0, t6, t0
3422 ; RV32ZBA-NEXT: sltu a7, t0, a7
3423 ; RV32ZBA-NEXT: sltu a5, a6, a5
3424 ; RV32ZBA-NEXT: mulhu a6, a1, a3
3425 ; RV32ZBA-NEXT: add a5, a6, a5
3426 ; RV32ZBA-NEXT: add a5, a5, a7
3427 ; RV32ZBA-NEXT: mulhu a6, a2, t1
3428 ; RV32ZBA-NEXT: add a6, a6, t2
3429 ; RV32ZBA-NEXT: mul a7, a3, t1
3430 ; RV32ZBA-NEXT: add a6, a6, a7
3431 ; RV32ZBA-NEXT: mul a7, t3, a1
3432 ; RV32ZBA-NEXT: mulhu t0, t3, a0
3433 ; RV32ZBA-NEXT: add a7, t0, a7
3434 ; RV32ZBA-NEXT: add a7, a7, t4
3435 ; RV32ZBA-NEXT: add a6, a7, a6
3436 ; RV32ZBA-NEXT: sltu a7, t5, t4
3437 ; RV32ZBA-NEXT: add a6, a6, a7
3438 ; RV32ZBA-NEXT: add a5, a5, a6
3439 ; RV32ZBA-NEXT: add a5, a5, s0
3440 ; RV32ZBA-NEXT: srai a4, a4, 31
3441 ; RV32ZBA-NEXT: xor a5, a5, a4
3442 ; RV32ZBA-NEXT: xor a4, t6, a4
3443 ; RV32ZBA-NEXT: or a4, a4, a5
3444 ; RV32ZBA-NEXT: bnez a4, .LBB46_2
3445 ; RV32ZBA-NEXT: # %bb.1: # %entry
3446 ; RV32ZBA-NEXT: mv a0, a2
3447 ; RV32ZBA-NEXT: mv a1, a3
3448 ; RV32ZBA-NEXT: .LBB46_2: # %entry
3449 ; RV32ZBA-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
3450 ; RV32ZBA-NEXT: addi sp, sp, 16
3451 ; RV32ZBA-NEXT: ret
3452 ;
3453 ; RV64ZBA-LABEL: smulo.select.i64:
3454 ; RV64ZBA: # %bb.0: # %entry
3455 ; RV64ZBA-NEXT: mulh a2, a0, a1
3456 ; RV64ZBA-NEXT: mul a3, a0, a1
3457 ; RV64ZBA-NEXT: srai a3, a3, 63
3458 ; RV64ZBA-NEXT: bne a2, a3, .LBB46_2
3459 ; RV64ZBA-NEXT: # %bb.1: # %entry
3460 ; RV64ZBA-NEXT: mv a0, a1
3461 ; RV64ZBA-NEXT: .LBB46_2: # %entry
3462 ; RV64ZBA-NEXT: ret
3463 ;
3464 ; RV32ZICOND-LABEL: smulo.select.i64:
3465 ; RV32ZICOND: # %bb.0: # %entry
3466 ; RV32ZICOND-NEXT: addi sp, sp, -16
3467 ; RV32ZICOND-NEXT: .cfi_def_cfa_offset 16
3468 ; RV32ZICOND-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
3469 ; RV32ZICOND-NEXT: .cfi_offset s0, -4
3470 ; RV32ZICOND-NEXT: mulhu a4, a0, a2
3471 ; RV32ZICOND-NEXT: mul a5, a1, a2
3472 ; RV32ZICOND-NEXT: add a4, a5, a4
3473 ; RV32ZICOND-NEXT: sltu a5, a4, a5
3474 ; RV32ZICOND-NEXT: mulhu a6, a1, a2
3475 ; RV32ZICOND-NEXT: add a5, a6, a5
3476 ; RV32ZICOND-NEXT: mul a6, a0, a3
3477 ; RV32ZICOND-NEXT: add a4, a6, a4
3478 ; RV32ZICOND-NEXT: sltu a6, a4, a6
3479 ; RV32ZICOND-NEXT: mulhu a7, a0, a3
3480 ; RV32ZICOND-NEXT: add a6, a7, a6
3481 ; RV32ZICOND-NEXT: add a6, a5, a6
3482 ; RV32ZICOND-NEXT: mul a7, a1, a3
3483 ; RV32ZICOND-NEXT: add t0, a7, a6
3484 ; RV32ZICOND-NEXT: srai t1, a1, 31
3485 ; RV32ZICOND-NEXT: mul t2, a2, t1
3486 ; RV32ZICOND-NEXT: srai t3, a3, 31
3487 ; RV32ZICOND-NEXT: mul t4, t3, a0
3488 ; RV32ZICOND-NEXT: add t5, t4, t2
3489 ; RV32ZICOND-NEXT: add t6, t0, t5
3490 ; RV32ZICOND-NEXT: sltu s0, t6, t0
3491 ; RV32ZICOND-NEXT: sltu a7, t0, a7
3492 ; RV32ZICOND-NEXT: sltu a5, a6, a5
3493 ; RV32ZICOND-NEXT: mulhu a6, a1, a3
3494 ; RV32ZICOND-NEXT: add a5, a6, a5
3495 ; RV32ZICOND-NEXT: add a5, a5, a7
3496 ; RV32ZICOND-NEXT: mulhu a6, a2, t1
3497 ; RV32ZICOND-NEXT: add a6, a6, t2
3498 ; RV32ZICOND-NEXT: mul a7, a3, t1
3499 ; RV32ZICOND-NEXT: add a6, a6, a7
3500 ; RV32ZICOND-NEXT: mul a7, t3, a1
3501 ; RV32ZICOND-NEXT: mulhu t0, t3, a0
3502 ; RV32ZICOND-NEXT: add a7, t0, a7
3503 ; RV32ZICOND-NEXT: add a7, a7, t4
3504 ; RV32ZICOND-NEXT: add a6, a7, a6
3505 ; RV32ZICOND-NEXT: sltu a7, t5, t4
3506 ; RV32ZICOND-NEXT: add a6, a6, a7
3507 ; RV32ZICOND-NEXT: add a5, a5, a6
3508 ; RV32ZICOND-NEXT: add a5, a5, s0
3509 ; RV32ZICOND-NEXT: srai a4, a4, 31
3510 ; RV32ZICOND-NEXT: xor a5, a5, a4
3511 ; RV32ZICOND-NEXT: xor a4, t6, a4
3512 ; RV32ZICOND-NEXT: or a4, a4, a5
3513 ; RV32ZICOND-NEXT: czero.nez a2, a2, a4
3514 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a4
3515 ; RV32ZICOND-NEXT: or a0, a0, a2
3516 ; RV32ZICOND-NEXT: czero.nez a2, a3, a4
3517 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a4
3518 ; RV32ZICOND-NEXT: or a1, a1, a2
3519 ; RV32ZICOND-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
3520 ; RV32ZICOND-NEXT: addi sp, sp, 16
3521 ; RV32ZICOND-NEXT: ret
3522 ;
3523 ; RV64ZICOND-LABEL: smulo.select.i64:
3524 ; RV64ZICOND: # %bb.0: # %entry
3525 ; RV64ZICOND-NEXT: mulh a2, a0, a1
3526 ; RV64ZICOND-NEXT: mul a3, a0, a1
3527 ; RV64ZICOND-NEXT: srai a3, a3, 63
3528 ; RV64ZICOND-NEXT: xor a2, a2, a3
3529 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2
3530 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
3531 ; RV64ZICOND-NEXT: or a0, a0, a1
3532 ; RV64ZICOND-NEXT: ret
3533 entry:
3534 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
3535 %obit = extractvalue {i64, i1} %t, 1
3536 %ret = select i1 %obit, i64 %v1, i64 %v2
3537 ret i64 %ret
3538 }
3540 define i1 @smulo.not.i64(i64 %v1, i64 %v2) {
3541 ; RV32-LABEL: smulo.not.i64:
3542 ; RV32: # %bb.0: # %entry
3543 ; RV32-NEXT: addi sp, sp, -16
3544 ; RV32-NEXT: .cfi_def_cfa_offset 16
3545 ; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
3546 ; RV32-NEXT: .cfi_offset s0, -4
3547 ; RV32-NEXT: mulhu a4, a0, a2
3548 ; RV32-NEXT: mul a5, a1, a2
3549 ; RV32-NEXT: add a4, a5, a4
3550 ; RV32-NEXT: sltu a5, a4, a5
3551 ; RV32-NEXT: mulhu a6, a1, a2
3552 ; RV32-NEXT: add a5, a6, a5
3553 ; RV32-NEXT: mul a6, a0, a3
3554 ; RV32-NEXT: add a4, a6, a4
3555 ; RV32-NEXT: sltu a6, a4, a6
3556 ; RV32-NEXT: mulhu a7, a0, a3
3557 ; RV32-NEXT: add a6, a7, a6
3558 ; RV32-NEXT: add a6, a5, a6
3559 ; RV32-NEXT: mul a7, a1, a3
3560 ; RV32-NEXT: add t0, a7, a6
3561 ; RV32-NEXT: srai t1, a1, 31
3562 ; RV32-NEXT: mul t2, a2, t1
3563 ; RV32-NEXT: srai t3, a3, 31
3564 ; RV32-NEXT: mul t4, t3, a0
3565 ; RV32-NEXT: add t5, t4, t2
3566 ; RV32-NEXT: add t6, t0, t5
3567 ; RV32-NEXT: sltu s0, t6, t0
3568 ; RV32-NEXT: sltu a7, t0, a7
3569 ; RV32-NEXT: sltu a5, a6, a5
3570 ; RV32-NEXT: mulhu a6, a1, a3
3571 ; RV32-NEXT: add a5, a6, a5
3572 ; RV32-NEXT: add a5, a5, a7
3573 ; RV32-NEXT: mulhu a2, a2, t1
3574 ; RV32-NEXT: add a2, a2, t2
3575 ; RV32-NEXT: mul a3, a3, t1
3576 ; RV32-NEXT: add a2, a2, a3
3577 ; RV32-NEXT: mul a1, t3, a1
3578 ; RV32-NEXT: mulhu a0, t3, a0
3579 ; RV32-NEXT: add a0, a0, a1
3580 ; RV32-NEXT: add a0, a0, t4
3581 ; RV32-NEXT: add a0, a0, a2
3582 ; RV32-NEXT: sltu a1, t5, t4
3583 ; RV32-NEXT: add a0, a0, a1
3584 ; RV32-NEXT: add a0, a5, a0
3585 ; RV32-NEXT: add a0, a0, s0
3586 ; RV32-NEXT: srai a4, a4, 31
3587 ; RV32-NEXT: xor a0, a0, a4
3588 ; RV32-NEXT: xor a1, t6, a4
3589 ; RV32-NEXT: or a0, a1, a0
3590 ; RV32-NEXT: seqz a0, a0
3591 ; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
3592 ; RV32-NEXT: addi sp, sp, 16
3593 ; RV32-NEXT: ret
3594 ;
3595 ; RV64-LABEL: smulo.not.i64:
3596 ; RV64: # %bb.0: # %entry
3597 ; RV64-NEXT: mulh a2, a0, a1
3598 ; RV64-NEXT: mul a0, a0, a1
3599 ; RV64-NEXT: srai a0, a0, 63
3600 ; RV64-NEXT: xor a0, a2, a0
3601 ; RV64-NEXT: seqz a0, a0
3602 ; RV64-NEXT: ret
3603 ;
3604 ; RV32ZBA-LABEL: smulo.not.i64:
3605 ; RV32ZBA: # %bb.0: # %entry
3606 ; RV32ZBA-NEXT: addi sp, sp, -16
3607 ; RV32ZBA-NEXT: .cfi_def_cfa_offset 16
3608 ; RV32ZBA-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
3609 ; RV32ZBA-NEXT: .cfi_offset s0, -4
3610 ; RV32ZBA-NEXT: mulhu a4, a0, a2
3611 ; RV32ZBA-NEXT: mul a5, a1, a2
3612 ; RV32ZBA-NEXT: add a4, a5, a4
3613 ; RV32ZBA-NEXT: sltu a5, a4, a5
3614 ; RV32ZBA-NEXT: mulhu a6, a1, a2
3615 ; RV32ZBA-NEXT: add a5, a6, a5
3616 ; RV32ZBA-NEXT: mul a6, a0, a3
3617 ; RV32ZBA-NEXT: add a4, a6, a4
3618 ; RV32ZBA-NEXT: sltu a6, a4, a6
3619 ; RV32ZBA-NEXT: mulhu a7, a0, a3
3620 ; RV32ZBA-NEXT: add a6, a7, a6
3621 ; RV32ZBA-NEXT: add a6, a5, a6
3622 ; RV32ZBA-NEXT: mul a7, a1, a3
3623 ; RV32ZBA-NEXT: add t0, a7, a6
3624 ; RV32ZBA-NEXT: srai t1, a1, 31
3625 ; RV32ZBA-NEXT: mul t2, a2, t1
3626 ; RV32ZBA-NEXT: srai t3, a3, 31
3627 ; RV32ZBA-NEXT: mul t4, t3, a0
3628 ; RV32ZBA-NEXT: add t5, t4, t2
3629 ; RV32ZBA-NEXT: add t6, t0, t5
3630 ; RV32ZBA-NEXT: sltu s0, t6, t0
3631 ; RV32ZBA-NEXT: sltu a7, t0, a7
3632 ; RV32ZBA-NEXT: sltu a5, a6, a5
3633 ; RV32ZBA-NEXT: mulhu a6, a1, a3
3634 ; RV32ZBA-NEXT: add a5, a6, a5
3635 ; RV32ZBA-NEXT: add a5, a5, a7
3636 ; RV32ZBA-NEXT: mulhu a2, a2, t1
3637 ; RV32ZBA-NEXT: add a2, a2, t2
3638 ; RV32ZBA-NEXT: mul a3, a3, t1
3639 ; RV32ZBA-NEXT: add a2, a2, a3
3640 ; RV32ZBA-NEXT: mul a1, t3, a1
3641 ; RV32ZBA-NEXT: mulhu a0, t3, a0
3642 ; RV32ZBA-NEXT: add a0, a0, a1
3643 ; RV32ZBA-NEXT: add a0, a0, t4
3644 ; RV32ZBA-NEXT: add a0, a0, a2
3645 ; RV32ZBA-NEXT: sltu a1, t5, t4
3646 ; RV32ZBA-NEXT: add a0, a0, a1
3647 ; RV32ZBA-NEXT: add a0, a5, a0
3648 ; RV32ZBA-NEXT: add a0, a0, s0
3649 ; RV32ZBA-NEXT: srai a4, a4, 31
3650 ; RV32ZBA-NEXT: xor a0, a0, a4
3651 ; RV32ZBA-NEXT: xor a1, t6, a4
3652 ; RV32ZBA-NEXT: or a0, a1, a0
3653 ; RV32ZBA-NEXT: seqz a0, a0
3654 ; RV32ZBA-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
3655 ; RV32ZBA-NEXT: addi sp, sp, 16
3656 ; RV32ZBA-NEXT: ret
3657 ;
3658 ; RV64ZBA-LABEL: smulo.not.i64:
3659 ; RV64ZBA: # %bb.0: # %entry
3660 ; RV64ZBA-NEXT: mulh a2, a0, a1
3661 ; RV64ZBA-NEXT: mul a0, a0, a1
3662 ; RV64ZBA-NEXT: srai a0, a0, 63
3663 ; RV64ZBA-NEXT: xor a0, a2, a0
3664 ; RV64ZBA-NEXT: seqz a0, a0
3665 ; RV64ZBA-NEXT: ret
3666 ;
3667 ; RV32ZICOND-LABEL: smulo.not.i64:
3668 ; RV32ZICOND: # %bb.0: # %entry
3669 ; RV32ZICOND-NEXT: addi sp, sp, -16
3670 ; RV32ZICOND-NEXT: .cfi_def_cfa_offset 16
3671 ; RV32ZICOND-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
3672 ; RV32ZICOND-NEXT: .cfi_offset s0, -4
3673 ; RV32ZICOND-NEXT: mulhu a4, a0, a2
3674 ; RV32ZICOND-NEXT: mul a5, a1, a2
3675 ; RV32ZICOND-NEXT: add a4, a5, a4
3676 ; RV32ZICOND-NEXT: sltu a5, a4, a5
3677 ; RV32ZICOND-NEXT: mulhu a6, a1, a2
3678 ; RV32ZICOND-NEXT: add a5, a6, a5
3679 ; RV32ZICOND-NEXT: mul a6, a0, a3
3680 ; RV32ZICOND-NEXT: add a4, a6, a4
3681 ; RV32ZICOND-NEXT: sltu a6, a4, a6
3682 ; RV32ZICOND-NEXT: mulhu a7, a0, a3
3683 ; RV32ZICOND-NEXT: add a6, a7, a6
3684 ; RV32ZICOND-NEXT: add a6, a5, a6
3685 ; RV32ZICOND-NEXT: mul a7, a1, a3
3686 ; RV32ZICOND-NEXT: add t0, a7, a6
3687 ; RV32ZICOND-NEXT: srai t1, a1, 31
3688 ; RV32ZICOND-NEXT: mul t2, a2, t1
3689 ; RV32ZICOND-NEXT: srai t3, a3, 31
3690 ; RV32ZICOND-NEXT: mul t4, t3, a0
3691 ; RV32ZICOND-NEXT: add t5, t4, t2
3692 ; RV32ZICOND-NEXT: add t6, t0, t5
3693 ; RV32ZICOND-NEXT: sltu s0, t6, t0
3694 ; RV32ZICOND-NEXT: sltu a7, t0, a7
3695 ; RV32ZICOND-NEXT: sltu a5, a6, a5
3696 ; RV32ZICOND-NEXT: mulhu a6, a1, a3
3697 ; RV32ZICOND-NEXT: add a5, a6, a5
3698 ; RV32ZICOND-NEXT: add a5, a5, a7
3699 ; RV32ZICOND-NEXT: mulhu a2, a2, t1
3700 ; RV32ZICOND-NEXT: add a2, a2, t2
3701 ; RV32ZICOND-NEXT: mul a3, a3, t1
3702 ; RV32ZICOND-NEXT: add a2, a2, a3
3703 ; RV32ZICOND-NEXT: mul a1, t3, a1
3704 ; RV32ZICOND-NEXT: mulhu a0, t3, a0
3705 ; RV32ZICOND-NEXT: add a0, a0, a1
3706 ; RV32ZICOND-NEXT: add a0, a0, t4
3707 ; RV32ZICOND-NEXT: add a0, a0, a2
3708 ; RV32ZICOND-NEXT: sltu a1, t5, t4
3709 ; RV32ZICOND-NEXT: add a0, a0, a1
3710 ; RV32ZICOND-NEXT: add a0, a5, a0
3711 ; RV32ZICOND-NEXT: add a0, a0, s0
3712 ; RV32ZICOND-NEXT: srai a4, a4, 31
3713 ; RV32ZICOND-NEXT: xor a0, a0, a4
3714 ; RV32ZICOND-NEXT: xor a1, t6, a4
3715 ; RV32ZICOND-NEXT: or a0, a1, a0
3716 ; RV32ZICOND-NEXT: seqz a0, a0
3717 ; RV32ZICOND-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
3718 ; RV32ZICOND-NEXT: addi sp, sp, 16
3719 ; RV32ZICOND-NEXT: ret
3720 ;
3721 ; RV64ZICOND-LABEL: smulo.not.i64:
3722 ; RV64ZICOND: # %bb.0: # %entry
3723 ; RV64ZICOND-NEXT: mulh a2, a0, a1
3724 ; RV64ZICOND-NEXT: mul a0, a0, a1
3725 ; RV64ZICOND-NEXT: srai a0, a0, 63
3726 ; RV64ZICOND-NEXT: xor a0, a2, a0
3727 ; RV64ZICOND-NEXT: seqz a0, a0
3728 ; RV64ZICOND-NEXT: ret
3729 entry:
3730 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
3731 %obit = extractvalue {i64, i1} %t, 1
3732 %ret = xor i1 %obit, true
3733 ret i1 %ret
3734 }
3736 define i32 @umulo.select.i32(i32 signext %v1, i32 signext %v2) {
3737 ; RV32-LABEL: umulo.select.i32:
3738 ; RV32: # %bb.0: # %entry
3739 ; RV32-NEXT: mulhu a2, a0, a1
3740 ; RV32-NEXT: bnez a2, .LBB48_2
3741 ; RV32-NEXT: # %bb.1: # %entry
3742 ; RV32-NEXT: mv a0, a1
3743 ; RV32-NEXT: .LBB48_2: # %entry
3744 ; RV32-NEXT: ret
3745 ;
3746 ; RV64-LABEL: umulo.select.i32:
3747 ; RV64: # %bb.0: # %entry
3748 ; RV64-NEXT: slli a2, a1, 32
3749 ; RV64-NEXT: slli a3, a0, 32
3750 ; RV64-NEXT: mulhu a2, a3, a2
3751 ; RV64-NEXT: srli a2, a2, 32
3752 ; RV64-NEXT: bnez a2, .LBB48_2
3753 ; RV64-NEXT: # %bb.1: # %entry
3754 ; RV64-NEXT: mv a0, a1
3755 ; RV64-NEXT: .LBB48_2: # %entry
3756 ; RV64-NEXT: ret
3757 ;
3758 ; RV32ZBA-LABEL: umulo.select.i32:
3759 ; RV32ZBA: # %bb.0: # %entry
3760 ; RV32ZBA-NEXT: mulhu a2, a0, a1
3761 ; RV32ZBA-NEXT: bnez a2, .LBB48_2
3762 ; RV32ZBA-NEXT: # %bb.1: # %entry
3763 ; RV32ZBA-NEXT: mv a0, a1
3764 ; RV32ZBA-NEXT: .LBB48_2: # %entry
3765 ; RV32ZBA-NEXT: ret
3766 ;
3767 ; RV64ZBA-LABEL: umulo.select.i32:
3768 ; RV64ZBA: # %bb.0: # %entry
3769 ; RV64ZBA-NEXT: zext.w a2, a1
3770 ; RV64ZBA-NEXT: zext.w a3, a0
3771 ; RV64ZBA-NEXT: mul a2, a3, a2
3772 ; RV64ZBA-NEXT: srli a2, a2, 32
3773 ; RV64ZBA-NEXT: bnez a2, .LBB48_2
3774 ; RV64ZBA-NEXT: # %bb.1: # %entry
3775 ; RV64ZBA-NEXT: mv a0, a1
3776 ; RV64ZBA-NEXT: .LBB48_2: # %entry
3777 ; RV64ZBA-NEXT: ret
3778 ;
3779 ; RV32ZICOND-LABEL: umulo.select.i32:
3780 ; RV32ZICOND: # %bb.0: # %entry
3781 ; RV32ZICOND-NEXT: mulhu a2, a0, a1
3782 ; RV32ZICOND-NEXT: czero.nez a1, a1, a2
3783 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a2
3784 ; RV32ZICOND-NEXT: or a0, a0, a1
3785 ; RV32ZICOND-NEXT: ret
3786 ;
3787 ; RV64ZICOND-LABEL: umulo.select.i32:
3788 ; RV64ZICOND: # %bb.0: # %entry
3789 ; RV64ZICOND-NEXT: slli a2, a1, 32
3790 ; RV64ZICOND-NEXT: slli a3, a0, 32
3791 ; RV64ZICOND-NEXT: mulhu a2, a3, a2
3792 ; RV64ZICOND-NEXT: srli a2, a2, 32
3793 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2
3794 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
3795 ; RV64ZICOND-NEXT: or a0, a0, a1
3796 ; RV64ZICOND-NEXT: ret
3797 entry:
3798 %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
3799 %obit = extractvalue {i32, i1} %t, 1
3800 %ret = select i1 %obit, i32 %v1, i32 %v2
3801 ret i32 %ret
3802 }
3804 define i1 @umulo.not.i32(i32 signext %v1, i32 signext %v2) {
3805 ; RV32-LABEL: umulo.not.i32:
3806 ; RV32: # %bb.0: # %entry
3807 ; RV32-NEXT: mulhu a0, a0, a1
3808 ; RV32-NEXT: seqz a0, a0
3809 ; RV32-NEXT: ret
3810 ;
3811 ; RV64-LABEL: umulo.not.i32:
3812 ; RV64: # %bb.0: # %entry
3813 ; RV64-NEXT: slli a1, a1, 32
3814 ; RV64-NEXT: slli a0, a0, 32
3815 ; RV64-NEXT: mulhu a0, a0, a1
3816 ; RV64-NEXT: srli a0, a0, 32
3817 ; RV64-NEXT: seqz a0, a0
3818 ; RV64-NEXT: ret
3819 ;
3820 ; RV32ZBA-LABEL: umulo.not.i32:
3821 ; RV32ZBA: # %bb.0: # %entry
3822 ; RV32ZBA-NEXT: mulhu a0, a0, a1
3823 ; RV32ZBA-NEXT: seqz a0, a0
3824 ; RV32ZBA-NEXT: ret
3825 ;
3826 ; RV64ZBA-LABEL: umulo.not.i32:
3827 ; RV64ZBA: # %bb.0: # %entry
3828 ; RV64ZBA-NEXT: zext.w a1, a1
3829 ; RV64ZBA-NEXT: zext.w a0, a0
3830 ; RV64ZBA-NEXT: mul a0, a0, a1
3831 ; RV64ZBA-NEXT: srli a0, a0, 32
3832 ; RV64ZBA-NEXT: seqz a0, a0
3833 ; RV64ZBA-NEXT: ret
3834 ;
3835 ; RV32ZICOND-LABEL: umulo.not.i32:
3836 ; RV32ZICOND: # %bb.0: # %entry
3837 ; RV32ZICOND-NEXT: mulhu a0, a0, a1
3838 ; RV32ZICOND-NEXT: seqz a0, a0
3839 ; RV32ZICOND-NEXT: ret
3840 ;
3841 ; RV64ZICOND-LABEL: umulo.not.i32:
3842 ; RV64ZICOND: # %bb.0: # %entry
3843 ; RV64ZICOND-NEXT: slli a1, a1, 32
3844 ; RV64ZICOND-NEXT: slli a0, a0, 32
3845 ; RV64ZICOND-NEXT: mulhu a0, a0, a1
3846 ; RV64ZICOND-NEXT: srli a0, a0, 32
3847 ; RV64ZICOND-NEXT: seqz a0, a0
3848 ; RV64ZICOND-NEXT: ret
3849 entry:
3850 %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
3851 %obit = extractvalue {i32, i1} %t, 1
3852 %ret = xor i1 %obit, true
3853 ret i1 %ret
3854 }
3856 define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
3857 ; RV32-LABEL: umulo.select.i64:
3858 ; RV32: # %bb.0: # %entry
3859 ; RV32-NEXT: mul a4, a3, a0
3860 ; RV32-NEXT: mul a5, a1, a2
3861 ; RV32-NEXT: add a4, a5, a4
3862 ; RV32-NEXT: mulhu a5, a0, a2
3863 ; RV32-NEXT: add a4, a5, a4
3864 ; RV32-NEXT: sltu a4, a4, a5
3865 ; RV32-NEXT: snez a5, a3
3866 ; RV32-NEXT: snez a6, a1
3867 ; RV32-NEXT: and a5, a6, a5
3868 ; RV32-NEXT: mulhu a6, a1, a2
3869 ; RV32-NEXT: snez a6, a6
3870 ; RV32-NEXT: or a5, a5, a6
3871 ; RV32-NEXT: mulhu a6, a3, a0
3872 ; RV32-NEXT: snez a6, a6
3873 ; RV32-NEXT: or a5, a5, a6
3874 ; RV32-NEXT: or a4, a5, a4
3875 ; RV32-NEXT: bnez a4, .LBB50_2
3876 ; RV32-NEXT: # %bb.1: # %entry
3877 ; RV32-NEXT: mv a0, a2
3878 ; RV32-NEXT: mv a1, a3
3879 ; RV32-NEXT: .LBB50_2: # %entry
3880 ; RV32-NEXT: ret
3881 ;
3882 ; RV64-LABEL: umulo.select.i64:
3883 ; RV64: # %bb.0: # %entry
3884 ; RV64-NEXT: mulhu a2, a0, a1
3885 ; RV64-NEXT: bnez a2, .LBB50_2
3886 ; RV64-NEXT: # %bb.1: # %entry
3887 ; RV64-NEXT: mv a0, a1
3888 ; RV64-NEXT: .LBB50_2: # %entry
3889 ; RV64-NEXT: ret
3890 ;
3891 ; RV32ZBA-LABEL: umulo.select.i64:
3892 ; RV32ZBA: # %bb.0: # %entry
3893 ; RV32ZBA-NEXT: mul a4, a3, a0
3894 ; RV32ZBA-NEXT: mul a5, a1, a2
3895 ; RV32ZBA-NEXT: add a4, a5, a4
3896 ; RV32ZBA-NEXT: mulhu a5, a0, a2
3897 ; RV32ZBA-NEXT: add a4, a5, a4
3898 ; RV32ZBA-NEXT: sltu a4, a4, a5
3899 ; RV32ZBA-NEXT: snez a5, a3
3900 ; RV32ZBA-NEXT: snez a6, a1
3901 ; RV32ZBA-NEXT: and a5, a6, a5
3902 ; RV32ZBA-NEXT: mulhu a6, a1, a2
3903 ; RV32ZBA-NEXT: snez a6, a6
3904 ; RV32ZBA-NEXT: or a5, a5, a6
3905 ; RV32ZBA-NEXT: mulhu a6, a3, a0
3906 ; RV32ZBA-NEXT: snez a6, a6
3907 ; RV32ZBA-NEXT: or a5, a5, a6
3908 ; RV32ZBA-NEXT: or a4, a5, a4
3909 ; RV32ZBA-NEXT: bnez a4, .LBB50_2
3910 ; RV32ZBA-NEXT: # %bb.1: # %entry
3911 ; RV32ZBA-NEXT: mv a0, a2
3912 ; RV32ZBA-NEXT: mv a1, a3
3913 ; RV32ZBA-NEXT: .LBB50_2: # %entry
3914 ; RV32ZBA-NEXT: ret
3915 ;
3916 ; RV64ZBA-LABEL: umulo.select.i64:
3917 ; RV64ZBA: # %bb.0: # %entry
3918 ; RV64ZBA-NEXT: mulhu a2, a0, a1
3919 ; RV64ZBA-NEXT: bnez a2, .LBB50_2
3920 ; RV64ZBA-NEXT: # %bb.1: # %entry
3921 ; RV64ZBA-NEXT: mv a0, a1
3922 ; RV64ZBA-NEXT: .LBB50_2: # %entry
3923 ; RV64ZBA-NEXT: ret
3924 ;
3925 ; RV32ZICOND-LABEL: umulo.select.i64:
3926 ; RV32ZICOND: # %bb.0: # %entry
3927 ; RV32ZICOND-NEXT: mul a4, a3, a0
3928 ; RV32ZICOND-NEXT: mul a5, a1, a2
3929 ; RV32ZICOND-NEXT: add a4, a5, a4
3930 ; RV32ZICOND-NEXT: mulhu a5, a0, a2
3931 ; RV32ZICOND-NEXT: add a4, a5, a4
3932 ; RV32ZICOND-NEXT: sltu a4, a4, a5
3933 ; RV32ZICOND-NEXT: snez a5, a3
3934 ; RV32ZICOND-NEXT: snez a6, a1
3935 ; RV32ZICOND-NEXT: and a5, a6, a5
3936 ; RV32ZICOND-NEXT: mulhu a6, a1, a2
3937 ; RV32ZICOND-NEXT: snez a6, a6
3938 ; RV32ZICOND-NEXT: or a5, a5, a6
3939 ; RV32ZICOND-NEXT: mulhu a6, a3, a0
3940 ; RV32ZICOND-NEXT: snez a6, a6
3941 ; RV32ZICOND-NEXT: or a5, a5, a6
3942 ; RV32ZICOND-NEXT: or a4, a5, a4
3943 ; RV32ZICOND-NEXT: czero.nez a2, a2, a4
3944 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a4
3945 ; RV32ZICOND-NEXT: or a0, a0, a2
3946 ; RV32ZICOND-NEXT: czero.nez a2, a3, a4
3947 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a4
3948 ; RV32ZICOND-NEXT: or a1, a1, a2
3949 ; RV32ZICOND-NEXT: ret
3950 ;
3951 ; RV64ZICOND-LABEL: umulo.select.i64:
3952 ; RV64ZICOND: # %bb.0: # %entry
3953 ; RV64ZICOND-NEXT: mulhu a2, a0, a1
3954 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2
3955 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
3956 ; RV64ZICOND-NEXT: or a0, a0, a1
3957 ; RV64ZICOND-NEXT: ret
3958 entry:
3959 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
3960 %obit = extractvalue {i64, i1} %t, 1
3961 %ret = select i1 %obit, i64 %v1, i64 %v2
3962 ret i64 %ret
3963 }
3965 define i1 @umulo.not.i64(i64 %v1, i64 %v2) {
3966 ; RV32-LABEL: umulo.not.i64:
3967 ; RV32: # %bb.0: # %entry
3968 ; RV32-NEXT: mul a4, a3, a0
3969 ; RV32-NEXT: mul a5, a1, a2
3970 ; RV32-NEXT: add a4, a5, a4
3971 ; RV32-NEXT: mulhu a5, a0, a2
3972 ; RV32-NEXT: add a4, a5, a4
3973 ; RV32-NEXT: sltu a4, a4, a5
3974 ; RV32-NEXT: snez a5, a3
3975 ; RV32-NEXT: snez a6, a1
3976 ; RV32-NEXT: and a5, a6, a5
3977 ; RV32-NEXT: mulhu a1, a1, a2
3978 ; RV32-NEXT: snez a1, a1
3979 ; RV32-NEXT: or a1, a5, a1
3980 ; RV32-NEXT: mulhu a0, a3, a0
3981 ; RV32-NEXT: snez a0, a0
3982 ; RV32-NEXT: or a0, a1, a0
3983 ; RV32-NEXT: or a0, a0, a4
3984 ; RV32-NEXT: xori a0, a0, 1
3985 ; RV32-NEXT: ret
3986 ;
3987 ; RV64-LABEL: umulo.not.i64:
3988 ; RV64: # %bb.0: # %entry
3989 ; RV64-NEXT: mulhu a0, a0, a1
3990 ; RV64-NEXT: seqz a0, a0
3991 ; RV64-NEXT: ret
3992 ;
3993 ; RV32ZBA-LABEL: umulo.not.i64:
3994 ; RV32ZBA: # %bb.0: # %entry
3995 ; RV32ZBA-NEXT: mul a4, a3, a0
3996 ; RV32ZBA-NEXT: mul a5, a1, a2
3997 ; RV32ZBA-NEXT: add a4, a5, a4
3998 ; RV32ZBA-NEXT: mulhu a5, a0, a2
3999 ; RV32ZBA-NEXT: add a4, a5, a4
4000 ; RV32ZBA-NEXT: sltu a4, a4, a5
4001 ; RV32ZBA-NEXT: snez a5, a3
4002 ; RV32ZBA-NEXT: snez a6, a1
4003 ; RV32ZBA-NEXT: and a5, a6, a5
4004 ; RV32ZBA-NEXT: mulhu a1, a1, a2
4005 ; RV32ZBA-NEXT: snez a1, a1
4006 ; RV32ZBA-NEXT: or a1, a5, a1
4007 ; RV32ZBA-NEXT: mulhu a0, a3, a0
4008 ; RV32ZBA-NEXT: snez a0, a0
4009 ; RV32ZBA-NEXT: or a0, a1, a0
4010 ; RV32ZBA-NEXT: or a0, a0, a4
4011 ; RV32ZBA-NEXT: xori a0, a0, 1
4012 ; RV32ZBA-NEXT: ret
4013 ;
4014 ; RV64ZBA-LABEL: umulo.not.i64:
4015 ; RV64ZBA: # %bb.0: # %entry
4016 ; RV64ZBA-NEXT: mulhu a0, a0, a1
4017 ; RV64ZBA-NEXT: seqz a0, a0
4018 ; RV64ZBA-NEXT: ret
4019 ;
4020 ; RV32ZICOND-LABEL: umulo.not.i64:
4021 ; RV32ZICOND: # %bb.0: # %entry
4022 ; RV32ZICOND-NEXT: mul a4, a3, a0
4023 ; RV32ZICOND-NEXT: mul a5, a1, a2
4024 ; RV32ZICOND-NEXT: add a4, a5, a4
4025 ; RV32ZICOND-NEXT: mulhu a5, a0, a2
4026 ; RV32ZICOND-NEXT: add a4, a5, a4
4027 ; RV32ZICOND-NEXT: sltu a4, a4, a5
4028 ; RV32ZICOND-NEXT: snez a5, a3
4029 ; RV32ZICOND-NEXT: snez a6, a1
4030 ; RV32ZICOND-NEXT: and a5, a6, a5
4031 ; RV32ZICOND-NEXT: mulhu a1, a1, a2
4032 ; RV32ZICOND-NEXT: snez a1, a1
4033 ; RV32ZICOND-NEXT: or a1, a5, a1
4034 ; RV32ZICOND-NEXT: mulhu a0, a3, a0
4035 ; RV32ZICOND-NEXT: snez a0, a0
4036 ; RV32ZICOND-NEXT: or a0, a1, a0
4037 ; RV32ZICOND-NEXT: or a0, a0, a4
4038 ; RV32ZICOND-NEXT: xori a0, a0, 1
4039 ; RV32ZICOND-NEXT: ret
4040 ;
4041 ; RV64ZICOND-LABEL: umulo.not.i64:
4042 ; RV64ZICOND: # %bb.0: # %entry
4043 ; RV64ZICOND-NEXT: mulhu a0, a0, a1
4044 ; RV64ZICOND-NEXT: seqz a0, a0
4045 ; RV64ZICOND-NEXT: ret
4046 entry:
4047 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
4048 %obit = extractvalue {i64, i1} %t, 1
4049 %ret = xor i1 %obit, true
4050 ret i1 %ret
4051 }
4054 ;
4055 ; Check the use of the overflow bit in combination with a branch instruction.
4056 ;
4057 define zeroext i1 @saddo.br.i32(i32 signext %v1, i32 signext %v2) {
4058 ; RV32-LABEL: saddo.br.i32:
4059 ; RV32: # %bb.0: # %entry
4060 ; RV32-NEXT: add a2, a0, a1
4061 ; RV32-NEXT: slt a0, a2, a0
4062 ; RV32-NEXT: slti a1, a1, 0
4063 ; RV32-NEXT: beq a1, a0, .LBB52_2
4064 ; RV32-NEXT: # %bb.1: # %overflow
4065 ; RV32-NEXT: li a0, 0
4066 ; RV32-NEXT: ret
4067 ; RV32-NEXT: .LBB52_2: # %continue
4068 ; RV32-NEXT: li a0, 1
4069 ; RV32-NEXT: ret
4070 ;
4071 ; RV64-LABEL: saddo.br.i32:
4072 ; RV64: # %bb.0: # %entry
4073 ; RV64-NEXT: add a2, a0, a1
4074 ; RV64-NEXT: addw a0, a0, a1
4075 ; RV64-NEXT: beq a0, a2, .LBB52_2
4076 ; RV64-NEXT: # %bb.1: # %overflow
4077 ; RV64-NEXT: li a0, 0
4078 ; RV64-NEXT: ret
4079 ; RV64-NEXT: .LBB52_2: # %continue
4080 ; RV64-NEXT: li a0, 1
4081 ; RV64-NEXT: ret
4082 ;
4083 ; RV32ZBA-LABEL: saddo.br.i32:
4084 ; RV32ZBA: # %bb.0: # %entry
4085 ; RV32ZBA-NEXT: add a2, a0, a1
4086 ; RV32ZBA-NEXT: slt a0, a2, a0
4087 ; RV32ZBA-NEXT: slti a1, a1, 0
4088 ; RV32ZBA-NEXT: beq a1, a0, .LBB52_2
4089 ; RV32ZBA-NEXT: # %bb.1: # %overflow
4090 ; RV32ZBA-NEXT: li a0, 0
4091 ; RV32ZBA-NEXT: ret
4092 ; RV32ZBA-NEXT: .LBB52_2: # %continue
4093 ; RV32ZBA-NEXT: li a0, 1
4094 ; RV32ZBA-NEXT: ret
4095 ;
4096 ; RV64ZBA-LABEL: saddo.br.i32:
4097 ; RV64ZBA: # %bb.0: # %entry
4098 ; RV64ZBA-NEXT: add a2, a0, a1
4099 ; RV64ZBA-NEXT: addw a0, a0, a1
4100 ; RV64ZBA-NEXT: beq a0, a2, .LBB52_2
4101 ; RV64ZBA-NEXT: # %bb.1: # %overflow
4102 ; RV64ZBA-NEXT: li a0, 0
4103 ; RV64ZBA-NEXT: ret
4104 ; RV64ZBA-NEXT: .LBB52_2: # %continue
4105 ; RV64ZBA-NEXT: li a0, 1
4106 ; RV64ZBA-NEXT: ret
4107 ;
4108 ; RV32ZICOND-LABEL: saddo.br.i32:
4109 ; RV32ZICOND: # %bb.0: # %entry
4110 ; RV32ZICOND-NEXT: add a2, a0, a1
4111 ; RV32ZICOND-NEXT: slt a0, a2, a0
4112 ; RV32ZICOND-NEXT: slti a1, a1, 0
4113 ; RV32ZICOND-NEXT: beq a1, a0, .LBB52_2
4114 ; RV32ZICOND-NEXT: # %bb.1: # %overflow
4115 ; RV32ZICOND-NEXT: li a0, 0
4116 ; RV32ZICOND-NEXT: ret
4117 ; RV32ZICOND-NEXT: .LBB52_2: # %continue
4118 ; RV32ZICOND-NEXT: li a0, 1
4119 ; RV32ZICOND-NEXT: ret
4120 ;
4121 ; RV64ZICOND-LABEL: saddo.br.i32:
4122 ; RV64ZICOND: # %bb.0: # %entry
4123 ; RV64ZICOND-NEXT: add a2, a0, a1
4124 ; RV64ZICOND-NEXT: addw a0, a0, a1
4125 ; RV64ZICOND-NEXT: beq a0, a2, .LBB52_2
4126 ; RV64ZICOND-NEXT: # %bb.1: # %overflow
4127 ; RV64ZICOND-NEXT: li a0, 0
4128 ; RV64ZICOND-NEXT: ret
4129 ; RV64ZICOND-NEXT: .LBB52_2: # %continue
4130 ; RV64ZICOND-NEXT: li a0, 1
4131 ; RV64ZICOND-NEXT: ret
4132 entry:
4133 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
4134 %val = extractvalue {i32, i1} %t, 0
4135 %obit = extractvalue {i32, i1} %t, 1
4136 br i1 %obit, label %overflow, label %continue
4138 overflow:
4139 ret i1 false
4141 continue:
4142 ret i1 true
4143 }
4145 define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
4146 ; RV32-LABEL: saddo.br.i64:
4147 ; RV32: # %bb.0: # %entry
4148 ; RV32-NEXT: add a4, a1, a3
4149 ; RV32-NEXT: add a2, a0, a2
4150 ; RV32-NEXT: sltu a0, a2, a0
4151 ; RV32-NEXT: add a0, a4, a0
4152 ; RV32-NEXT: xor a0, a1, a0
4153 ; RV32-NEXT: xor a1, a1, a3
4154 ; RV32-NEXT: not a1, a1
4155 ; RV32-NEXT: and a0, a1, a0
4156 ; RV32-NEXT: bgez a0, .LBB53_2
4157 ; RV32-NEXT: # %bb.1: # %overflow
4158 ; RV32-NEXT: li a0, 0
4159 ; RV32-NEXT: ret
4160 ; RV32-NEXT: .LBB53_2: # %continue
4161 ; RV32-NEXT: li a0, 1
4162 ; RV32-NEXT: ret
4163 ;
4164 ; RV64-LABEL: saddo.br.i64:
4165 ; RV64: # %bb.0: # %entry
4166 ; RV64-NEXT: add a2, a0, a1
4167 ; RV64-NEXT: slt a0, a2, a0
4168 ; RV64-NEXT: slti a1, a1, 0
4169 ; RV64-NEXT: beq a1, a0, .LBB53_2
4170 ; RV64-NEXT: # %bb.1: # %overflow
4171 ; RV64-NEXT: li a0, 0
4172 ; RV64-NEXT: ret
4173 ; RV64-NEXT: .LBB53_2: # %continue
4174 ; RV64-NEXT: li a0, 1
4175 ; RV64-NEXT: ret
4176 ;
4177 ; RV32ZBA-LABEL: saddo.br.i64:
4178 ; RV32ZBA: # %bb.0: # %entry
4179 ; RV32ZBA-NEXT: add a4, a1, a3
4180 ; RV32ZBA-NEXT: add a2, a0, a2
4181 ; RV32ZBA-NEXT: sltu a0, a2, a0
4182 ; RV32ZBA-NEXT: add a0, a4, a0
4183 ; RV32ZBA-NEXT: xor a0, a1, a0
4184 ; RV32ZBA-NEXT: xor a1, a1, a3
4185 ; RV32ZBA-NEXT: not a1, a1
4186 ; RV32ZBA-NEXT: and a0, a1, a0
4187 ; RV32ZBA-NEXT: bgez a0, .LBB53_2
4188 ; RV32ZBA-NEXT: # %bb.1: # %overflow
4189 ; RV32ZBA-NEXT: li a0, 0
4190 ; RV32ZBA-NEXT: ret
4191 ; RV32ZBA-NEXT: .LBB53_2: # %continue
4192 ; RV32ZBA-NEXT: li a0, 1
4193 ; RV32ZBA-NEXT: ret
4194 ;
4195 ; RV64ZBA-LABEL: saddo.br.i64:
4196 ; RV64ZBA: # %bb.0: # %entry
4197 ; RV64ZBA-NEXT: add a2, a0, a1
4198 ; RV64ZBA-NEXT: slt a0, a2, a0
4199 ; RV64ZBA-NEXT: slti a1, a1, 0
4200 ; RV64ZBA-NEXT: beq a1, a0, .LBB53_2
4201 ; RV64ZBA-NEXT: # %bb.1: # %overflow
4202 ; RV64ZBA-NEXT: li a0, 0
4203 ; RV64ZBA-NEXT: ret
4204 ; RV64ZBA-NEXT: .LBB53_2: # %continue
4205 ; RV64ZBA-NEXT: li a0, 1
4206 ; RV64ZBA-NEXT: ret
4207 ;
4208 ; RV32ZICOND-LABEL: saddo.br.i64:
4209 ; RV32ZICOND: # %bb.0: # %entry
4210 ; RV32ZICOND-NEXT: add a4, a1, a3
4211 ; RV32ZICOND-NEXT: add a2, a0, a2
4212 ; RV32ZICOND-NEXT: sltu a0, a2, a0
4213 ; RV32ZICOND-NEXT: add a0, a4, a0
4214 ; RV32ZICOND-NEXT: xor a0, a1, a0
4215 ; RV32ZICOND-NEXT: xor a1, a1, a3
4216 ; RV32ZICOND-NEXT: not a1, a1
4217 ; RV32ZICOND-NEXT: and a0, a1, a0
4218 ; RV32ZICOND-NEXT: bgez a0, .LBB53_2
4219 ; RV32ZICOND-NEXT: # %bb.1: # %overflow
4220 ; RV32ZICOND-NEXT: li a0, 0
4221 ; RV32ZICOND-NEXT: ret
4222 ; RV32ZICOND-NEXT: .LBB53_2: # %continue
4223 ; RV32ZICOND-NEXT: li a0, 1
4224 ; RV32ZICOND-NEXT: ret
4225 ;
4226 ; RV64ZICOND-LABEL: saddo.br.i64:
4227 ; RV64ZICOND: # %bb.0: # %entry
4228 ; RV64ZICOND-NEXT: add a2, a0, a1
4229 ; RV64ZICOND-NEXT: slt a0, a2, a0
4230 ; RV64ZICOND-NEXT: slti a1, a1, 0
4231 ; RV64ZICOND-NEXT: beq a1, a0, .LBB53_2
4232 ; RV64ZICOND-NEXT: # %bb.1: # %overflow
4233 ; RV64ZICOND-NEXT: li a0, 0
4234 ; RV64ZICOND-NEXT: ret
4235 ; RV64ZICOND-NEXT: .LBB53_2: # %continue
4236 ; RV64ZICOND-NEXT: li a0, 1
4237 ; RV64ZICOND-NEXT: ret
4238 entry:
4239 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
4240 %val = extractvalue {i64, i1} %t, 0
4241 %obit = extractvalue {i64, i1} %t, 1
4242 br i1 %obit, label %overflow, label %continue
4244 overflow:
4245 ret i1 false
4247 continue:
4248 ret i1 true
4249 }
4251 define zeroext i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
4252 ; RV32-LABEL: uaddo.br.i32:
4253 ; RV32: # %bb.0: # %entry
4254 ; RV32-NEXT: add a1, a0, a1
4255 ; RV32-NEXT: bgeu a1, a0, .LBB54_2
4256 ; RV32-NEXT: # %bb.1: # %overflow
4257 ; RV32-NEXT: li a0, 0
4258 ; RV32-NEXT: ret
4259 ; RV32-NEXT: .LBB54_2: # %continue
4260 ; RV32-NEXT: li a0, 1
4261 ; RV32-NEXT: ret
4262 ;
4263 ; RV64-LABEL: uaddo.br.i32:
4264 ; RV64: # %bb.0: # %entry
4265 ; RV64-NEXT: addw a1, a0, a1
4266 ; RV64-NEXT: sext.w a0, a0
4267 ; RV64-NEXT: bgeu a1, a0, .LBB54_2
4268 ; RV64-NEXT: # %bb.1: # %overflow
4269 ; RV64-NEXT: li a0, 0
4270 ; RV64-NEXT: ret
4271 ; RV64-NEXT: .LBB54_2: # %continue
4272 ; RV64-NEXT: li a0, 1
4273 ; RV64-NEXT: ret
4274 ;
4275 ; RV32ZBA-LABEL: uaddo.br.i32:
4276 ; RV32ZBA: # %bb.0: # %entry
4277 ; RV32ZBA-NEXT: add a1, a0, a1
4278 ; RV32ZBA-NEXT: bgeu a1, a0, .LBB54_2
4279 ; RV32ZBA-NEXT: # %bb.1: # %overflow
4280 ; RV32ZBA-NEXT: li a0, 0
4281 ; RV32ZBA-NEXT: ret
4282 ; RV32ZBA-NEXT: .LBB54_2: # %continue
4283 ; RV32ZBA-NEXT: li a0, 1
4284 ; RV32ZBA-NEXT: ret
4285 ;
4286 ; RV64ZBA-LABEL: uaddo.br.i32:
4287 ; RV64ZBA: # %bb.0: # %entry
4288 ; RV64ZBA-NEXT: addw a1, a0, a1
4289 ; RV64ZBA-NEXT: sext.w a0, a0
4290 ; RV64ZBA-NEXT: bgeu a1, a0, .LBB54_2
4291 ; RV64ZBA-NEXT: # %bb.1: # %overflow
4292 ; RV64ZBA-NEXT: li a0, 0
4293 ; RV64ZBA-NEXT: ret
4294 ; RV64ZBA-NEXT: .LBB54_2: # %continue
4295 ; RV64ZBA-NEXT: li a0, 1
4296 ; RV64ZBA-NEXT: ret
4297 ;
4298 ; RV32ZICOND-LABEL: uaddo.br.i32:
4299 ; RV32ZICOND: # %bb.0: # %entry
4300 ; RV32ZICOND-NEXT: add a1, a0, a1
4301 ; RV32ZICOND-NEXT: bgeu a1, a0, .LBB54_2
4302 ; RV32ZICOND-NEXT: # %bb.1: # %overflow
4303 ; RV32ZICOND-NEXT: li a0, 0
4304 ; RV32ZICOND-NEXT: ret
4305 ; RV32ZICOND-NEXT: .LBB54_2: # %continue
4306 ; RV32ZICOND-NEXT: li a0, 1
4307 ; RV32ZICOND-NEXT: ret
4308 ;
4309 ; RV64ZICOND-LABEL: uaddo.br.i32:
4310 ; RV64ZICOND: # %bb.0: # %entry
4311 ; RV64ZICOND-NEXT: addw a1, a0, a1
4312 ; RV64ZICOND-NEXT: sext.w a0, a0
4313 ; RV64ZICOND-NEXT: bgeu a1, a0, .LBB54_2
4314 ; RV64ZICOND-NEXT: # %bb.1: # %overflow
4315 ; RV64ZICOND-NEXT: li a0, 0
4316 ; RV64ZICOND-NEXT: ret
4317 ; RV64ZICOND-NEXT: .LBB54_2: # %continue
4318 ; RV64ZICOND-NEXT: li a0, 1
4319 ; RV64ZICOND-NEXT: ret
4320 entry:
4321 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
4322 %val = extractvalue {i32, i1} %t, 0
4323 %obit = extractvalue {i32, i1} %t, 1
4324 br i1 %obit, label %overflow, label %continue
4326 overflow:
4327 ret i1 false
4329 continue:
4330 ret i1 true
4331 }
4333 define zeroext i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
4334 ; RV32-LABEL: uaddo.br.i64:
4335 ; RV32: # %bb.0: # %entry
4336 ; RV32-NEXT: add a3, a1, a3
4337 ; RV32-NEXT: add a2, a0, a2
4338 ; RV32-NEXT: sltu a0, a2, a0
4339 ; RV32-NEXT: add a2, a3, a0
4340 ; RV32-NEXT: beq a2, a1, .LBB55_2
4341 ; RV32-NEXT: # %bb.1: # %entry
4342 ; RV32-NEXT: sltu a0, a2, a1
4343 ; RV32-NEXT: .LBB55_2: # %entry
4344 ; RV32-NEXT: beqz a0, .LBB55_4
4345 ; RV32-NEXT: # %bb.3: # %overflow
4346 ; RV32-NEXT: li a0, 0
4347 ; RV32-NEXT: ret
4348 ; RV32-NEXT: .LBB55_4: # %continue
4349 ; RV32-NEXT: li a0, 1
4350 ; RV32-NEXT: ret
4351 ;
4352 ; RV64-LABEL: uaddo.br.i64:
4353 ; RV64: # %bb.0: # %entry
4354 ; RV64-NEXT: add a1, a0, a1
4355 ; RV64-NEXT: bgeu a1, a0, .LBB55_2
4356 ; RV64-NEXT: # %bb.1: # %overflow
4357 ; RV64-NEXT: li a0, 0
4358 ; RV64-NEXT: ret
4359 ; RV64-NEXT: .LBB55_2: # %continue
4360 ; RV64-NEXT: li a0, 1
4361 ; RV64-NEXT: ret
4362 ;
4363 ; RV32ZBA-LABEL: uaddo.br.i64:
4364 ; RV32ZBA: # %bb.0: # %entry
4365 ; RV32ZBA-NEXT: add a3, a1, a3
4366 ; RV32ZBA-NEXT: add a2, a0, a2
4367 ; RV32ZBA-NEXT: sltu a0, a2, a0
4368 ; RV32ZBA-NEXT: add a2, a3, a0
4369 ; RV32ZBA-NEXT: beq a2, a1, .LBB55_2
4370 ; RV32ZBA-NEXT: # %bb.1: # %entry
4371 ; RV32ZBA-NEXT: sltu a0, a2, a1
4372 ; RV32ZBA-NEXT: .LBB55_2: # %entry
4373 ; RV32ZBA-NEXT: beqz a0, .LBB55_4
4374 ; RV32ZBA-NEXT: # %bb.3: # %overflow
4375 ; RV32ZBA-NEXT: li a0, 0
4376 ; RV32ZBA-NEXT: ret
4377 ; RV32ZBA-NEXT: .LBB55_4: # %continue
4378 ; RV32ZBA-NEXT: li a0, 1
4379 ; RV32ZBA-NEXT: ret
4380 ;
4381 ; RV64ZBA-LABEL: uaddo.br.i64:
4382 ; RV64ZBA: # %bb.0: # %entry
4383 ; RV64ZBA-NEXT: add a1, a0, a1
4384 ; RV64ZBA-NEXT: bgeu a1, a0, .LBB55_2
4385 ; RV64ZBA-NEXT: # %bb.1: # %overflow
4386 ; RV64ZBA-NEXT: li a0, 0
4387 ; RV64ZBA-NEXT: ret
4388 ; RV64ZBA-NEXT: .LBB55_2: # %continue
4389 ; RV64ZBA-NEXT: li a0, 1
4390 ; RV64ZBA-NEXT: ret
4391 ;
4392 ; RV32ZICOND-LABEL: uaddo.br.i64:
4393 ; RV32ZICOND: # %bb.0: # %entry
4394 ; RV32ZICOND-NEXT: add a3, a1, a3
4395 ; RV32ZICOND-NEXT: add a2, a0, a2
4396 ; RV32ZICOND-NEXT: sltu a0, a2, a0
4397 ; RV32ZICOND-NEXT: add a3, a3, a0
4398 ; RV32ZICOND-NEXT: xor a2, a3, a1
4399 ; RV32ZICOND-NEXT: sltu a1, a3, a1
4400 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a2
4401 ; RV32ZICOND-NEXT: czero.nez a0, a0, a2
4402 ; RV32ZICOND-NEXT: or a0, a0, a1
4403 ; RV32ZICOND-NEXT: beqz a0, .LBB55_2
4404 ; RV32ZICOND-NEXT: # %bb.1: # %overflow
4405 ; RV32ZICOND-NEXT: li a0, 0
4406 ; RV32ZICOND-NEXT: ret
4407 ; RV32ZICOND-NEXT: .LBB55_2: # %continue
4408 ; RV32ZICOND-NEXT: li a0, 1
4409 ; RV32ZICOND-NEXT: ret
4410 ;
4411 ; RV64ZICOND-LABEL: uaddo.br.i64:
4412 ; RV64ZICOND: # %bb.0: # %entry
4413 ; RV64ZICOND-NEXT: add a1, a0, a1
4414 ; RV64ZICOND-NEXT: bgeu a1, a0, .LBB55_2
4415 ; RV64ZICOND-NEXT: # %bb.1: # %overflow
4416 ; RV64ZICOND-NEXT: li a0, 0
4417 ; RV64ZICOND-NEXT: ret
4418 ; RV64ZICOND-NEXT: .LBB55_2: # %continue
4419 ; RV64ZICOND-NEXT: li a0, 1
4420 ; RV64ZICOND-NEXT: ret
4421 entry:
4422 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
4423 %val = extractvalue {i64, i1} %t, 0
4424 %obit = extractvalue {i64, i1} %t, 1
4425 br i1 %obit, label %overflow, label %continue
4427 overflow:
4428 ret i1 false
4430 continue:
4431 ret i1 true
4432 }
4434 define zeroext i1 @ssubo.br.i32(i32 signext %v1, i32 signext %v2) {
4435 ; RV32-LABEL: ssubo.br.i32:
4436 ; RV32: # %bb.0: # %entry
4437 ; RV32-NEXT: sgtz a2, a1
4438 ; RV32-NEXT: sub a1, a0, a1
4439 ; RV32-NEXT: slt a0, a1, a0
4440 ; RV32-NEXT: beq a2, a0, .LBB56_2
4441 ; RV32-NEXT: # %bb.1: # %overflow
4442 ; RV32-NEXT: li a0, 0
4443 ; RV32-NEXT: ret
4444 ; RV32-NEXT: .LBB56_2: # %continue
4445 ; RV32-NEXT: li a0, 1
4446 ; RV32-NEXT: ret
4447 ;
4448 ; RV64-LABEL: ssubo.br.i32:
4449 ; RV64: # %bb.0: # %entry
4450 ; RV64-NEXT: sub a2, a0, a1
4451 ; RV64-NEXT: subw a0, a0, a1
4452 ; RV64-NEXT: beq a0, a2, .LBB56_2
4453 ; RV64-NEXT: # %bb.1: # %overflow
4454 ; RV64-NEXT: li a0, 0
4455 ; RV64-NEXT: ret
4456 ; RV64-NEXT: .LBB56_2: # %continue
4457 ; RV64-NEXT: li a0, 1
4458 ; RV64-NEXT: ret
4459 ;
4460 ; RV32ZBA-LABEL: ssubo.br.i32:
4461 ; RV32ZBA: # %bb.0: # %entry
4462 ; RV32ZBA-NEXT: sgtz a2, a1
4463 ; RV32ZBA-NEXT: sub a1, a0, a1
4464 ; RV32ZBA-NEXT: slt a0, a1, a0
4465 ; RV32ZBA-NEXT: beq a2, a0, .LBB56_2
4466 ; RV32ZBA-NEXT: # %bb.1: # %overflow
4467 ; RV32ZBA-NEXT: li a0, 0
4468 ; RV32ZBA-NEXT: ret
4469 ; RV32ZBA-NEXT: .LBB56_2: # %continue
4470 ; RV32ZBA-NEXT: li a0, 1
4471 ; RV32ZBA-NEXT: ret
4472 ;
4473 ; RV64ZBA-LABEL: ssubo.br.i32:
4474 ; RV64ZBA: # %bb.0: # %entry
4475 ; RV64ZBA-NEXT: sub a2, a0, a1
4476 ; RV64ZBA-NEXT: subw a0, a0, a1
4477 ; RV64ZBA-NEXT: beq a0, a2, .LBB56_2
4478 ; RV64ZBA-NEXT: # %bb.1: # %overflow
4479 ; RV64ZBA-NEXT: li a0, 0
4480 ; RV64ZBA-NEXT: ret
4481 ; RV64ZBA-NEXT: .LBB56_2: # %continue
4482 ; RV64ZBA-NEXT: li a0, 1
4483 ; RV64ZBA-NEXT: ret
4484 ;
4485 ; RV32ZICOND-LABEL: ssubo.br.i32:
4486 ; RV32ZICOND: # %bb.0: # %entry
4487 ; RV32ZICOND-NEXT: sgtz a2, a1
4488 ; RV32ZICOND-NEXT: sub a1, a0, a1
4489 ; RV32ZICOND-NEXT: slt a0, a1, a0
4490 ; RV32ZICOND-NEXT: beq a2, a0, .LBB56_2
4491 ; RV32ZICOND-NEXT: # %bb.1: # %overflow
4492 ; RV32ZICOND-NEXT: li a0, 0
4493 ; RV32ZICOND-NEXT: ret
4494 ; RV32ZICOND-NEXT: .LBB56_2: # %continue
4495 ; RV32ZICOND-NEXT: li a0, 1
4496 ; RV32ZICOND-NEXT: ret
4497 ;
4498 ; RV64ZICOND-LABEL: ssubo.br.i32:
4499 ; RV64ZICOND: # %bb.0: # %entry
4500 ; RV64ZICOND-NEXT: sub a2, a0, a1
4501 ; RV64ZICOND-NEXT: subw a0, a0, a1
4502 ; RV64ZICOND-NEXT: beq a0, a2, .LBB56_2
4503 ; RV64ZICOND-NEXT: # %bb.1: # %overflow
4504 ; RV64ZICOND-NEXT: li a0, 0
4505 ; RV64ZICOND-NEXT: ret
4506 ; RV64ZICOND-NEXT: .LBB56_2: # %continue
4507 ; RV64ZICOND-NEXT: li a0, 1
4508 ; RV64ZICOND-NEXT: ret
4509 entry:
4510 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
4511 %val = extractvalue {i32, i1} %t, 0
4512 %obit = extractvalue {i32, i1} %t, 1
4513 br i1 %obit, label %overflow, label %continue
4515 overflow:
4516 ret i1 false
4518 continue:
4519 ret i1 true
4520 }
4522 define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
4523 ; RV32-LABEL: ssubo.br.i64:
4524 ; RV32: # %bb.0: # %entry
4525 ; RV32-NEXT: sltu a0, a0, a2
4526 ; RV32-NEXT: sub a2, a1, a3
4527 ; RV32-NEXT: sub a2, a2, a0
4528 ; RV32-NEXT: xor a2, a1, a2
4529 ; RV32-NEXT: xor a1, a1, a3
4530 ; RV32-NEXT: and a1, a1, a2
4531 ; RV32-NEXT: bgez a1, .LBB57_2
4532 ; RV32-NEXT: # %bb.1: # %overflow
4533 ; RV32-NEXT: li a0, 0
4534 ; RV32-NEXT: ret
4535 ; RV32-NEXT: .LBB57_2: # %continue
4536 ; RV32-NEXT: li a0, 1
4537 ; RV32-NEXT: ret
4538 ;
4539 ; RV64-LABEL: ssubo.br.i64:
4540 ; RV64: # %bb.0: # %entry
4541 ; RV64-NEXT: sgtz a2, a1
4542 ; RV64-NEXT: sub a1, a0, a1
4543 ; RV64-NEXT: slt a0, a1, a0
4544 ; RV64-NEXT: beq a2, a0, .LBB57_2
4545 ; RV64-NEXT: # %bb.1: # %overflow
4546 ; RV64-NEXT: li a0, 0
4547 ; RV64-NEXT: ret
4548 ; RV64-NEXT: .LBB57_2: # %continue
4549 ; RV64-NEXT: li a0, 1
4550 ; RV64-NEXT: ret
4551 ;
4552 ; RV32ZBA-LABEL: ssubo.br.i64:
4553 ; RV32ZBA: # %bb.0: # %entry
4554 ; RV32ZBA-NEXT: sltu a0, a0, a2
4555 ; RV32ZBA-NEXT: sub a2, a1, a3
4556 ; RV32ZBA-NEXT: sub a2, a2, a0
4557 ; RV32ZBA-NEXT: xor a2, a1, a2
4558 ; RV32ZBA-NEXT: xor a1, a1, a3
4559 ; RV32ZBA-NEXT: and a1, a1, a2
4560 ; RV32ZBA-NEXT: bgez a1, .LBB57_2
4561 ; RV32ZBA-NEXT: # %bb.1: # %overflow
4562 ; RV32ZBA-NEXT: li a0, 0
4563 ; RV32ZBA-NEXT: ret
4564 ; RV32ZBA-NEXT: .LBB57_2: # %continue
4565 ; RV32ZBA-NEXT: li a0, 1
4566 ; RV32ZBA-NEXT: ret
4567 ;
4568 ; RV64ZBA-LABEL: ssubo.br.i64:
4569 ; RV64ZBA: # %bb.0: # %entry
4570 ; RV64ZBA-NEXT: sgtz a2, a1
4571 ; RV64ZBA-NEXT: sub a1, a0, a1
4572 ; RV64ZBA-NEXT: slt a0, a1, a0
4573 ; RV64ZBA-NEXT: beq a2, a0, .LBB57_2
4574 ; RV64ZBA-NEXT: # %bb.1: # %overflow
4575 ; RV64ZBA-NEXT: li a0, 0
4576 ; RV64ZBA-NEXT: ret
4577 ; RV64ZBA-NEXT: .LBB57_2: # %continue
4578 ; RV64ZBA-NEXT: li a0, 1
4579 ; RV64ZBA-NEXT: ret
4580 ;
4581 ; RV32ZICOND-LABEL: ssubo.br.i64:
4582 ; RV32ZICOND: # %bb.0: # %entry
4583 ; RV32ZICOND-NEXT: sltu a0, a0, a2
4584 ; RV32ZICOND-NEXT: sub a2, a1, a3
4585 ; RV32ZICOND-NEXT: sub a2, a2, a0
4586 ; RV32ZICOND-NEXT: xor a2, a1, a2
4587 ; RV32ZICOND-NEXT: xor a1, a1, a3
4588 ; RV32ZICOND-NEXT: and a1, a1, a2
4589 ; RV32ZICOND-NEXT: bgez a1, .LBB57_2
4590 ; RV32ZICOND-NEXT: # %bb.1: # %overflow
4591 ; RV32ZICOND-NEXT: li a0, 0
4592 ; RV32ZICOND-NEXT: ret
4593 ; RV32ZICOND-NEXT: .LBB57_2: # %continue
4594 ; RV32ZICOND-NEXT: li a0, 1
4595 ; RV32ZICOND-NEXT: ret
4596 ;
4597 ; RV64ZICOND-LABEL: ssubo.br.i64:
4598 ; RV64ZICOND: # %bb.0: # %entry
4599 ; RV64ZICOND-NEXT: sgtz a2, a1
4600 ; RV64ZICOND-NEXT: sub a1, a0, a1
4601 ; RV64ZICOND-NEXT: slt a0, a1, a0
4602 ; RV64ZICOND-NEXT: beq a2, a0, .LBB57_2
4603 ; RV64ZICOND-NEXT: # %bb.1: # %overflow
4604 ; RV64ZICOND-NEXT: li a0, 0
4605 ; RV64ZICOND-NEXT: ret
4606 ; RV64ZICOND-NEXT: .LBB57_2: # %continue
4607 ; RV64ZICOND-NEXT: li a0, 1
4608 ; RV64ZICOND-NEXT: ret
4609 entry:
4610 %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
4611 %val = extractvalue {i64, i1} %t, 0
4612 %obit = extractvalue {i64, i1} %t, 1
4613 br i1 %obit, label %overflow, label %continue
4615 overflow:
4616 ret i1 false
4618 continue:
4619 ret i1 true
4620 }
4622 define zeroext i1 @usubo.br.i32(i32 signext %v1, i32 signext %v2) {
4623 ; RV32-LABEL: usubo.br.i32:
4624 ; RV32: # %bb.0: # %entry
4625 ; RV32-NEXT: sub a1, a0, a1
4626 ; RV32-NEXT: bgeu a0, a1, .LBB58_2
4627 ; RV32-NEXT: # %bb.1: # %overflow
4628 ; RV32-NEXT: li a0, 0
4629 ; RV32-NEXT: ret
4630 ; RV32-NEXT: .LBB58_2: # %continue
4631 ; RV32-NEXT: li a0, 1
4632 ; RV32-NEXT: ret
4633 ;
4634 ; RV64-LABEL: usubo.br.i32:
4635 ; RV64: # %bb.0: # %entry
4636 ; RV64-NEXT: subw a1, a0, a1
4637 ; RV64-NEXT: bgeu a0, a1, .LBB58_2
4638 ; RV64-NEXT: # %bb.1: # %overflow
4639 ; RV64-NEXT: li a0, 0
4640 ; RV64-NEXT: ret
4641 ; RV64-NEXT: .LBB58_2: # %continue
4642 ; RV64-NEXT: li a0, 1
4643 ; RV64-NEXT: ret
4644 ;
4645 ; RV32ZBA-LABEL: usubo.br.i32:
4646 ; RV32ZBA: # %bb.0: # %entry
4647 ; RV32ZBA-NEXT: sub a1, a0, a1
4648 ; RV32ZBA-NEXT: bgeu a0, a1, .LBB58_2
4649 ; RV32ZBA-NEXT: # %bb.1: # %overflow
4650 ; RV32ZBA-NEXT: li a0, 0
4651 ; RV32ZBA-NEXT: ret
4652 ; RV32ZBA-NEXT: .LBB58_2: # %continue
4653 ; RV32ZBA-NEXT: li a0, 1
4654 ; RV32ZBA-NEXT: ret
4655 ;
4656 ; RV64ZBA-LABEL: usubo.br.i32:
4657 ; RV64ZBA: # %bb.0: # %entry
4658 ; RV64ZBA-NEXT: subw a1, a0, a1
4659 ; RV64ZBA-NEXT: bgeu a0, a1, .LBB58_2
4660 ; RV64ZBA-NEXT: # %bb.1: # %overflow
4661 ; RV64ZBA-NEXT: li a0, 0
4662 ; RV64ZBA-NEXT: ret
4663 ; RV64ZBA-NEXT: .LBB58_2: # %continue
4664 ; RV64ZBA-NEXT: li a0, 1
4665 ; RV64ZBA-NEXT: ret
4666 ;
4667 ; RV32ZICOND-LABEL: usubo.br.i32:
4668 ; RV32ZICOND: # %bb.0: # %entry
4669 ; RV32ZICOND-NEXT: sub a1, a0, a1
4670 ; RV32ZICOND-NEXT: bgeu a0, a1, .LBB58_2
4671 ; RV32ZICOND-NEXT: # %bb.1: # %overflow
4672 ; RV32ZICOND-NEXT: li a0, 0
4673 ; RV32ZICOND-NEXT: ret
4674 ; RV32ZICOND-NEXT: .LBB58_2: # %continue
4675 ; RV32ZICOND-NEXT: li a0, 1
4676 ; RV32ZICOND-NEXT: ret
4677 ;
4678 ; RV64ZICOND-LABEL: usubo.br.i32:
4679 ; RV64ZICOND: # %bb.0: # %entry
4680 ; RV64ZICOND-NEXT: subw a1, a0, a1
4681 ; RV64ZICOND-NEXT: bgeu a0, a1, .LBB58_2
4682 ; RV64ZICOND-NEXT: # %bb.1: # %overflow
4683 ; RV64ZICOND-NEXT: li a0, 0
4684 ; RV64ZICOND-NEXT: ret
4685 ; RV64ZICOND-NEXT: .LBB58_2: # %continue
4686 ; RV64ZICOND-NEXT: li a0, 1
4687 ; RV64ZICOND-NEXT: ret
4688 entry:
4689 %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
4690 %val = extractvalue {i32, i1} %t, 0
4691 %obit = extractvalue {i32, i1} %t, 1
4692 br i1 %obit, label %overflow, label %continue
4694 overflow:
4695 ret i1 false
4697 continue:
4698 ret i1 true
4699 }
4701 define zeroext i1 @usubo.br.i64(i64 %v1, i64 %v2) {
4702 ; RV32-LABEL: usubo.br.i64:
4703 ; RV32: # %bb.0: # %entry
4704 ; RV32-NEXT: sltu a4, a0, a2
4705 ; RV32-NEXT: sub a3, a1, a3
4706 ; RV32-NEXT: sub a3, a3, a4
4707 ; RV32-NEXT: beq a3, a1, .LBB59_3
4708 ; RV32-NEXT: # %bb.1: # %entry
4709 ; RV32-NEXT: sltu a0, a1, a3
4710 ; RV32-NEXT: bnez a0, .LBB59_4
4711 ; RV32-NEXT: .LBB59_2: # %continue
4712 ; RV32-NEXT: li a0, 1
4713 ; RV32-NEXT: ret
4714 ; RV32-NEXT: .LBB59_3:
4715 ; RV32-NEXT: sub a1, a0, a2
4716 ; RV32-NEXT: sltu a0, a0, a1
4717 ; RV32-NEXT: beqz a0, .LBB59_2
4718 ; RV32-NEXT: .LBB59_4: # %overflow
4719 ; RV32-NEXT: li a0, 0
4720 ; RV32-NEXT: ret
4721 ;
4722 ; RV64-LABEL: usubo.br.i64:
4723 ; RV64: # %bb.0: # %entry
4724 ; RV64-NEXT: sub a1, a0, a1
4725 ; RV64-NEXT: bgeu a0, a1, .LBB59_2
4726 ; RV64-NEXT: # %bb.1: # %overflow
4727 ; RV64-NEXT: li a0, 0
4728 ; RV64-NEXT: ret
4729 ; RV64-NEXT: .LBB59_2: # %continue
4730 ; RV64-NEXT: li a0, 1
4731 ; RV64-NEXT: ret
4732 ;
4733 ; RV32ZBA-LABEL: usubo.br.i64:
4734 ; RV32ZBA: # %bb.0: # %entry
4735 ; RV32ZBA-NEXT: sltu a4, a0, a2
4736 ; RV32ZBA-NEXT: sub a3, a1, a3
4737 ; RV32ZBA-NEXT: sub a3, a3, a4
4738 ; RV32ZBA-NEXT: beq a3, a1, .LBB59_3
4739 ; RV32ZBA-NEXT: # %bb.1: # %entry
4740 ; RV32ZBA-NEXT: sltu a0, a1, a3
4741 ; RV32ZBA-NEXT: bnez a0, .LBB59_4
4742 ; RV32ZBA-NEXT: .LBB59_2: # %continue
4743 ; RV32ZBA-NEXT: li a0, 1
4744 ; RV32ZBA-NEXT: ret
4745 ; RV32ZBA-NEXT: .LBB59_3:
4746 ; RV32ZBA-NEXT: sub a1, a0, a2
4747 ; RV32ZBA-NEXT: sltu a0, a0, a1
4748 ; RV32ZBA-NEXT: beqz a0, .LBB59_2
4749 ; RV32ZBA-NEXT: .LBB59_4: # %overflow
4750 ; RV32ZBA-NEXT: li a0, 0
4751 ; RV32ZBA-NEXT: ret
4752 ;
4753 ; RV64ZBA-LABEL: usubo.br.i64:
4754 ; RV64ZBA: # %bb.0: # %entry
4755 ; RV64ZBA-NEXT: sub a1, a0, a1
4756 ; RV64ZBA-NEXT: bgeu a0, a1, .LBB59_2
4757 ; RV64ZBA-NEXT: # %bb.1: # %overflow
4758 ; RV64ZBA-NEXT: li a0, 0
4759 ; RV64ZBA-NEXT: ret
4760 ; RV64ZBA-NEXT: .LBB59_2: # %continue
4761 ; RV64ZBA-NEXT: li a0, 1
4762 ; RV64ZBA-NEXT: ret
4763 ;
4764 ; RV32ZICOND-LABEL: usubo.br.i64:
4765 ; RV32ZICOND: # %bb.0: # %entry
4766 ; RV32ZICOND-NEXT: sltu a4, a0, a2
4767 ; RV32ZICOND-NEXT: sub a3, a1, a3
4768 ; RV32ZICOND-NEXT: sub a3, a3, a4
4769 ; RV32ZICOND-NEXT: xor a4, a3, a1
4770 ; RV32ZICOND-NEXT: sltu a1, a1, a3
4771 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a4
4772 ; RV32ZICOND-NEXT: sub a2, a0, a2
4773 ; RV32ZICOND-NEXT: sltu a0, a0, a2
4774 ; RV32ZICOND-NEXT: czero.nez a0, a0, a4
4775 ; RV32ZICOND-NEXT: or a0, a0, a1
4776 ; RV32ZICOND-NEXT: beqz a0, .LBB59_2
4777 ; RV32ZICOND-NEXT: # %bb.1: # %overflow
4778 ; RV32ZICOND-NEXT: li a0, 0
4779 ; RV32ZICOND-NEXT: ret
4780 ; RV32ZICOND-NEXT: .LBB59_2: # %continue
4781 ; RV32ZICOND-NEXT: li a0, 1
4782 ; RV32ZICOND-NEXT: ret
4783 ;
4784 ; RV64ZICOND-LABEL: usubo.br.i64:
4785 ; RV64ZICOND: # %bb.0: # %entry
4786 ; RV64ZICOND-NEXT: sub a1, a0, a1
4787 ; RV64ZICOND-NEXT: bgeu a0, a1, .LBB59_2
4788 ; RV64ZICOND-NEXT: # %bb.1: # %overflow
4789 ; RV64ZICOND-NEXT: li a0, 0
4790 ; RV64ZICOND-NEXT: ret
4791 ; RV64ZICOND-NEXT: .LBB59_2: # %continue
4792 ; RV64ZICOND-NEXT: li a0, 1
4793 ; RV64ZICOND-NEXT: ret
4794 entry:
4795 %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
4796 %val = extractvalue {i64, i1} %t, 0
4797 %obit = extractvalue {i64, i1} %t, 1
4798 br i1 %obit, label %overflow, label %continue
4800 overflow:
4801 ret i1 false
4803 continue:
4804 ret i1 true
4805 }
4807 define zeroext i1 @smulo.br.i32(i32 signext %v1, i32 signext %v2) {
4808 ; RV32-LABEL: smulo.br.i32:
4809 ; RV32: # %bb.0: # %entry
4810 ; RV32-NEXT: mulh a2, a0, a1
4811 ; RV32-NEXT: mul a0, a0, a1
4812 ; RV32-NEXT: srai a0, a0, 31
4813 ; RV32-NEXT: beq a2, a0, .LBB60_2
4814 ; RV32-NEXT: # %bb.1: # %overflow
4815 ; RV32-NEXT: li a0, 0
4816 ; RV32-NEXT: ret
4817 ; RV32-NEXT: .LBB60_2: # %continue
4818 ; RV32-NEXT: li a0, 1
4819 ; RV32-NEXT: ret
4820 ;
4821 ; RV64-LABEL: smulo.br.i32:
4822 ; RV64: # %bb.0: # %entry
4823 ; RV64-NEXT: mul a2, a0, a1
4824 ; RV64-NEXT: mulw a0, a0, a1
4825 ; RV64-NEXT: beq a0, a2, .LBB60_2
4826 ; RV64-NEXT: # %bb.1: # %overflow
4827 ; RV64-NEXT: li a0, 0
4828 ; RV64-NEXT: ret
4829 ; RV64-NEXT: .LBB60_2: # %continue
4830 ; RV64-NEXT: li a0, 1
4831 ; RV64-NEXT: ret
4832 ;
4833 ; RV32ZBA-LABEL: smulo.br.i32:
4834 ; RV32ZBA: # %bb.0: # %entry
4835 ; RV32ZBA-NEXT: mulh a2, a0, a1
4836 ; RV32ZBA-NEXT: mul a0, a0, a1
4837 ; RV32ZBA-NEXT: srai a0, a0, 31
4838 ; RV32ZBA-NEXT: beq a2, a0, .LBB60_2
4839 ; RV32ZBA-NEXT: # %bb.1: # %overflow
4840 ; RV32ZBA-NEXT: li a0, 0
4841 ; RV32ZBA-NEXT: ret
4842 ; RV32ZBA-NEXT: .LBB60_2: # %continue
4843 ; RV32ZBA-NEXT: li a0, 1
4844 ; RV32ZBA-NEXT: ret
4845 ;
4846 ; RV64ZBA-LABEL: smulo.br.i32:
4847 ; RV64ZBA: # %bb.0: # %entry
4848 ; RV64ZBA-NEXT: mul a2, a0, a1
4849 ; RV64ZBA-NEXT: mulw a0, a0, a1
4850 ; RV64ZBA-NEXT: beq a0, a2, .LBB60_2
4851 ; RV64ZBA-NEXT: # %bb.1: # %overflow
4852 ; RV64ZBA-NEXT: li a0, 0
4853 ; RV64ZBA-NEXT: ret
4854 ; RV64ZBA-NEXT: .LBB60_2: # %continue
4855 ; RV64ZBA-NEXT: li a0, 1
4856 ; RV64ZBA-NEXT: ret
4857 ;
4858 ; RV32ZICOND-LABEL: smulo.br.i32:
4859 ; RV32ZICOND: # %bb.0: # %entry
4860 ; RV32ZICOND-NEXT: mulh a2, a0, a1
4861 ; RV32ZICOND-NEXT: mul a0, a0, a1
4862 ; RV32ZICOND-NEXT: srai a0, a0, 31
4863 ; RV32ZICOND-NEXT: beq a2, a0, .LBB60_2
4864 ; RV32ZICOND-NEXT: # %bb.1: # %overflow
4865 ; RV32ZICOND-NEXT: li a0, 0
4866 ; RV32ZICOND-NEXT: ret
4867 ; RV32ZICOND-NEXT: .LBB60_2: # %continue
4868 ; RV32ZICOND-NEXT: li a0, 1
4869 ; RV32ZICOND-NEXT: ret
4870 ;
4871 ; RV64ZICOND-LABEL: smulo.br.i32:
4872 ; RV64ZICOND: # %bb.0: # %entry
4873 ; RV64ZICOND-NEXT: mul a2, a0, a1
4874 ; RV64ZICOND-NEXT: mulw a0, a0, a1
4875 ; RV64ZICOND-NEXT: beq a0, a2, .LBB60_2
4876 ; RV64ZICOND-NEXT: # %bb.1: # %overflow
4877 ; RV64ZICOND-NEXT: li a0, 0
4878 ; RV64ZICOND-NEXT: ret
4879 ; RV64ZICOND-NEXT: .LBB60_2: # %continue
4880 ; RV64ZICOND-NEXT: li a0, 1
4881 ; RV64ZICOND-NEXT: ret
4882 entry:
4883 %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
4884 %val = extractvalue {i32, i1} %t, 0
4885 %obit = extractvalue {i32, i1} %t, 1
4886 br i1 %obit, label %overflow, label %continue
4888 overflow:
4889 ret i1 false
4891 continue:
4892 ret i1 true
4893 }
4895 define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) {
4896 ; RV32-LABEL: smulo.br.i64:
4897 ; RV32: # %bb.0: # %entry
4898 ; RV32-NEXT: addi sp, sp, -16
4899 ; RV32-NEXT: .cfi_def_cfa_offset 16
4900 ; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
4901 ; RV32-NEXT: .cfi_offset s0, -4
4902 ; RV32-NEXT: mulhu a4, a0, a2
4903 ; RV32-NEXT: mul a5, a1, a2
4904 ; RV32-NEXT: add a4, a5, a4
4905 ; RV32-NEXT: sltu a5, a4, a5
4906 ; RV32-NEXT: mulhu a6, a1, a2
4907 ; RV32-NEXT: add a5, a6, a5
4908 ; RV32-NEXT: mul a6, a0, a3
4909 ; RV32-NEXT: add a4, a6, a4
4910 ; RV32-NEXT: sltu a6, a4, a6
4911 ; RV32-NEXT: mulhu a7, a0, a3
4912 ; RV32-NEXT: add a6, a7, a6
4913 ; RV32-NEXT: add a6, a5, a6
4914 ; RV32-NEXT: mul a7, a1, a3
4915 ; RV32-NEXT: add t0, a7, a6
4916 ; RV32-NEXT: srai t1, a1, 31
4917 ; RV32-NEXT: mul t2, a2, t1
4918 ; RV32-NEXT: srai t3, a3, 31
4919 ; RV32-NEXT: mul t4, t3, a0
4920 ; RV32-NEXT: add t5, t4, t2
4921 ; RV32-NEXT: add t6, t0, t5
4922 ; RV32-NEXT: sltu s0, t6, t0
4923 ; RV32-NEXT: sltu a7, t0, a7
4924 ; RV32-NEXT: sltu a5, a6, a5
4925 ; RV32-NEXT: mulhu a6, a1, a3
4926 ; RV32-NEXT: add a5, a6, a5
4927 ; RV32-NEXT: add a5, a5, a7
4928 ; RV32-NEXT: mulhu a2, a2, t1
4929 ; RV32-NEXT: add a2, a2, t2
4930 ; RV32-NEXT: mul a3, a3, t1
4931 ; RV32-NEXT: add a2, a2, a3
4932 ; RV32-NEXT: mul a1, t3, a1
4933 ; RV32-NEXT: mulhu a0, t3, a0
4934 ; RV32-NEXT: add a0, a0, a1
4935 ; RV32-NEXT: add a0, a0, t4
4936 ; RV32-NEXT: add a0, a0, a2
4937 ; RV32-NEXT: sltu a1, t5, t4
4938 ; RV32-NEXT: add a0, a0, a1
4939 ; RV32-NEXT: add a0, a5, a0
4940 ; RV32-NEXT: add a0, a0, s0
4941 ; RV32-NEXT: srai a4, a4, 31
4942 ; RV32-NEXT: xor a0, a0, a4
4943 ; RV32-NEXT: xor a1, t6, a4
4944 ; RV32-NEXT: or a0, a1, a0
4945 ; RV32-NEXT: beqz a0, .LBB61_2
4946 ; RV32-NEXT: # %bb.1: # %overflow
4947 ; RV32-NEXT: li a0, 0
4948 ; RV32-NEXT: j .LBB61_3
4949 ; RV32-NEXT: .LBB61_2: # %continue
4950 ; RV32-NEXT: li a0, 1
4951 ; RV32-NEXT: .LBB61_3: # %overflow
4952 ; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
4953 ; RV32-NEXT: addi sp, sp, 16
4954 ; RV32-NEXT: ret
4955 ;
4956 ; RV64-LABEL: smulo.br.i64:
4957 ; RV64: # %bb.0: # %entry
4958 ; RV64-NEXT: mulh a2, a0, a1
4959 ; RV64-NEXT: mul a0, a0, a1
4960 ; RV64-NEXT: srai a0, a0, 63
4961 ; RV64-NEXT: beq a2, a0, .LBB61_2
4962 ; RV64-NEXT: # %bb.1: # %overflow
4963 ; RV64-NEXT: li a0, 0
4964 ; RV64-NEXT: ret
4965 ; RV64-NEXT: .LBB61_2: # %continue
4966 ; RV64-NEXT: li a0, 1
4967 ; RV64-NEXT: ret
4968 ;
4969 ; RV32ZBA-LABEL: smulo.br.i64:
4970 ; RV32ZBA: # %bb.0: # %entry
4971 ; RV32ZBA-NEXT: addi sp, sp, -16
4972 ; RV32ZBA-NEXT: .cfi_def_cfa_offset 16
4973 ; RV32ZBA-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
4974 ; RV32ZBA-NEXT: .cfi_offset s0, -4
4975 ; RV32ZBA-NEXT: mulhu a4, a0, a2
4976 ; RV32ZBA-NEXT: mul a5, a1, a2
4977 ; RV32ZBA-NEXT: add a4, a5, a4
4978 ; RV32ZBA-NEXT: sltu a5, a4, a5
4979 ; RV32ZBA-NEXT: mulhu a6, a1, a2
4980 ; RV32ZBA-NEXT: add a5, a6, a5
4981 ; RV32ZBA-NEXT: mul a6, a0, a3
4982 ; RV32ZBA-NEXT: add a4, a6, a4
4983 ; RV32ZBA-NEXT: sltu a6, a4, a6
4984 ; RV32ZBA-NEXT: mulhu a7, a0, a3
4985 ; RV32ZBA-NEXT: add a6, a7, a6
4986 ; RV32ZBA-NEXT: add a6, a5, a6
4987 ; RV32ZBA-NEXT: mul a7, a1, a3
4988 ; RV32ZBA-NEXT: add t0, a7, a6
4989 ; RV32ZBA-NEXT: srai t1, a1, 31
4990 ; RV32ZBA-NEXT: mul t2, a2, t1
4991 ; RV32ZBA-NEXT: srai t3, a3, 31
4992 ; RV32ZBA-NEXT: mul t4, t3, a0
4993 ; RV32ZBA-NEXT: add t5, t4, t2
4994 ; RV32ZBA-NEXT: add t6, t0, t5
4995 ; RV32ZBA-NEXT: sltu s0, t6, t0
4996 ; RV32ZBA-NEXT: sltu a7, t0, a7
4997 ; RV32ZBA-NEXT: sltu a5, a6, a5
4998 ; RV32ZBA-NEXT: mulhu a6, a1, a3
4999 ; RV32ZBA-NEXT: add a5, a6, a5
5000 ; RV32ZBA-NEXT: add a5, a5, a7
5001 ; RV32ZBA-NEXT: mulhu a2, a2, t1
5002 ; RV32ZBA-NEXT: add a2, a2, t2
5003 ; RV32ZBA-NEXT: mul a3, a3, t1
5004 ; RV32ZBA-NEXT: add a2, a2, a3
5005 ; RV32ZBA-NEXT: mul a1, t3, a1
5006 ; RV32ZBA-NEXT: mulhu a0, t3, a0
5007 ; RV32ZBA-NEXT: add a0, a0, a1
5008 ; RV32ZBA-NEXT: add a0, a0, t4
5009 ; RV32ZBA-NEXT: add a0, a0, a2
5010 ; RV32ZBA-NEXT: sltu a1, t5, t4
5011 ; RV32ZBA-NEXT: add a0, a0, a1
5012 ; RV32ZBA-NEXT: add a0, a5, a0
5013 ; RV32ZBA-NEXT: add a0, a0, s0
5014 ; RV32ZBA-NEXT: srai a4, a4, 31
5015 ; RV32ZBA-NEXT: xor a0, a0, a4
5016 ; RV32ZBA-NEXT: xor a1, t6, a4
5017 ; RV32ZBA-NEXT: or a0, a1, a0
5018 ; RV32ZBA-NEXT: beqz a0, .LBB61_2
5019 ; RV32ZBA-NEXT: # %bb.1: # %overflow
5020 ; RV32ZBA-NEXT: li a0, 0
5021 ; RV32ZBA-NEXT: j .LBB61_3
5022 ; RV32ZBA-NEXT: .LBB61_2: # %continue
5023 ; RV32ZBA-NEXT: li a0, 1
5024 ; RV32ZBA-NEXT: .LBB61_3: # %overflow
5025 ; RV32ZBA-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
5026 ; RV32ZBA-NEXT: addi sp, sp, 16
5027 ; RV32ZBA-NEXT: ret
5028 ;
5029 ; RV64ZBA-LABEL: smulo.br.i64:
5030 ; RV64ZBA: # %bb.0: # %entry
5031 ; RV64ZBA-NEXT: mulh a2, a0, a1
5032 ; RV64ZBA-NEXT: mul a0, a0, a1
5033 ; RV64ZBA-NEXT: srai a0, a0, 63
5034 ; RV64ZBA-NEXT: beq a2, a0, .LBB61_2
5035 ; RV64ZBA-NEXT: # %bb.1: # %overflow
5036 ; RV64ZBA-NEXT: li a0, 0
5037 ; RV64ZBA-NEXT: ret
5038 ; RV64ZBA-NEXT: .LBB61_2: # %continue
5039 ; RV64ZBA-NEXT: li a0, 1
5040 ; RV64ZBA-NEXT: ret
5041 ;
5042 ; RV32ZICOND-LABEL: smulo.br.i64:
5043 ; RV32ZICOND: # %bb.0: # %entry
5044 ; RV32ZICOND-NEXT: addi sp, sp, -16
5045 ; RV32ZICOND-NEXT: .cfi_def_cfa_offset 16
5046 ; RV32ZICOND-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
5047 ; RV32ZICOND-NEXT: .cfi_offset s0, -4
5048 ; RV32ZICOND-NEXT: mulhu a4, a0, a2
5049 ; RV32ZICOND-NEXT: mul a5, a1, a2
5050 ; RV32ZICOND-NEXT: add a4, a5, a4
5051 ; RV32ZICOND-NEXT: sltu a5, a4, a5
5052 ; RV32ZICOND-NEXT: mulhu a6, a1, a2
5053 ; RV32ZICOND-NEXT: add a5, a6, a5
5054 ; RV32ZICOND-NEXT: mul a6, a0, a3
5055 ; RV32ZICOND-NEXT: add a4, a6, a4
5056 ; RV32ZICOND-NEXT: sltu a6, a4, a6
5057 ; RV32ZICOND-NEXT: mulhu a7, a0, a3
5058 ; RV32ZICOND-NEXT: add a6, a7, a6
5059 ; RV32ZICOND-NEXT: add a6, a5, a6
5060 ; RV32ZICOND-NEXT: mul a7, a1, a3
5061 ; RV32ZICOND-NEXT: add t0, a7, a6
5062 ; RV32ZICOND-NEXT: srai t1, a1, 31
5063 ; RV32ZICOND-NEXT: mul t2, a2, t1
5064 ; RV32ZICOND-NEXT: srai t3, a3, 31
5065 ; RV32ZICOND-NEXT: mul t4, t3, a0
5066 ; RV32ZICOND-NEXT: add t5, t4, t2
5067 ; RV32ZICOND-NEXT: add t6, t0, t5
5068 ; RV32ZICOND-NEXT: sltu s0, t6, t0
5069 ; RV32ZICOND-NEXT: sltu a7, t0, a7
5070 ; RV32ZICOND-NEXT: sltu a5, a6, a5
5071 ; RV32ZICOND-NEXT: mulhu a6, a1, a3
5072 ; RV32ZICOND-NEXT: add a5, a6, a5
5073 ; RV32ZICOND-NEXT: add a5, a5, a7
5074 ; RV32ZICOND-NEXT: mulhu a2, a2, t1
5075 ; RV32ZICOND-NEXT: add a2, a2, t2
5076 ; RV32ZICOND-NEXT: mul a3, a3, t1
5077 ; RV32ZICOND-NEXT: add a2, a2, a3
5078 ; RV32ZICOND-NEXT: mul a1, t3, a1
5079 ; RV32ZICOND-NEXT: mulhu a0, t3, a0
5080 ; RV32ZICOND-NEXT: add a0, a0, a1
5081 ; RV32ZICOND-NEXT: add a0, a0, t4
5082 ; RV32ZICOND-NEXT: add a0, a0, a2
5083 ; RV32ZICOND-NEXT: sltu a1, t5, t4
5084 ; RV32ZICOND-NEXT: add a0, a0, a1
5085 ; RV32ZICOND-NEXT: add a0, a5, a0
5086 ; RV32ZICOND-NEXT: add a0, a0, s0
5087 ; RV32ZICOND-NEXT: srai a4, a4, 31
5088 ; RV32ZICOND-NEXT: xor a0, a0, a4
5089 ; RV32ZICOND-NEXT: xor a1, t6, a4
5090 ; RV32ZICOND-NEXT: or a0, a1, a0
5091 ; RV32ZICOND-NEXT: beqz a0, .LBB61_2
5092 ; RV32ZICOND-NEXT: # %bb.1: # %overflow
5093 ; RV32ZICOND-NEXT: li a0, 0
5094 ; RV32ZICOND-NEXT: j .LBB61_3
5095 ; RV32ZICOND-NEXT: .LBB61_2: # %continue
5096 ; RV32ZICOND-NEXT: li a0, 1
5097 ; RV32ZICOND-NEXT: .LBB61_3: # %overflow
5098 ; RV32ZICOND-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
5099 ; RV32ZICOND-NEXT: addi sp, sp, 16
5100 ; RV32ZICOND-NEXT: ret
5101 ;
5102 ; RV64ZICOND-LABEL: smulo.br.i64:
5103 ; RV64ZICOND: # %bb.0: # %entry
5104 ; RV64ZICOND-NEXT: mulh a2, a0, a1
5105 ; RV64ZICOND-NEXT: mul a0, a0, a1
5106 ; RV64ZICOND-NEXT: srai a0, a0, 63
5107 ; RV64ZICOND-NEXT: beq a2, a0, .LBB61_2
5108 ; RV64ZICOND-NEXT: # %bb.1: # %overflow
5109 ; RV64ZICOND-NEXT: li a0, 0
5110 ; RV64ZICOND-NEXT: ret
5111 ; RV64ZICOND-NEXT: .LBB61_2: # %continue
5112 ; RV64ZICOND-NEXT: li a0, 1
5113 ; RV64ZICOND-NEXT: ret
5114 entry:
5115 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
5116 %val = extractvalue {i64, i1} %t, 0
5117 %obit = extractvalue {i64, i1} %t, 1
5118 br i1 %obit, label %overflow, label %continue
5120 overflow:
5121 ret i1 false
5123 continue:
5124 ret i1 true
5125 }
5127 define zeroext i1 @smulo2.br.i64(i64 %v1) {
5128 ; RV32-LABEL: smulo2.br.i64:
5129 ; RV32: # %bb.0: # %entry
5130 ; RV32-NEXT: li a2, -13
5131 ; RV32-NEXT: mulhu a3, a0, a2
5132 ; RV32-NEXT: mul a4, a1, a2
5133 ; RV32-NEXT: add a3, a4, a3
5134 ; RV32-NEXT: sltu a4, a3, a4
5135 ; RV32-NEXT: mulhu a5, a1, a2
5136 ; RV32-NEXT: add a4, a5, a4
5137 ; RV32-NEXT: sub a3, a3, a0
5138 ; RV32-NEXT: neg a5, a0
5139 ; RV32-NEXT: sltu a6, a3, a5
5140 ; RV32-NEXT: li a7, -1
5141 ; RV32-NEXT: mulhu t0, a0, a7
5142 ; RV32-NEXT: add a6, t0, a6
5143 ; RV32-NEXT: add a6, a4, a6
5144 ; RV32-NEXT: sub t1, a6, a1
5145 ; RV32-NEXT: srai t2, a1, 31
5146 ; RV32-NEXT: mul t3, t2, a2
5147 ; RV32-NEXT: sub t3, t3, a0
5148 ; RV32-NEXT: add t4, t1, t3
5149 ; RV32-NEXT: sltu t5, t4, t1
5150 ; RV32-NEXT: neg t6, a1
5151 ; RV32-NEXT: sltu t1, t1, t6
5152 ; RV32-NEXT: sltu a4, a6, a4
5153 ; RV32-NEXT: mulhu a6, a1, a7
5154 ; RV32-NEXT: add a4, a6, a4
5155 ; RV32-NEXT: add a4, a4, t1
5156 ; RV32-NEXT: sltu a5, t3, a5
5157 ; RV32-NEXT: mulh a2, t2, a2
5158 ; RV32-NEXT: add a0, a0, a1
5159 ; RV32-NEXT: sub a0, t0, a0
5160 ; RV32-NEXT: add a0, a0, a2
5161 ; RV32-NEXT: add a0, a0, a5
5162 ; RV32-NEXT: add a0, a4, a0
5163 ; RV32-NEXT: add a0, a0, t5
5164 ; RV32-NEXT: srai a3, a3, 31
5165 ; RV32-NEXT: xor a0, a0, a3
5166 ; RV32-NEXT: xor a1, t4, a3
5167 ; RV32-NEXT: or a0, a1, a0
5168 ; RV32-NEXT: beqz a0, .LBB62_2
5169 ; RV32-NEXT: # %bb.1: # %overflow
5170 ; RV32-NEXT: li a0, 0
5171 ; RV32-NEXT: ret
5172 ; RV32-NEXT: .LBB62_2: # %continue
5173 ; RV32-NEXT: li a0, 1
5174 ; RV32-NEXT: ret
5175 ;
5176 ; RV64-LABEL: smulo2.br.i64:
5177 ; RV64: # %bb.0: # %entry
5178 ; RV64-NEXT: li a1, -13
5179 ; RV64-NEXT: mulh a2, a0, a1
5180 ; RV64-NEXT: mul a0, a0, a1
5181 ; RV64-NEXT: srai a0, a0, 63
5182 ; RV64-NEXT: beq a2, a0, .LBB62_2
5183 ; RV64-NEXT: # %bb.1: # %overflow
5184 ; RV64-NEXT: li a0, 0
5185 ; RV64-NEXT: ret
5186 ; RV64-NEXT: .LBB62_2: # %continue
5187 ; RV64-NEXT: li a0, 1
5188 ; RV64-NEXT: ret
5189 ;
5190 ; RV32ZBA-LABEL: smulo2.br.i64:
5191 ; RV32ZBA: # %bb.0: # %entry
5192 ; RV32ZBA-NEXT: li a2, -13
5193 ; RV32ZBA-NEXT: mulhu a3, a0, a2
5194 ; RV32ZBA-NEXT: mul a4, a1, a2
5195 ; RV32ZBA-NEXT: add a3, a4, a3
5196 ; RV32ZBA-NEXT: sltu a4, a3, a4
5197 ; RV32ZBA-NEXT: mulhu a5, a1, a2
5198 ; RV32ZBA-NEXT: add a4, a5, a4
5199 ; RV32ZBA-NEXT: sub a3, a3, a0
5200 ; RV32ZBA-NEXT: neg a5, a0
5201 ; RV32ZBA-NEXT: sltu a6, a3, a5
5202 ; RV32ZBA-NEXT: li a7, -1
5203 ; RV32ZBA-NEXT: mulhu t0, a0, a7
5204 ; RV32ZBA-NEXT: add a6, t0, a6
5205 ; RV32ZBA-NEXT: add a6, a4, a6
5206 ; RV32ZBA-NEXT: sub t1, a6, a1
5207 ; RV32ZBA-NEXT: srai t2, a1, 31
5208 ; RV32ZBA-NEXT: mul t3, t2, a2
5209 ; RV32ZBA-NEXT: sub t3, t3, a0
5210 ; RV32ZBA-NEXT: add t4, t1, t3
5211 ; RV32ZBA-NEXT: sltu t5, t4, t1
5212 ; RV32ZBA-NEXT: neg t6, a1
5213 ; RV32ZBA-NEXT: sltu t1, t1, t6
5214 ; RV32ZBA-NEXT: sltu a4, a6, a4
5215 ; RV32ZBA-NEXT: mulhu a6, a1, a7
5216 ; RV32ZBA-NEXT: add a4, a6, a4
5217 ; RV32ZBA-NEXT: add a4, a4, t1
5218 ; RV32ZBA-NEXT: sltu a5, t3, a5
5219 ; RV32ZBA-NEXT: mulh a2, t2, a2
5220 ; RV32ZBA-NEXT: add a0, a0, a1
5221 ; RV32ZBA-NEXT: sub a0, t0, a0
5222 ; RV32ZBA-NEXT: add a0, a0, a2
5223 ; RV32ZBA-NEXT: add a0, a0, a5
5224 ; RV32ZBA-NEXT: add a0, a4, a0
5225 ; RV32ZBA-NEXT: add a0, a0, t5
5226 ; RV32ZBA-NEXT: srai a3, a3, 31
5227 ; RV32ZBA-NEXT: xor a0, a0, a3
5228 ; RV32ZBA-NEXT: xor a1, t4, a3
5229 ; RV32ZBA-NEXT: or a0, a1, a0
5230 ; RV32ZBA-NEXT: beqz a0, .LBB62_2
5231 ; RV32ZBA-NEXT: # %bb.1: # %overflow
5232 ; RV32ZBA-NEXT: li a0, 0
5233 ; RV32ZBA-NEXT: ret
5234 ; RV32ZBA-NEXT: .LBB62_2: # %continue
5235 ; RV32ZBA-NEXT: li a0, 1
5236 ; RV32ZBA-NEXT: ret
5237 ;
5238 ; RV64ZBA-LABEL: smulo2.br.i64:
5239 ; RV64ZBA: # %bb.0: # %entry
5240 ; RV64ZBA-NEXT: li a1, -13
5241 ; RV64ZBA-NEXT: mulh a2, a0, a1
5242 ; RV64ZBA-NEXT: mul a0, a0, a1
5243 ; RV64ZBA-NEXT: srai a0, a0, 63
5244 ; RV64ZBA-NEXT: beq a2, a0, .LBB62_2
5245 ; RV64ZBA-NEXT: # %bb.1: # %overflow
5246 ; RV64ZBA-NEXT: li a0, 0
5247 ; RV64ZBA-NEXT: ret
5248 ; RV64ZBA-NEXT: .LBB62_2: # %continue
5249 ; RV64ZBA-NEXT: li a0, 1
5250 ; RV64ZBA-NEXT: ret
5251 ;
5252 ; RV32ZICOND-LABEL: smulo2.br.i64:
5253 ; RV32ZICOND: # %bb.0: # %entry
5254 ; RV32ZICOND-NEXT: li a2, -13
5255 ; RV32ZICOND-NEXT: mulhu a3, a0, a2
5256 ; RV32ZICOND-NEXT: mul a4, a1, a2
5257 ; RV32ZICOND-NEXT: add a3, a4, a3
5258 ; RV32ZICOND-NEXT: sltu a4, a3, a4
5259 ; RV32ZICOND-NEXT: mulhu a5, a1, a2
5260 ; RV32ZICOND-NEXT: add a4, a5, a4
5261 ; RV32ZICOND-NEXT: sub a3, a3, a0
5262 ; RV32ZICOND-NEXT: neg a5, a0
5263 ; RV32ZICOND-NEXT: sltu a6, a3, a5
5264 ; RV32ZICOND-NEXT: li a7, -1
5265 ; RV32ZICOND-NEXT: mulhu t0, a0, a7
5266 ; RV32ZICOND-NEXT: add a6, t0, a6
5267 ; RV32ZICOND-NEXT: add a6, a4, a6
5268 ; RV32ZICOND-NEXT: sub t1, a6, a1
5269 ; RV32ZICOND-NEXT: srai t2, a1, 31
5270 ; RV32ZICOND-NEXT: mul t3, t2, a2
5271 ; RV32ZICOND-NEXT: sub t3, t3, a0
5272 ; RV32ZICOND-NEXT: add t4, t1, t3
5273 ; RV32ZICOND-NEXT: sltu t5, t4, t1
5274 ; RV32ZICOND-NEXT: neg t6, a1
5275 ; RV32ZICOND-NEXT: sltu t1, t1, t6
5276 ; RV32ZICOND-NEXT: sltu a4, a6, a4
5277 ; RV32ZICOND-NEXT: mulhu a6, a1, a7
5278 ; RV32ZICOND-NEXT: add a4, a6, a4
5279 ; RV32ZICOND-NEXT: add a4, a4, t1
5280 ; RV32ZICOND-NEXT: sltu a5, t3, a5
5281 ; RV32ZICOND-NEXT: mulh a2, t2, a2
5282 ; RV32ZICOND-NEXT: add a0, a0, a1
5283 ; RV32ZICOND-NEXT: sub a0, t0, a0
5284 ; RV32ZICOND-NEXT: add a0, a0, a2
5285 ; RV32ZICOND-NEXT: add a0, a0, a5
5286 ; RV32ZICOND-NEXT: add a0, a4, a0
5287 ; RV32ZICOND-NEXT: add a0, a0, t5
5288 ; RV32ZICOND-NEXT: srai a3, a3, 31
5289 ; RV32ZICOND-NEXT: xor a0, a0, a3
5290 ; RV32ZICOND-NEXT: xor a1, t4, a3
5291 ; RV32ZICOND-NEXT: or a0, a1, a0
5292 ; RV32ZICOND-NEXT: beqz a0, .LBB62_2
5293 ; RV32ZICOND-NEXT: # %bb.1: # %overflow
5294 ; RV32ZICOND-NEXT: li a0, 0
5295 ; RV32ZICOND-NEXT: ret
5296 ; RV32ZICOND-NEXT: .LBB62_2: # %continue
5297 ; RV32ZICOND-NEXT: li a0, 1
5298 ; RV32ZICOND-NEXT: ret
5299 ;
5300 ; RV64ZICOND-LABEL: smulo2.br.i64:
5301 ; RV64ZICOND: # %bb.0: # %entry
5302 ; RV64ZICOND-NEXT: li a1, -13
5303 ; RV64ZICOND-NEXT: mulh a2, a0, a1
5304 ; RV64ZICOND-NEXT: mul a0, a0, a1
5305 ; RV64ZICOND-NEXT: srai a0, a0, 63
5306 ; RV64ZICOND-NEXT: beq a2, a0, .LBB62_2
5307 ; RV64ZICOND-NEXT: # %bb.1: # %overflow
5308 ; RV64ZICOND-NEXT: li a0, 0
5309 ; RV64ZICOND-NEXT: ret
5310 ; RV64ZICOND-NEXT: .LBB62_2: # %continue
5311 ; RV64ZICOND-NEXT: li a0, 1
5312 ; RV64ZICOND-NEXT: ret
5313 entry:
5314 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 -13)
5315 %val = extractvalue {i64, i1} %t, 0
5316 %obit = extractvalue {i64, i1} %t, 1
5317 br i1 %obit, label %overflow, label %continue
5319 overflow:
5320 ret i1 false
5322 continue:
5323 ret i1 true
5324 }
5326 define zeroext i1 @umulo.br.i32(i32 signext %v1, i32 signext %v2) {
5327 ; RV32-LABEL: umulo.br.i32:
5328 ; RV32: # %bb.0: # %entry
5329 ; RV32-NEXT: mulhu a0, a0, a1
5330 ; RV32-NEXT: beqz a0, .LBB63_2
5331 ; RV32-NEXT: # %bb.1: # %overflow
5332 ; RV32-NEXT: li a0, 0
5333 ; RV32-NEXT: ret
5334 ; RV32-NEXT: .LBB63_2: # %continue
5335 ; RV32-NEXT: li a0, 1
5336 ; RV32-NEXT: ret
5337 ;
5338 ; RV64-LABEL: umulo.br.i32:
5339 ; RV64: # %bb.0: # %entry
5340 ; RV64-NEXT: slli a1, a1, 32
5341 ; RV64-NEXT: slli a0, a0, 32
5342 ; RV64-NEXT: mulhu a0, a0, a1
5343 ; RV64-NEXT: srli a0, a0, 32
5344 ; RV64-NEXT: beqz a0, .LBB63_2
5345 ; RV64-NEXT: # %bb.1: # %overflow
5346 ; RV64-NEXT: li a0, 0
5347 ; RV64-NEXT: ret
5348 ; RV64-NEXT: .LBB63_2: # %continue
5349 ; RV64-NEXT: li a0, 1
5350 ; RV64-NEXT: ret
5351 ;
5352 ; RV32ZBA-LABEL: umulo.br.i32:
5353 ; RV32ZBA: # %bb.0: # %entry
5354 ; RV32ZBA-NEXT: mulhu a0, a0, a1
5355 ; RV32ZBA-NEXT: beqz a0, .LBB63_2
5356 ; RV32ZBA-NEXT: # %bb.1: # %overflow
5357 ; RV32ZBA-NEXT: li a0, 0
5358 ; RV32ZBA-NEXT: ret
5359 ; RV32ZBA-NEXT: .LBB63_2: # %continue
5360 ; RV32ZBA-NEXT: li a0, 1
5361 ; RV32ZBA-NEXT: ret
5362 ;
5363 ; RV64ZBA-LABEL: umulo.br.i32:
5364 ; RV64ZBA: # %bb.0: # %entry
5365 ; RV64ZBA-NEXT: zext.w a1, a1
5366 ; RV64ZBA-NEXT: zext.w a0, a0
5367 ; RV64ZBA-NEXT: mul a0, a0, a1
5368 ; RV64ZBA-NEXT: srli a0, a0, 32
5369 ; RV64ZBA-NEXT: beqz a0, .LBB63_2
5370 ; RV64ZBA-NEXT: # %bb.1: # %overflow
5371 ; RV64ZBA-NEXT: li a0, 0
5372 ; RV64ZBA-NEXT: ret
5373 ; RV64ZBA-NEXT: .LBB63_2: # %continue
5374 ; RV64ZBA-NEXT: li a0, 1
5375 ; RV64ZBA-NEXT: ret
5376 ;
5377 ; RV32ZICOND-LABEL: umulo.br.i32:
5378 ; RV32ZICOND: # %bb.0: # %entry
5379 ; RV32ZICOND-NEXT: mulhu a0, a0, a1
5380 ; RV32ZICOND-NEXT: beqz a0, .LBB63_2
5381 ; RV32ZICOND-NEXT: # %bb.1: # %overflow
5382 ; RV32ZICOND-NEXT: li a0, 0
5383 ; RV32ZICOND-NEXT: ret
5384 ; RV32ZICOND-NEXT: .LBB63_2: # %continue
5385 ; RV32ZICOND-NEXT: li a0, 1
5386 ; RV32ZICOND-NEXT: ret
5387 ;
5388 ; RV64ZICOND-LABEL: umulo.br.i32:
5389 ; RV64ZICOND: # %bb.0: # %entry
5390 ; RV64ZICOND-NEXT: slli a1, a1, 32
5391 ; RV64ZICOND-NEXT: slli a0, a0, 32
5392 ; RV64ZICOND-NEXT: mulhu a0, a0, a1
5393 ; RV64ZICOND-NEXT: srli a0, a0, 32
5394 ; RV64ZICOND-NEXT: beqz a0, .LBB63_2
5395 ; RV64ZICOND-NEXT: # %bb.1: # %overflow
5396 ; RV64ZICOND-NEXT: li a0, 0
5397 ; RV64ZICOND-NEXT: ret
5398 ; RV64ZICOND-NEXT: .LBB63_2: # %continue
5399 ; RV64ZICOND-NEXT: li a0, 1
5400 ; RV64ZICOND-NEXT: ret
5401 entry:
5402 %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
5403 %val = extractvalue {i32, i1} %t, 0
5404 %obit = extractvalue {i32, i1} %t, 1
5405 br i1 %obit, label %overflow, label %continue
5407 overflow:
5408 ret i1 false
5410 continue:
5411 ret i1 true
5412 }
5414 define zeroext i1 @umulo.br.i64(i64 %v1, i64 %v2) {
5415 ; RV32-LABEL: umulo.br.i64:
5416 ; RV32: # %bb.0: # %entry
5417 ; RV32-NEXT: mul a4, a3, a0
5418 ; RV32-NEXT: mul a5, a1, a2
5419 ; RV32-NEXT: add a4, a5, a4
5420 ; RV32-NEXT: mulhu a5, a0, a2
5421 ; RV32-NEXT: add a4, a5, a4
5422 ; RV32-NEXT: sltu a4, a4, a5
5423 ; RV32-NEXT: snez a5, a3
5424 ; RV32-NEXT: snez a6, a1
5425 ; RV32-NEXT: and a5, a6, a5
5426 ; RV32-NEXT: mulhu a1, a1, a2
5427 ; RV32-NEXT: snez a1, a1
5428 ; RV32-NEXT: or a1, a5, a1
5429 ; RV32-NEXT: mulhu a0, a3, a0
5430 ; RV32-NEXT: snez a0, a0
5431 ; RV32-NEXT: or a0, a1, a0
5432 ; RV32-NEXT: or a0, a0, a4
5433 ; RV32-NEXT: beqz a0, .LBB64_2
5434 ; RV32-NEXT: # %bb.1: # %overflow
5435 ; RV32-NEXT: li a0, 0
5436 ; RV32-NEXT: ret
5437 ; RV32-NEXT: .LBB64_2: # %continue
5438 ; RV32-NEXT: li a0, 1
5439 ; RV32-NEXT: ret
5440 ;
5441 ; RV64-LABEL: umulo.br.i64:
5442 ; RV64: # %bb.0: # %entry
5443 ; RV64-NEXT: mulhu a0, a0, a1
5444 ; RV64-NEXT: beqz a0, .LBB64_2
5445 ; RV64-NEXT: # %bb.1: # %overflow
5446 ; RV64-NEXT: li a0, 0
5447 ; RV64-NEXT: ret
5448 ; RV64-NEXT: .LBB64_2: # %continue
5449 ; RV64-NEXT: li a0, 1
5450 ; RV64-NEXT: ret
5451 ;
5452 ; RV32ZBA-LABEL: umulo.br.i64:
5453 ; RV32ZBA: # %bb.0: # %entry
5454 ; RV32ZBA-NEXT: mul a4, a3, a0
5455 ; RV32ZBA-NEXT: mul a5, a1, a2
5456 ; RV32ZBA-NEXT: add a4, a5, a4
5457 ; RV32ZBA-NEXT: mulhu a5, a0, a2
5458 ; RV32ZBA-NEXT: add a4, a5, a4
5459 ; RV32ZBA-NEXT: sltu a4, a4, a5
5460 ; RV32ZBA-NEXT: snez a5, a3
5461 ; RV32ZBA-NEXT: snez a6, a1
5462 ; RV32ZBA-NEXT: and a5, a6, a5
5463 ; RV32ZBA-NEXT: mulhu a1, a1, a2
5464 ; RV32ZBA-NEXT: snez a1, a1
5465 ; RV32ZBA-NEXT: or a1, a5, a1
5466 ; RV32ZBA-NEXT: mulhu a0, a3, a0
5467 ; RV32ZBA-NEXT: snez a0, a0
5468 ; RV32ZBA-NEXT: or a0, a1, a0
5469 ; RV32ZBA-NEXT: or a0, a0, a4
5470 ; RV32ZBA-NEXT: beqz a0, .LBB64_2
5471 ; RV32ZBA-NEXT: # %bb.1: # %overflow
5472 ; RV32ZBA-NEXT: li a0, 0
5473 ; RV32ZBA-NEXT: ret
5474 ; RV32ZBA-NEXT: .LBB64_2: # %continue
5475 ; RV32ZBA-NEXT: li a0, 1
5476 ; RV32ZBA-NEXT: ret
5477 ;
5478 ; RV64ZBA-LABEL: umulo.br.i64:
5479 ; RV64ZBA: # %bb.0: # %entry
5480 ; RV64ZBA-NEXT: mulhu a0, a0, a1
5481 ; RV64ZBA-NEXT: beqz a0, .LBB64_2
5482 ; RV64ZBA-NEXT: # %bb.1: # %overflow
5483 ; RV64ZBA-NEXT: li a0, 0
5484 ; RV64ZBA-NEXT: ret
5485 ; RV64ZBA-NEXT: .LBB64_2: # %continue
5486 ; RV64ZBA-NEXT: li a0, 1
5487 ; RV64ZBA-NEXT: ret
5488 ;
5489 ; RV32ZICOND-LABEL: umulo.br.i64:
5490 ; RV32ZICOND: # %bb.0: # %entry
5491 ; RV32ZICOND-NEXT: mul a4, a3, a0
5492 ; RV32ZICOND-NEXT: mul a5, a1, a2
5493 ; RV32ZICOND-NEXT: add a4, a5, a4
5494 ; RV32ZICOND-NEXT: mulhu a5, a0, a2
5495 ; RV32ZICOND-NEXT: add a4, a5, a4
5496 ; RV32ZICOND-NEXT: sltu a4, a4, a5
5497 ; RV32ZICOND-NEXT: snez a5, a3
5498 ; RV32ZICOND-NEXT: snez a6, a1
5499 ; RV32ZICOND-NEXT: and a5, a6, a5
5500 ; RV32ZICOND-NEXT: mulhu a1, a1, a2
5501 ; RV32ZICOND-NEXT: snez a1, a1
5502 ; RV32ZICOND-NEXT: or a1, a5, a1
5503 ; RV32ZICOND-NEXT: mulhu a0, a3, a0
5504 ; RV32ZICOND-NEXT: snez a0, a0
5505 ; RV32ZICOND-NEXT: or a0, a1, a0
5506 ; RV32ZICOND-NEXT: or a0, a0, a4
5507 ; RV32ZICOND-NEXT: beqz a0, .LBB64_2
5508 ; RV32ZICOND-NEXT: # %bb.1: # %overflow
5509 ; RV32ZICOND-NEXT: li a0, 0
5510 ; RV32ZICOND-NEXT: ret
5511 ; RV32ZICOND-NEXT: .LBB64_2: # %continue
5512 ; RV32ZICOND-NEXT: li a0, 1
5513 ; RV32ZICOND-NEXT: ret
5514 ;
5515 ; RV64ZICOND-LABEL: umulo.br.i64:
5516 ; RV64ZICOND: # %bb.0: # %entry
5517 ; RV64ZICOND-NEXT: mulhu a0, a0, a1
5518 ; RV64ZICOND-NEXT: beqz a0, .LBB64_2
5519 ; RV64ZICOND-NEXT: # %bb.1: # %overflow
5520 ; RV64ZICOND-NEXT: li a0, 0
5521 ; RV64ZICOND-NEXT: ret
5522 ; RV64ZICOND-NEXT: .LBB64_2: # %continue
5523 ; RV64ZICOND-NEXT: li a0, 1
5524 ; RV64ZICOND-NEXT: ret
5525 entry:
5526 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
5527 %val = extractvalue {i64, i1} %t, 0
5528 %obit = extractvalue {i64, i1} %t, 1
5529 br i1 %obit, label %overflow, label %continue
5531 overflow:
5532 ret i1 false
5534 continue:
5535 ret i1 true
5536 }
5538 define zeroext i1 @umulo2.br.i64(i64 %v1) {
5539 ; RV32-LABEL: umulo2.br.i64:
5540 ; RV32: # %bb.0: # %entry
5541 ; RV32-NEXT: add a2, a0, a0
5542 ; RV32-NEXT: sltu a0, a2, a0
5543 ; RV32-NEXT: add a2, a1, a1
5544 ; RV32-NEXT: add a2, a2, a0
5545 ; RV32-NEXT: beq a2, a1, .LBB65_2
5546 ; RV32-NEXT: # %bb.1: # %entry
5547 ; RV32-NEXT: sltu a0, a2, a1
5548 ; RV32-NEXT: .LBB65_2: # %entry
5549 ; RV32-NEXT: beqz a0, .LBB65_4
5550 ; RV32-NEXT: # %bb.3: # %overflow
5551 ; RV32-NEXT: li a0, 0
5552 ; RV32-NEXT: ret
5553 ; RV32-NEXT: .LBB65_4: # %continue
5554 ; RV32-NEXT: li a0, 1
5555 ; RV32-NEXT: ret
5556 ;
5557 ; RV64-LABEL: umulo2.br.i64:
5558 ; RV64: # %bb.0: # %entry
5559 ; RV64-NEXT: add a1, a0, a0
5560 ; RV64-NEXT: bgeu a1, a0, .LBB65_2
5561 ; RV64-NEXT: # %bb.1: # %overflow
5562 ; RV64-NEXT: li a0, 0
5563 ; RV64-NEXT: ret
5564 ; RV64-NEXT: .LBB65_2: # %continue
5565 ; RV64-NEXT: li a0, 1
5566 ; RV64-NEXT: ret
5567 ;
5568 ; RV32ZBA-LABEL: umulo2.br.i64:
5569 ; RV32ZBA: # %bb.0: # %entry
5570 ; RV32ZBA-NEXT: add a2, a0, a0
5571 ; RV32ZBA-NEXT: sltu a0, a2, a0
5572 ; RV32ZBA-NEXT: add a2, a1, a1
5573 ; RV32ZBA-NEXT: add a2, a2, a0
5574 ; RV32ZBA-NEXT: beq a2, a1, .LBB65_2
5575 ; RV32ZBA-NEXT: # %bb.1: # %entry
5576 ; RV32ZBA-NEXT: sltu a0, a2, a1
5577 ; RV32ZBA-NEXT: .LBB65_2: # %entry
5578 ; RV32ZBA-NEXT: beqz a0, .LBB65_4
5579 ; RV32ZBA-NEXT: # %bb.3: # %overflow
5580 ; RV32ZBA-NEXT: li a0, 0
5581 ; RV32ZBA-NEXT: ret
5582 ; RV32ZBA-NEXT: .LBB65_4: # %continue
5583 ; RV32ZBA-NEXT: li a0, 1
5584 ; RV32ZBA-NEXT: ret
5585 ;
5586 ; RV64ZBA-LABEL: umulo2.br.i64:
5587 ; RV64ZBA: # %bb.0: # %entry
5588 ; RV64ZBA-NEXT: add a1, a0, a0
5589 ; RV64ZBA-NEXT: bgeu a1, a0, .LBB65_2
5590 ; RV64ZBA-NEXT: # %bb.1: # %overflow
5591 ; RV64ZBA-NEXT: li a0, 0
5592 ; RV64ZBA-NEXT: ret
5593 ; RV64ZBA-NEXT: .LBB65_2: # %continue
5594 ; RV64ZBA-NEXT: li a0, 1
5595 ; RV64ZBA-NEXT: ret
5596 ;
5597 ; RV32ZICOND-LABEL: umulo2.br.i64:
5598 ; RV32ZICOND: # %bb.0: # %entry
5599 ; RV32ZICOND-NEXT: add a2, a0, a0
5600 ; RV32ZICOND-NEXT: sltu a0, a2, a0
5601 ; RV32ZICOND-NEXT: add a2, a1, a1
5602 ; RV32ZICOND-NEXT: add a2, a2, a0
5603 ; RV32ZICOND-NEXT: xor a3, a2, a1
5604 ; RV32ZICOND-NEXT: sltu a1, a2, a1
5605 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a3
5606 ; RV32ZICOND-NEXT: czero.nez a0, a0, a3
5607 ; RV32ZICOND-NEXT: or a0, a0, a1
5608 ; RV32ZICOND-NEXT: beqz a0, .LBB65_2
5609 ; RV32ZICOND-NEXT: # %bb.1: # %overflow
5610 ; RV32ZICOND-NEXT: li a0, 0
5611 ; RV32ZICOND-NEXT: ret
5612 ; RV32ZICOND-NEXT: .LBB65_2: # %continue
5613 ; RV32ZICOND-NEXT: li a0, 1
5614 ; RV32ZICOND-NEXT: ret
5615 ;
5616 ; RV64ZICOND-LABEL: umulo2.br.i64:
5617 ; RV64ZICOND: # %bb.0: # %entry
5618 ; RV64ZICOND-NEXT: add a1, a0, a0
5619 ; RV64ZICOND-NEXT: bgeu a1, a0, .LBB65_2
5620 ; RV64ZICOND-NEXT: # %bb.1: # %overflow
5621 ; RV64ZICOND-NEXT: li a0, 0
5622 ; RV64ZICOND-NEXT: ret
5623 ; RV64ZICOND-NEXT: .LBB65_2: # %continue
5624 ; RV64ZICOND-NEXT: li a0, 1
5625 ; RV64ZICOND-NEXT: ret
5626 entry:
5627 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 2)
5628 %val = extractvalue {i64, i1} %t, 0
5629 %obit = extractvalue {i64, i1} %t, 1
5630 br i1 %obit, label %overflow, label %continue
5632 overflow:
5633 ret i1 false
5635 continue:
5636 ret i1 true
5637 }
5639 define zeroext i1 @uaddo.i64.constant(i64 %v1, ptr %res) {
5640 ; RV32-LABEL: uaddo.i64.constant:
5641 ; RV32: # %bb.0: # %entry
5642 ; RV32-NEXT: addi a3, a0, 2
5643 ; RV32-NEXT: sltu a0, a3, a0
5644 ; RV32-NEXT: add a4, a1, a0
5645 ; RV32-NEXT: sltu a1, a4, a1
5646 ; RV32-NEXT: and a0, a0, a1
5647 ; RV32-NEXT: sw a3, 0(a2)
5648 ; RV32-NEXT: sw a4, 4(a2)
5649 ; RV32-NEXT: ret
5650 ;
5651 ; RV64-LABEL: uaddo.i64.constant:
5652 ; RV64: # %bb.0: # %entry
5653 ; RV64-NEXT: addi a2, a0, 2
5654 ; RV64-NEXT: sltu a0, a2, a0
5655 ; RV64-NEXT: sd a2, 0(a1)
5656 ; RV64-NEXT: ret
5657 ;
5658 ; RV32ZBA-LABEL: uaddo.i64.constant:
5659 ; RV32ZBA: # %bb.0: # %entry
5660 ; RV32ZBA-NEXT: addi a3, a0, 2
5661 ; RV32ZBA-NEXT: sltu a0, a3, a0
5662 ; RV32ZBA-NEXT: add a4, a1, a0
5663 ; RV32ZBA-NEXT: sltu a1, a4, a1
5664 ; RV32ZBA-NEXT: and a0, a0, a1
5665 ; RV32ZBA-NEXT: sw a3, 0(a2)
5666 ; RV32ZBA-NEXT: sw a4, 4(a2)
5667 ; RV32ZBA-NEXT: ret
5668 ;
5669 ; RV64ZBA-LABEL: uaddo.i64.constant:
5670 ; RV64ZBA: # %bb.0: # %entry
5671 ; RV64ZBA-NEXT: addi a2, a0, 2
5672 ; RV64ZBA-NEXT: sltu a0, a2, a0
5673 ; RV64ZBA-NEXT: sd a2, 0(a1)
5674 ; RV64ZBA-NEXT: ret
5675 ;
5676 ; RV32ZICOND-LABEL: uaddo.i64.constant:
5677 ; RV32ZICOND: # %bb.0: # %entry
5678 ; RV32ZICOND-NEXT: addi a3, a0, 2
5679 ; RV32ZICOND-NEXT: sltu a0, a3, a0
5680 ; RV32ZICOND-NEXT: add a4, a1, a0
5681 ; RV32ZICOND-NEXT: sltu a1, a4, a1
5682 ; RV32ZICOND-NEXT: and a0, a0, a1
5683 ; RV32ZICOND-NEXT: sw a3, 0(a2)
5684 ; RV32ZICOND-NEXT: sw a4, 4(a2)
5685 ; RV32ZICOND-NEXT: ret
5686 ;
5687 ; RV64ZICOND-LABEL: uaddo.i64.constant:
5688 ; RV64ZICOND: # %bb.0: # %entry
5689 ; RV64ZICOND-NEXT: addi a2, a0, 2
5690 ; RV64ZICOND-NEXT: sltu a0, a2, a0
5691 ; RV64ZICOND-NEXT: sd a2, 0(a1)
5692 ; RV64ZICOND-NEXT: ret
5693 entry:
5694 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 2)
5695 %val = extractvalue {i64, i1} %t, 0
5696 %obit = extractvalue {i64, i1} %t, 1
5697 store i64 %val, ptr %res
5698 ret i1 %obit
5699 }
5701 define zeroext i1 @uaddo.i64.constant_2048(i64 %v1, ptr %res) {
5702 ; RV32-LABEL: uaddo.i64.constant_2048:
5703 ; RV32: # %bb.0: # %entry
5704 ; RV32-NEXT: addi a3, a0, 2047
5705 ; RV32-NEXT: addi a3, a3, 1
5706 ; RV32-NEXT: sltu a0, a3, a0
5707 ; RV32-NEXT: add a4, a1, a0
5708 ; RV32-NEXT: sltu a1, a4, a1
5709 ; RV32-NEXT: and a0, a0, a1
5710 ; RV32-NEXT: sw a3, 0(a2)
5711 ; RV32-NEXT: sw a4, 4(a2)
5712 ; RV32-NEXT: ret
5713 ;
5714 ; RV64-LABEL: uaddo.i64.constant_2048:
5715 ; RV64: # %bb.0: # %entry
5716 ; RV64-NEXT: addi a2, a0, 2047
5717 ; RV64-NEXT: addi a2, a2, 1
5718 ; RV64-NEXT: sltu a0, a2, a0
5719 ; RV64-NEXT: sd a2, 0(a1)
5720 ; RV64-NEXT: ret
5721 ;
5722 ; RV32ZBA-LABEL: uaddo.i64.constant_2048:
5723 ; RV32ZBA: # %bb.0: # %entry
5724 ; RV32ZBA-NEXT: addi a3, a0, 2047
5725 ; RV32ZBA-NEXT: addi a3, a3, 1
5726 ; RV32ZBA-NEXT: sltu a0, a3, a0
5727 ; RV32ZBA-NEXT: add a4, a1, a0
5728 ; RV32ZBA-NEXT: sltu a1, a4, a1
5729 ; RV32ZBA-NEXT: and a0, a0, a1
5730 ; RV32ZBA-NEXT: sw a3, 0(a2)
5731 ; RV32ZBA-NEXT: sw a4, 4(a2)
5732 ; RV32ZBA-NEXT: ret
5733 ;
5734 ; RV64ZBA-LABEL: uaddo.i64.constant_2048:
5735 ; RV64ZBA: # %bb.0: # %entry
5736 ; RV64ZBA-NEXT: addi a2, a0, 2047
5737 ; RV64ZBA-NEXT: addi a2, a2, 1
5738 ; RV64ZBA-NEXT: sltu a0, a2, a0
5739 ; RV64ZBA-NEXT: sd a2, 0(a1)
5740 ; RV64ZBA-NEXT: ret
5741 ;
5742 ; RV32ZICOND-LABEL: uaddo.i64.constant_2048:
5743 ; RV32ZICOND: # %bb.0: # %entry
5744 ; RV32ZICOND-NEXT: addi a3, a0, 2047
5745 ; RV32ZICOND-NEXT: addi a3, a3, 1
5746 ; RV32ZICOND-NEXT: sltu a0, a3, a0
5747 ; RV32ZICOND-NEXT: add a4, a1, a0
5748 ; RV32ZICOND-NEXT: sltu a1, a4, a1
5749 ; RV32ZICOND-NEXT: and a0, a0, a1
5750 ; RV32ZICOND-NEXT: sw a3, 0(a2)
5751 ; RV32ZICOND-NEXT: sw a4, 4(a2)
5752 ; RV32ZICOND-NEXT: ret
5753 ;
5754 ; RV64ZICOND-LABEL: uaddo.i64.constant_2048:
5755 ; RV64ZICOND: # %bb.0: # %entry
5756 ; RV64ZICOND-NEXT: addi a2, a0, 2047
5757 ; RV64ZICOND-NEXT: addi a2, a2, 1
5758 ; RV64ZICOND-NEXT: sltu a0, a2, a0
5759 ; RV64ZICOND-NEXT: sd a2, 0(a1)
5760 ; RV64ZICOND-NEXT: ret
5761 entry:
5762 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 2048)
5763 %val = extractvalue {i64, i1} %t, 0
5764 %obit = extractvalue {i64, i1} %t, 1
5765 store i64 %val, ptr %res
5766 ret i1 %obit
5767 }
5769 define zeroext i1 @uaddo.i64.constant_2049(i64 %v1, ptr %res) {
5770 ; RV32-LABEL: uaddo.i64.constant_2049:
5771 ; RV32: # %bb.0: # %entry
5772 ; RV32-NEXT: addi a3, a0, 2047
5773 ; RV32-NEXT: addi a3, a3, 2
5774 ; RV32-NEXT: sltu a0, a3, a0
5775 ; RV32-NEXT: add a4, a1, a0
5776 ; RV32-NEXT: sltu a1, a4, a1
5777 ; RV32-NEXT: and a0, a0, a1
5778 ; RV32-NEXT: sw a3, 0(a2)
5779 ; RV32-NEXT: sw a4, 4(a2)
5780 ; RV32-NEXT: ret
5781 ;
5782 ; RV64-LABEL: uaddo.i64.constant_2049:
5783 ; RV64: # %bb.0: # %entry
5784 ; RV64-NEXT: addi a2, a0, 2047
5785 ; RV64-NEXT: addi a2, a2, 2
5786 ; RV64-NEXT: sltu a0, a2, a0
5787 ; RV64-NEXT: sd a2, 0(a1)
5788 ; RV64-NEXT: ret
5789 ;
5790 ; RV32ZBA-LABEL: uaddo.i64.constant_2049:
5791 ; RV32ZBA: # %bb.0: # %entry
5792 ; RV32ZBA-NEXT: addi a3, a0, 2047
5793 ; RV32ZBA-NEXT: addi a3, a3, 2
5794 ; RV32ZBA-NEXT: sltu a0, a3, a0
5795 ; RV32ZBA-NEXT: add a4, a1, a0
5796 ; RV32ZBA-NEXT: sltu a1, a4, a1
5797 ; RV32ZBA-NEXT: and a0, a0, a1
5798 ; RV32ZBA-NEXT: sw a3, 0(a2)
5799 ; RV32ZBA-NEXT: sw a4, 4(a2)
5800 ; RV32ZBA-NEXT: ret
5801 ;
5802 ; RV64ZBA-LABEL: uaddo.i64.constant_2049:
5803 ; RV64ZBA: # %bb.0: # %entry
5804 ; RV64ZBA-NEXT: addi a2, a0, 2047
5805 ; RV64ZBA-NEXT: addi a2, a2, 2
5806 ; RV64ZBA-NEXT: sltu a0, a2, a0
5807 ; RV64ZBA-NEXT: sd a2, 0(a1)
5808 ; RV64ZBA-NEXT: ret
5809 ;
5810 ; RV32ZICOND-LABEL: uaddo.i64.constant_2049:
5811 ; RV32ZICOND: # %bb.0: # %entry
5812 ; RV32ZICOND-NEXT: addi a3, a0, 2047
5813 ; RV32ZICOND-NEXT: addi a3, a3, 2
5814 ; RV32ZICOND-NEXT: sltu a0, a3, a0
5815 ; RV32ZICOND-NEXT: add a4, a1, a0
5816 ; RV32ZICOND-NEXT: sltu a1, a4, a1
5817 ; RV32ZICOND-NEXT: and a0, a0, a1
5818 ; RV32ZICOND-NEXT: sw a3, 0(a2)
5819 ; RV32ZICOND-NEXT: sw a4, 4(a2)
5820 ; RV32ZICOND-NEXT: ret
5821 ;
5822 ; RV64ZICOND-LABEL: uaddo.i64.constant_2049:
5823 ; RV64ZICOND: # %bb.0: # %entry
5824 ; RV64ZICOND-NEXT: addi a2, a0, 2047
5825 ; RV64ZICOND-NEXT: addi a2, a2, 2
5826 ; RV64ZICOND-NEXT: sltu a0, a2, a0
5827 ; RV64ZICOND-NEXT: sd a2, 0(a1)
5828 ; RV64ZICOND-NEXT: ret
5829 entry:
5830 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 2049)
5831 %val = extractvalue {i64, i1} %t, 0
5832 %obit = extractvalue {i64, i1} %t, 1
5833 store i64 %val, ptr %res
5834 ret i1 %obit
5835 }
5837 define i64 @uaddo.i64.constant_setcc_on_overflow_flag(ptr %p) {
5838 ; RV32-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
5839 ; RV32: # %bb.0: # %entry
5840 ; RV32-NEXT: lw a1, 0(a0)
5841 ; RV32-NEXT: lw a2, 4(a0)
5842 ; RV32-NEXT: addi a0, a1, 2
5843 ; RV32-NEXT: sltu a3, a0, a1
5844 ; RV32-NEXT: add a1, a2, a3
5845 ; RV32-NEXT: sltu a2, a1, a2
5846 ; RV32-NEXT: and a2, a3, a2
5847 ; RV32-NEXT: bnez a2, .LBB69_2
5848 ; RV32-NEXT: # %bb.1: # %IfOverflow
5849 ; RV32-NEXT: li a0, 0
5850 ; RV32-NEXT: li a1, 0
5851 ; RV32-NEXT: .LBB69_2: # %IfNoOverflow
5852 ; RV32-NEXT: ret
5853 ;
5854 ; RV64-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
5855 ; RV64: # %bb.0: # %entry
5856 ; RV64-NEXT: ld a1, 0(a0)
5857 ; RV64-NEXT: addi a0, a1, 2
5858 ; RV64-NEXT: bltu a0, a1, .LBB69_2
5859 ; RV64-NEXT: # %bb.1: # %IfOverflow
5860 ; RV64-NEXT: li a0, 0
5861 ; RV64-NEXT: .LBB69_2: # %IfNoOverflow
5862 ; RV64-NEXT: ret
5863 ;
5864 ; RV32ZBA-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
5865 ; RV32ZBA: # %bb.0: # %entry
5866 ; RV32ZBA-NEXT: lw a1, 0(a0)
5867 ; RV32ZBA-NEXT: lw a2, 4(a0)
5868 ; RV32ZBA-NEXT: addi a0, a1, 2
5869 ; RV32ZBA-NEXT: sltu a3, a0, a1
5870 ; RV32ZBA-NEXT: add a1, a2, a3
5871 ; RV32ZBA-NEXT: sltu a2, a1, a2
5872 ; RV32ZBA-NEXT: and a2, a3, a2
5873 ; RV32ZBA-NEXT: bnez a2, .LBB69_2
5874 ; RV32ZBA-NEXT: # %bb.1: # %IfOverflow
5875 ; RV32ZBA-NEXT: li a0, 0
5876 ; RV32ZBA-NEXT: li a1, 0
5877 ; RV32ZBA-NEXT: .LBB69_2: # %IfNoOverflow
5878 ; RV32ZBA-NEXT: ret
5879 ;
5880 ; RV64ZBA-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
5881 ; RV64ZBA: # %bb.0: # %entry
5882 ; RV64ZBA-NEXT: ld a1, 0(a0)
5883 ; RV64ZBA-NEXT: addi a0, a1, 2
5884 ; RV64ZBA-NEXT: bltu a0, a1, .LBB69_2
5885 ; RV64ZBA-NEXT: # %bb.1: # %IfOverflow
5886 ; RV64ZBA-NEXT: li a0, 0
5887 ; RV64ZBA-NEXT: .LBB69_2: # %IfNoOverflow
5888 ; RV64ZBA-NEXT: ret
5889 ;
5890 ; RV32ZICOND-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
5891 ; RV32ZICOND: # %bb.0: # %entry
5892 ; RV32ZICOND-NEXT: lw a1, 0(a0)
5893 ; RV32ZICOND-NEXT: lw a2, 4(a0)
5894 ; RV32ZICOND-NEXT: addi a0, a1, 2
5895 ; RV32ZICOND-NEXT: sltu a3, a0, a1
5896 ; RV32ZICOND-NEXT: add a1, a2, a3
5897 ; RV32ZICOND-NEXT: sltu a2, a1, a2
5898 ; RV32ZICOND-NEXT: and a2, a3, a2
5899 ; RV32ZICOND-NEXT: bnez a2, .LBB69_2
5900 ; RV32ZICOND-NEXT: # %bb.1: # %IfOverflow
5901 ; RV32ZICOND-NEXT: li a0, 0
5902 ; RV32ZICOND-NEXT: li a1, 0
5903 ; RV32ZICOND-NEXT: .LBB69_2: # %IfNoOverflow
5904 ; RV32ZICOND-NEXT: ret
5905 ;
5906 ; RV64ZICOND-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
5907 ; RV64ZICOND: # %bb.0: # %entry
5908 ; RV64ZICOND-NEXT: ld a1, 0(a0)
5909 ; RV64ZICOND-NEXT: addi a0, a1, 2
5910 ; RV64ZICOND-NEXT: bltu a0, a1, .LBB69_2
5911 ; RV64ZICOND-NEXT: # %bb.1: # %IfOverflow
5912 ; RV64ZICOND-NEXT: li a0, 0
5913 ; RV64ZICOND-NEXT: .LBB69_2: # %IfNoOverflow
5914 ; RV64ZICOND-NEXT: ret
5915 entry:
5916 %v1 = load i64, ptr %p
5917 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 2)
5918 %val = extractvalue {i64, i1} %t, 0
5919 %obit = extractvalue {i64, i1} %t, 1
5920 br i1 %obit, label %IfNoOverflow, label %IfOverflow
5921 IfOverflow:
5922 ret i64 0
5923 IfNoOverflow:
5924 ret i64 %val
5925 }
5927 declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
5928 declare {i64, i1} @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
5929 declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
5930 declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
5931 declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
5932 declare {i64, i1} @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
5933 declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
5934 declare {i64, i1} @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
5935 declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone
5936 declare {i64, i1} @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
5937 declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
5938 declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone