| blob | eec1c3973923fa9399278998f138c6e092136b0e |
1 # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
2 # CHECK-NOT: t2DLS
3 # CHECK: bb.5.for.inc16:
4 # CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
5 # CHECK-NOT: t2CMPri $lr
6 # CHECK: tBcc %bb.6, 1 /* CC::ne */
7 # CHECK: tB %bb.2
8 # CHECK: bb.6.for.cond4.preheader:
10 --- |
11 ; ModuleID = 'revert-non-header.ll'
12 source_filename = "revert-non-header.ll"
13 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
14 target triple = "thumbv8.1m.main"
16 define void @header_not_target_unrolled_loop(ptr nocapture %v, i32 %n) {
17 entry:
18 %cmp56 = icmp sgt i32 %n, 1
19 br i1 %cmp56, label %for.cond1.preheader.preheader, label %for.end20
21 for.cond1.preheader.preheader: ; preds = %entry
22 br label %for.cond1.preheader
24 for.cond.loopexit: ; preds = %for.inc16, %for.cond1.preheader
25 %cmp = icmp sgt i32 %gap.057.in, 3
26 br i1 %cmp, label %for.cond1.preheader, label %for.end20
28 for.cond1.preheader: ; preds = %for.cond1.preheader.preheader, %for.cond.loopexit
29 %gap.057.in = phi i32 [ %gap.057, %for.cond.loopexit ], [ %n, %for.cond1.preheader.preheader ]
30 %gap.057 = sdiv i32 %gap.057.in, 2
31 %cmp252 = icmp slt i32 %gap.057, %n
32 %tmp = sub i32 %n, %gap.057
33 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp)
34 br i1 %cmp252, label %for.cond4.preheader.preheader, label %for.cond.loopexit
36 for.cond4.preheader.preheader: ; preds = %for.cond1.preheader
37 %tmp2 = mul i32 %gap.057, -4
38 %tmp6 = mul i32 %gap.057, -2
39 %scevgep1 = getelementptr i32, ptr %v, i32 %gap.057
40 %0 = shl i32 %gap.057, 2
41 br label %for.cond4.preheader
43 for.cond4.preheader: ; preds = %for.inc16, %for.cond4.preheader.preheader
44 %lsr.iv2 = phi ptr [ %scevgep3, %for.inc16 ], [ %scevgep1, %for.cond4.preheader.preheader ]
45 %lsr.iv = phi ptr [ %v, %for.cond4.preheader.preheader ], [ %scevgep, %for.inc16 ]
46 %i.053 = phi i32 [ %inc, %for.inc16 ], [ %gap.057, %for.cond4.preheader.preheader ]
47 %tmp8 = phi i32 [ %start, %for.cond4.preheader.preheader ], [ %tmp16, %for.inc16 ]
48 %j.048 = sub nsw i32 %i.053, %gap.057
49 %cmp549 = icmp sgt i32 %j.048, -1
50 br i1 %cmp549, label %land.rhs.preheader, label %for.inc16
52 land.rhs.preheader: ; preds = %for.cond4.preheader
53 br label %land.rhs
55 land.rhs: ; preds = %land.rhs.preheader, %for.body8
56 %lsr.iv4 = phi i32 [ %lsr.iv.next, %for.body8 ], [ 0, %land.rhs.preheader ]
57 %j.051 = phi i32 [ %j.0, %for.body8 ], [ %j.048, %land.rhs.preheader ]
58 %1 = bitcast ptr %lsr.iv2 to ptr
59 %2 = bitcast ptr %lsr.iv to ptr
60 %uglygep3 = getelementptr i8, ptr %2, i32 %lsr.iv4
61 %uglygep34 = bitcast ptr %uglygep3 to ptr
62 %tmp9 = load i32, ptr %uglygep34, align 4
63 %uglygep1 = getelementptr i8, ptr %1, i32 %lsr.iv4
64 %uglygep12 = bitcast ptr %uglygep1 to ptr
65 %tmp12 = load i32, ptr %uglygep12, align 4
66 %cmp7 = icmp sgt i32 %tmp9, %tmp12
67 br i1 %cmp7, label %for.body8, label %for.inc16
69 for.body8: ; preds = %land.rhs
70 %3 = bitcast ptr %lsr.iv2 to ptr
71 %4 = bitcast ptr %lsr.iv to ptr
72 %sunkaddr = getelementptr i8, ptr %4, i32 %lsr.iv4
73 %5 = bitcast ptr %sunkaddr to ptr
74 store i32 %tmp12, ptr %5, align 4
75 %uglygep = getelementptr i8, ptr %3, i32 %lsr.iv4
76 %uglygep6 = bitcast ptr %uglygep to ptr
77 store i32 %tmp9, ptr %uglygep6, align 4
78 %j.0 = sub nsw i32 %j.051, %gap.057
79 %lsr.iv.next = add i32 %lsr.iv4, %0
80 %cmp5 = icmp sgt i32 %j.0, -1
81 br i1 %cmp5, label %land.rhs, label %for.inc16
83 for.inc16: ; preds = %for.body8, %land.rhs, %for.cond4.preheader
84 %inc = add nsw i32 %i.053, 1
85 %scevgep = getelementptr i32, ptr %lsr.iv, i32 1
86 %tmp16 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp8, i32 1)
87 %tmp17 = icmp ne i32 %tmp16, 0
88 %scevgep3 = getelementptr i32, ptr %lsr.iv2, i32 1
89 br i1 %tmp17, label %for.cond4.preheader, label %for.cond.loopexit
91 for.end20: ; preds = %for.cond.loopexit, %entry
92 ret void
93 }
95 ; Function Attrs: noduplicate nounwind
96 declare i32 @llvm.start.loop.iterations.i32(i32) #0
98 ; Function Attrs: noduplicate nounwind
99 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
101 ; Function Attrs: nounwind
102 declare void @llvm.stackprotector(ptr, ptr) #1
104 attributes #0 = { noduplicate nounwind }
105 attributes #1 = { nounwind }
107 ...
108 ---
109 name: header_not_target_unrolled_loop
110 alignment: 2
111 exposesReturnsTwice: false
112 legalized: false
113 regBankSelected: false
114 selected: false
115 failedISel: false
116 tracksRegLiveness: true
117 hasWinCFI: false
118 registers: []
119 liveins:
120 - { reg: '$r0', virtual-reg: '' }
121 - { reg: '$r1', virtual-reg: '' }
122 frameInfo:
123 isFrameAddressTaken: false
124 isReturnAddressTaken: false
125 hasStackMap: false
126 hasPatchPoint: false
127 stackSize: 32
128 offsetAdjustment: 0
129 maxAlignment: 4
130 adjustsStack: false
131 hasCalls: false
132 stackProtector: ''
133 maxCallFrameSize: 0
134 cvBytesOfCalleeSavedRegisters: 0
135 hasOpaqueSPAdjustment: false
136 hasVAStart: false
137 hasMustTailInVarArgFunc: false
138 localFrameSize: 0
139 savePoint: ''
140 restorePoint: ''
141 fixedStack: []
142 stack:
143 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
144 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
145 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
146 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
147 stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true,
148 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
149 - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
150 stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true,
151 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
152 - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
153 stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true,
154 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
155 - { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
156 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
157 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
158 - { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
159 stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
160 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
161 - { id: 6, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
162 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
163 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
164 - { id: 7, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
165 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
166 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
167 callSites: []
168 constants: []
169 machineFunctionInfo: {}
170 body: |
171 bb.0.entry:
172 successors: %bb.1(0x40000000), %bb.9(0x40000000)
173 liveins: $r0, $r1, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $lr
175 $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr
176 frame-setup CFI_INSTRUCTION def_cfa_offset 32
177 frame-setup CFI_INSTRUCTION offset $lr, -4
178 frame-setup CFI_INSTRUCTION offset $r10, -8
179 frame-setup CFI_INSTRUCTION offset $r9, -12
180 frame-setup CFI_INSTRUCTION offset $r8, -16
181 frame-setup CFI_INSTRUCTION offset $r7, -20
182 frame-setup CFI_INSTRUCTION offset $r6, -24
183 frame-setup CFI_INSTRUCTION offset $r5, -28
184 frame-setup CFI_INSTRUCTION offset $r4, -32
185 tCMPi8 renamable $r1, 2, 14, $noreg, implicit-def $cpsr
186 tBcc %bb.9, 11, killed $cpsr
188 bb.1:
189 successors: %bb.3(0x80000000)
190 liveins: $r0, $r1
192 $r9 = tMOVr $r1, 14, $noreg
193 tB %bb.3, 14, $noreg
195 bb.2.for.cond.loopexit:
196 successors: %bb.3(0x7c000000), %bb.9(0x04000000)
197 liveins: $r0, $r1, $r9, $r12
199 t2CMPri killed renamable $r12, 4, 14, $noreg, implicit-def $cpsr
200 tBcc %bb.9, 11, killed $cpsr
202 bb.3.for.cond1.preheader:
203 successors: %bb.4(0x40000000), %bb.2(0x40000000)
204 liveins: $r0, $r1, $r9
206 renamable $r2 = t2ADDrs $r9, $r9, 251, 14, $noreg, $noreg
207 $r12 = tMOVr killed $r9, 14, $noreg
208 renamable $lr = t2SUBrs renamable $r1, renamable $r2, 9, 14, $noreg, $noreg
209 renamable $r9 = t2ASRri renamable $r2, 1, 14, $noreg, $noreg
210 t2CMPrs renamable $r1, killed renamable $r2, 9, 14, $noreg, implicit-def $cpsr
211 $lr = t2DoLoopStart renamable $lr
212 tBcc %bb.2, 13, killed $cpsr
214 bb.4.for.cond4.preheader.preheader:
215 successors: %bb.7(0x50000000), %bb.5(0x30000000)
216 liveins: $lr, $r0, $r1, $r9, $r12
218 renamable $r3 = t2ADDrs renamable $r0, renamable $r9, 18, 14, $noreg, $noreg
219 renamable $r10 = t2LSLri renamable $r9, 2, 14, $noreg, $noreg
220 $r5 = tMOVr $r0, 14, $noreg
221 $r8 = tMOVr $r9, 14, $noreg
222 renamable $r7 = nsw t2SUBrr renamable $r8, renamable $r9, 14, $noreg, def $cpsr
223 tBcc %bb.7, 5, killed $cpsr
225 bb.5.for.inc16:
226 successors: %bb.6(0x7c000000), %bb.2(0x04000000)
227 liveins: $lr, $r0, $r1, $r3, $r5, $r8, $r9, $r10, $r12
229 renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg
230 renamable $r5, dead $cpsr = tADDi8 killed renamable $r5, 4, 14, $noreg
231 renamable $r8 = nsw t2ADDri killed renamable $r8, 1, 14, $noreg, $noreg
232 renamable $lr = t2LoopDec killed renamable $lr, 1
233 t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
234 tB %bb.2, 14, $noreg
236 bb.6.for.cond4.preheader:
237 successors: %bb.7(0x50000000), %bb.5(0x30000000)
238 liveins: $lr, $r0, $r1, $r3, $r5, $r8, $r9, $r10, $r12
240 renamable $r7 = nsw t2SUBrr renamable $r8, renamable $r9, 14, $noreg, def $cpsr
241 tBcc %bb.5, 4, killed $cpsr
243 bb.7.land.rhs.preheader:
244 successors: %bb.8(0x80000000)
245 liveins: $lr, $r0, $r1, $r3, $r5, $r7, $r8, $r9, $r10, $r12
247 renamable $r6, dead $cpsr = tMOVi8 0, 14, $noreg
249 bb.8.land.rhs:
250 successors: %bb.5(0x07e00000), %bb.8(0x78200000)
251 liveins: $lr, $r0, $r1, $r3, $r5, $r6, $r7, $r8, $r9, $r10, $r12
253 renamable $r4 = tLDRr renamable $r3, $r6, 14, $noreg :: (load (s32) from %ir.uglygep12)
254 renamable $r2 = tLDRr renamable $r5, $r6, 14, $noreg :: (load (s32) from %ir.uglygep34)
255 tCMPr renamable $r2, renamable $r4, 14, $noreg, implicit-def $cpsr
256 t2IT 12, 1, implicit-def $itstate
257 tSTRr killed renamable $r4, renamable $r5, $r6, 12, $cpsr, implicit $itstate :: (store (s32) into %ir.5)
258 tSTRr killed renamable $r2, renamable $r3, $r6, 12, $cpsr, implicit $itstate :: (store (s32) into %ir.uglygep6)
259 renamable $r6 = tADDhirr killed renamable $r6, renamable $r10, 12, $cpsr, implicit $r6, implicit $itstate
260 renamable $r7 = nsw t2SUBrr killed renamable $r7, renamable $r9, 12, $cpsr, $noreg, implicit $r7, implicit killed $itstate
261 t2IT 12, 8, implicit-def $itstate
262 t2CMPri renamable $r7, -1, 12, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
263 tBcc %bb.8, 12, killed $cpsr
264 tB %bb.5, 14, $noreg
266 bb.9.for.end20:
267 $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $pc
269 ...