1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
4 define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) {
5 ; CHECK-LABEL: cmpeqz_v4i1:
6 ; CHECK: @ %bb.0: @ %entry
7 ; CHECK-NEXT: vcmp.i32 eq, q1, zr
8 ; CHECK-NEXT: vmrs r0, p0
9 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
10 ; CHECK-NEXT: vmrs r1, p0
11 ; CHECK-NEXT: eors r0, r1
12 ; CHECK-NEXT: vmsr p0, r0
13 ; CHECK-NEXT: vpsel q0, q0, q1
16 %c1 = icmp eq <4 x i32> %a, zeroinitializer
17 %c2 = icmp eq <4 x i32> %b, zeroinitializer
18 %o = xor <4 x i1> %c1, %c2
19 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
23 define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b) {
24 ; CHECK-LABEL: cmpnez_v4i1:
25 ; CHECK: @ %bb.0: @ %entry
26 ; CHECK-NEXT: vcmp.i32 ne, q1, zr
27 ; CHECK-NEXT: vmrs r0, p0
28 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
29 ; CHECK-NEXT: vmrs r1, p0
30 ; CHECK-NEXT: eors r0, r1
31 ; CHECK-NEXT: vmsr p0, r0
32 ; CHECK-NEXT: vpsel q0, q0, q1
35 %c1 = icmp eq <4 x i32> %a, zeroinitializer
36 %c2 = icmp ne <4 x i32> %b, zeroinitializer
37 %o = xor <4 x i1> %c1, %c2
38 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
42 define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b) {
43 ; CHECK-LABEL: cmpsltz_v4i1:
44 ; CHECK: @ %bb.0: @ %entry
45 ; CHECK-NEXT: vcmp.s32 lt, q1, zr
46 ; CHECK-NEXT: vmrs r0, p0
47 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
48 ; CHECK-NEXT: vmrs r1, p0
49 ; CHECK-NEXT: eors r0, r1
50 ; CHECK-NEXT: vmsr p0, r0
51 ; CHECK-NEXT: vpsel q0, q0, q1
54 %c1 = icmp eq <4 x i32> %a, zeroinitializer
55 %c2 = icmp slt <4 x i32> %b, zeroinitializer
56 %o = xor <4 x i1> %c1, %c2
57 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
61 define arm_aapcs_vfpcc <4 x i32> @cmpsgtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
62 ; CHECK-LABEL: cmpsgtz_v4i1:
63 ; CHECK: @ %bb.0: @ %entry
64 ; CHECK-NEXT: vcmp.s32 gt, q1, zr
65 ; CHECK-NEXT: vmrs r0, p0
66 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
67 ; CHECK-NEXT: vmrs r1, p0
68 ; CHECK-NEXT: eors r0, r1
69 ; CHECK-NEXT: vmsr p0, r0
70 ; CHECK-NEXT: vpsel q0, q0, q1
73 %c1 = icmp eq <4 x i32> %a, zeroinitializer
74 %c2 = icmp sgt <4 x i32> %b, zeroinitializer
75 %o = xor <4 x i1> %c1, %c2
76 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
80 define arm_aapcs_vfpcc <4 x i32> @cmpslez_v4i1(<4 x i32> %a, <4 x i32> %b) {
81 ; CHECK-LABEL: cmpslez_v4i1:
82 ; CHECK: @ %bb.0: @ %entry
83 ; CHECK-NEXT: vcmp.s32 le, q1, zr
84 ; CHECK-NEXT: vmrs r0, p0
85 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
86 ; CHECK-NEXT: vmrs r1, p0
87 ; CHECK-NEXT: eors r0, r1
88 ; CHECK-NEXT: vmsr p0, r0
89 ; CHECK-NEXT: vpsel q0, q0, q1
92 %c1 = icmp eq <4 x i32> %a, zeroinitializer
93 %c2 = icmp sle <4 x i32> %b, zeroinitializer
94 %o = xor <4 x i1> %c1, %c2
95 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
99 define arm_aapcs_vfpcc <4 x i32> @cmpsgez_v4i1(<4 x i32> %a, <4 x i32> %b) {
100 ; CHECK-LABEL: cmpsgez_v4i1:
101 ; CHECK: @ %bb.0: @ %entry
102 ; CHECK-NEXT: vcmp.s32 ge, q1, zr
103 ; CHECK-NEXT: vmrs r0, p0
104 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
105 ; CHECK-NEXT: vmrs r1, p0
106 ; CHECK-NEXT: eors r0, r1
107 ; CHECK-NEXT: vmsr p0, r0
108 ; CHECK-NEXT: vpsel q0, q0, q1
111 %c1 = icmp eq <4 x i32> %a, zeroinitializer
112 %c2 = icmp sge <4 x i32> %b, zeroinitializer
113 %o = xor <4 x i1> %c1, %c2
114 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
118 define arm_aapcs_vfpcc <4 x i32> @cmpultz_v4i1(<4 x i32> %a, <4 x i32> %b) {
119 ; CHECK-LABEL: cmpultz_v4i1:
120 ; CHECK: @ %bb.0: @ %entry
121 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
122 ; CHECK-NEXT: vpsel q0, q0, q1
125 %c1 = icmp eq <4 x i32> %a, zeroinitializer
126 %c2 = icmp ult <4 x i32> %b, zeroinitializer
127 %o = xor <4 x i1> %c1, %c2
128 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
132 define arm_aapcs_vfpcc <4 x i32> @cmpugtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
133 ; CHECK-LABEL: cmpugtz_v4i1:
134 ; CHECK: @ %bb.0: @ %entry
135 ; CHECK-NEXT: vcmp.i32 ne, q1, zr
136 ; CHECK-NEXT: vmrs r0, p0
137 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
138 ; CHECK-NEXT: vmrs r1, p0
139 ; CHECK-NEXT: eors r0, r1
140 ; CHECK-NEXT: vmsr p0, r0
141 ; CHECK-NEXT: vpsel q0, q0, q1
144 %c1 = icmp eq <4 x i32> %a, zeroinitializer
145 %c2 = icmp ugt <4 x i32> %b, zeroinitializer
146 %o = xor <4 x i1> %c1, %c2
147 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
151 define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {
152 ; CHECK-LABEL: cmpulez_v4i1:
153 ; CHECK: @ %bb.0: @ %entry
154 ; CHECK-NEXT: vmov.i32 q2, #0x0
155 ; CHECK-NEXT: vcmp.u32 cs, q2, q1
156 ; CHECK-NEXT: vmrs r0, p0
157 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
158 ; CHECK-NEXT: vmrs r1, p0
159 ; CHECK-NEXT: eors r0, r1
160 ; CHECK-NEXT: vmsr p0, r0
161 ; CHECK-NEXT: vpsel q0, q0, q1
164 %c1 = icmp eq <4 x i32> %a, zeroinitializer
165 %c2 = icmp ule <4 x i32> %b, zeroinitializer
166 %o = xor <4 x i1> %c1, %c2
167 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
171 define arm_aapcs_vfpcc <4 x i32> @cmpugez_v4i1(<4 x i32> %a, <4 x i32> %b) {
172 ; CHECK-LABEL: cmpugez_v4i1:
173 ; CHECK: @ %bb.0: @ %entry
174 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
175 ; CHECK-NEXT: vpsel q0, q1, q0
178 %c1 = icmp eq <4 x i32> %a, zeroinitializer
179 %c2 = icmp uge <4 x i32> %b, zeroinitializer
180 %o = xor <4 x i1> %c1, %c2
181 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
187 define arm_aapcs_vfpcc <4 x i32> @cmpeq_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
188 ; CHECK-LABEL: cmpeq_v4i1:
189 ; CHECK: @ %bb.0: @ %entry
190 ; CHECK-NEXT: vcmp.i32 eq, q1, q2
191 ; CHECK-NEXT: vmrs r0, p0
192 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
193 ; CHECK-NEXT: vmrs r1, p0
194 ; CHECK-NEXT: eors r0, r1
195 ; CHECK-NEXT: vmsr p0, r0
196 ; CHECK-NEXT: vpsel q0, q0, q1
199 %c1 = icmp eq <4 x i32> %a, zeroinitializer
200 %c2 = icmp eq <4 x i32> %b, %c
201 %o = xor <4 x i1> %c1, %c2
202 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
206 define arm_aapcs_vfpcc <4 x i32> @cmpne_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
207 ; CHECK-LABEL: cmpne_v4i1:
208 ; CHECK: @ %bb.0: @ %entry
209 ; CHECK-NEXT: vcmp.i32 ne, q1, q2
210 ; CHECK-NEXT: vmrs r0, p0
211 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
212 ; CHECK-NEXT: vmrs r1, p0
213 ; CHECK-NEXT: eors r0, r1
214 ; CHECK-NEXT: vmsr p0, r0
215 ; CHECK-NEXT: vpsel q0, q0, q1
218 %c1 = icmp eq <4 x i32> %a, zeroinitializer
219 %c2 = icmp ne <4 x i32> %b, %c
220 %o = xor <4 x i1> %c1, %c2
221 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
225 define arm_aapcs_vfpcc <4 x i32> @cmpslt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
226 ; CHECK-LABEL: cmpslt_v4i1:
227 ; CHECK: @ %bb.0: @ %entry
228 ; CHECK-NEXT: vcmp.s32 gt, q2, q1
229 ; CHECK-NEXT: vmrs r0, p0
230 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
231 ; CHECK-NEXT: vmrs r1, p0
232 ; CHECK-NEXT: eors r0, r1
233 ; CHECK-NEXT: vmsr p0, r0
234 ; CHECK-NEXT: vpsel q0, q0, q1
237 %c1 = icmp eq <4 x i32> %a, zeroinitializer
238 %c2 = icmp slt <4 x i32> %b, %c
239 %o = xor <4 x i1> %c1, %c2
240 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
244 define arm_aapcs_vfpcc <4 x i32> @cmpsgt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
245 ; CHECK-LABEL: cmpsgt_v4i1:
246 ; CHECK: @ %bb.0: @ %entry
247 ; CHECK-NEXT: vcmp.s32 gt, q1, q2
248 ; CHECK-NEXT: vmrs r0, p0
249 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
250 ; CHECK-NEXT: vmrs r1, p0
251 ; CHECK-NEXT: eors r0, r1
252 ; CHECK-NEXT: vmsr p0, r0
253 ; CHECK-NEXT: vpsel q0, q0, q1
256 %c1 = icmp eq <4 x i32> %a, zeroinitializer
257 %c2 = icmp sgt <4 x i32> %b, %c
258 %o = xor <4 x i1> %c1, %c2
259 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
263 define arm_aapcs_vfpcc <4 x i32> @cmpsle_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
264 ; CHECK-LABEL: cmpsle_v4i1:
265 ; CHECK: @ %bb.0: @ %entry
266 ; CHECK-NEXT: vcmp.s32 ge, q2, q1
267 ; CHECK-NEXT: vmrs r0, p0
268 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
269 ; CHECK-NEXT: vmrs r1, p0
270 ; CHECK-NEXT: eors r0, r1
271 ; CHECK-NEXT: vmsr p0, r0
272 ; CHECK-NEXT: vpsel q0, q0, q1
275 %c1 = icmp eq <4 x i32> %a, zeroinitializer
276 %c2 = icmp sle <4 x i32> %b, %c
277 %o = xor <4 x i1> %c1, %c2
278 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
282 define arm_aapcs_vfpcc <4 x i32> @cmpsge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
283 ; CHECK-LABEL: cmpsge_v4i1:
284 ; CHECK: @ %bb.0: @ %entry
285 ; CHECK-NEXT: vcmp.s32 ge, q1, q2
286 ; CHECK-NEXT: vmrs r0, p0
287 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
288 ; CHECK-NEXT: vmrs r1, p0
289 ; CHECK-NEXT: eors r0, r1
290 ; CHECK-NEXT: vmsr p0, r0
291 ; CHECK-NEXT: vpsel q0, q0, q1
294 %c1 = icmp eq <4 x i32> %a, zeroinitializer
295 %c2 = icmp sge <4 x i32> %b, %c
296 %o = xor <4 x i1> %c1, %c2
297 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
301 define arm_aapcs_vfpcc <4 x i32> @cmpult_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
302 ; CHECK-LABEL: cmpult_v4i1:
303 ; CHECK: @ %bb.0: @ %entry
304 ; CHECK-NEXT: vcmp.u32 hi, q2, q1
305 ; CHECK-NEXT: vmrs r0, p0
306 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
307 ; CHECK-NEXT: vmrs r1, p0
308 ; CHECK-NEXT: eors r0, r1
309 ; CHECK-NEXT: vmsr p0, r0
310 ; CHECK-NEXT: vpsel q0, q0, q1
313 %c1 = icmp eq <4 x i32> %a, zeroinitializer
314 %c2 = icmp ult <4 x i32> %b, %c
315 %o = xor <4 x i1> %c1, %c2
316 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
320 define arm_aapcs_vfpcc <4 x i32> @cmpugt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
321 ; CHECK-LABEL: cmpugt_v4i1:
322 ; CHECK: @ %bb.0: @ %entry
323 ; CHECK-NEXT: vcmp.u32 hi, q1, q2
324 ; CHECK-NEXT: vmrs r0, p0
325 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
326 ; CHECK-NEXT: vmrs r1, p0
327 ; CHECK-NEXT: eors r0, r1
328 ; CHECK-NEXT: vmsr p0, r0
329 ; CHECK-NEXT: vpsel q0, q0, q1
332 %c1 = icmp eq <4 x i32> %a, zeroinitializer
333 %c2 = icmp ugt <4 x i32> %b, %c
334 %o = xor <4 x i1> %c1, %c2
335 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
339 define arm_aapcs_vfpcc <4 x i32> @cmpule_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
340 ; CHECK-LABEL: cmpule_v4i1:
341 ; CHECK: @ %bb.0: @ %entry
342 ; CHECK-NEXT: vcmp.u32 cs, q2, q1
343 ; CHECK-NEXT: vmrs r0, p0
344 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
345 ; CHECK-NEXT: vmrs r1, p0
346 ; CHECK-NEXT: eors r0, r1
347 ; CHECK-NEXT: vmsr p0, r0
348 ; CHECK-NEXT: vpsel q0, q0, q1
351 %c1 = icmp eq <4 x i32> %a, zeroinitializer
352 %c2 = icmp ule <4 x i32> %b, %c
353 %o = xor <4 x i1> %c1, %c2
354 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
358 define arm_aapcs_vfpcc <4 x i32> @cmpuge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
359 ; CHECK-LABEL: cmpuge_v4i1:
360 ; CHECK: @ %bb.0: @ %entry
361 ; CHECK-NEXT: vcmp.u32 cs, q1, q2
362 ; CHECK-NEXT: vmrs r0, p0
363 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
364 ; CHECK-NEXT: vmrs r1, p0
365 ; CHECK-NEXT: eors r0, r1
366 ; CHECK-NEXT: vmsr p0, r0
367 ; CHECK-NEXT: vpsel q0, q0, q1
370 %c1 = icmp eq <4 x i32> %a, zeroinitializer
371 %c2 = icmp uge <4 x i32> %b, %c
372 %o = xor <4 x i1> %c1, %c2
373 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
380 define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b) {
381 ; CHECK-LABEL: cmpeqz_v8i1:
382 ; CHECK: @ %bb.0: @ %entry
383 ; CHECK-NEXT: vcmp.i16 eq, q1, zr
384 ; CHECK-NEXT: vmrs r0, p0
385 ; CHECK-NEXT: vcmp.i16 eq, q0, zr
386 ; CHECK-NEXT: vmrs r1, p0
387 ; CHECK-NEXT: eors r0, r1
388 ; CHECK-NEXT: vmsr p0, r0
389 ; CHECK-NEXT: vpsel q0, q0, q1
392 %c1 = icmp eq <8 x i16> %a, zeroinitializer
393 %c2 = icmp eq <8 x i16> %b, zeroinitializer
394 %o = xor <8 x i1> %c1, %c2
395 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b
399 define arm_aapcs_vfpcc <8 x i16> @cmpeq_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
400 ; CHECK-LABEL: cmpeq_v8i1:
401 ; CHECK: @ %bb.0: @ %entry
402 ; CHECK-NEXT: vcmp.i16 eq, q1, q2
403 ; CHECK-NEXT: vmrs r0, p0
404 ; CHECK-NEXT: vcmp.i16 eq, q0, zr
405 ; CHECK-NEXT: vmrs r1, p0
406 ; CHECK-NEXT: eors r0, r1
407 ; CHECK-NEXT: vmsr p0, r0
408 ; CHECK-NEXT: vpsel q0, q0, q1
411 %c1 = icmp eq <8 x i16> %a, zeroinitializer
412 %c2 = icmp eq <8 x i16> %b, %c
413 %o = xor <8 x i1> %c1, %c2
414 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b
419 define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b) {
420 ; CHECK-LABEL: cmpeqz_v16i1:
421 ; CHECK: @ %bb.0: @ %entry
422 ; CHECK-NEXT: vcmp.i8 eq, q1, zr
423 ; CHECK-NEXT: vmrs r0, p0
424 ; CHECK-NEXT: vcmp.i8 eq, q0, zr
425 ; CHECK-NEXT: vmrs r1, p0
426 ; CHECK-NEXT: eors r0, r1
427 ; CHECK-NEXT: vmsr p0, r0
428 ; CHECK-NEXT: vpsel q0, q0, q1
431 %c1 = icmp eq <16 x i8> %a, zeroinitializer
432 %c2 = icmp eq <16 x i8> %b, zeroinitializer
433 %o = xor <16 x i1> %c1, %c2
434 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b
438 define arm_aapcs_vfpcc <16 x i8> @cmpeq_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
439 ; CHECK-LABEL: cmpeq_v16i1:
440 ; CHECK: @ %bb.0: @ %entry
441 ; CHECK-NEXT: vcmp.i8 eq, q1, q2
442 ; CHECK-NEXT: vmrs r0, p0
443 ; CHECK-NEXT: vcmp.i8 eq, q0, zr
444 ; CHECK-NEXT: vmrs r1, p0
445 ; CHECK-NEXT: eors r0, r1
446 ; CHECK-NEXT: vmsr p0, r0
447 ; CHECK-NEXT: vpsel q0, q0, q1
450 %c1 = icmp eq <16 x i8> %a, zeroinitializer
451 %c2 = icmp eq <16 x i8> %b, %c
452 %o = xor <16 x i1> %c1, %c2
453 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b
458 define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
459 ; CHECK-LABEL: cmpeqz_v2i1:
460 ; CHECK: @ %bb.0: @ %entry
461 ; CHECK-NEXT: vmov r0, r1, d0
462 ; CHECK-NEXT: orrs r0, r1
463 ; CHECK-NEXT: vmov r1, r2, d2
464 ; CHECK-NEXT: orrs r1, r2
465 ; CHECK-NEXT: cset r1, eq
466 ; CHECK-NEXT: cmp r0, #0
468 ; CHECK-NEXT: eoreq r1, r1, #1
469 ; CHECK-NEXT: rsbs r0, r1, #0
470 ; CHECK-NEXT: movs r1, #0
471 ; CHECK-NEXT: bfi r1, r0, #0, #8
472 ; CHECK-NEXT: vmov r0, r2, d1
473 ; CHECK-NEXT: orrs r0, r2
474 ; CHECK-NEXT: vmov r2, r3, d3
475 ; CHECK-NEXT: orrs r2, r3
476 ; CHECK-NEXT: cset r2, eq
477 ; CHECK-NEXT: cmp r0, #0
479 ; CHECK-NEXT: eoreq r2, r2, #1
480 ; CHECK-NEXT: rsbs r0, r2, #0
481 ; CHECK-NEXT: bfi r1, r0, #8, #8
482 ; CHECK-NEXT: vmsr p0, r1
483 ; CHECK-NEXT: vpsel q0, q0, q1
486 %c1 = icmp eq <2 x i64> %a, zeroinitializer
487 %c2 = icmp eq <2 x i64> %b, zeroinitializer
488 %o = xor <2 x i1> %c1, %c2
489 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
493 define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
494 ; CHECK-LABEL: cmpeq_v2i1:
495 ; CHECK: @ %bb.0: @ %entry
496 ; CHECK-NEXT: vmov r0, r1, d4
497 ; CHECK-NEXT: vmov r2, r3, d2
498 ; CHECK-NEXT: eors r1, r3
499 ; CHECK-NEXT: eors r0, r2
500 ; CHECK-NEXT: orrs r0, r1
501 ; CHECK-NEXT: vmov r1, r2, d0
502 ; CHECK-NEXT: cset r0, eq
503 ; CHECK-NEXT: orrs r1, r2
505 ; CHECK-NEXT: eoreq r0, r0, #1
506 ; CHECK-NEXT: rsbs r0, r0, #0
507 ; CHECK-NEXT: movs r1, #0
508 ; CHECK-NEXT: bfi r1, r0, #0, #8
509 ; CHECK-NEXT: vmov r12, r2, d5
510 ; CHECK-NEXT: vmov r3, r0, d3
511 ; CHECK-NEXT: eors r0, r2
512 ; CHECK-NEXT: eor.w r2, r3, r12
513 ; CHECK-NEXT: orrs r0, r2
514 ; CHECK-NEXT: vmov r2, r3, d1
515 ; CHECK-NEXT: cset r0, eq
516 ; CHECK-NEXT: orrs r2, r3
518 ; CHECK-NEXT: eoreq r0, r0, #1
519 ; CHECK-NEXT: rsbs r0, r0, #0
520 ; CHECK-NEXT: bfi r1, r0, #8, #8
521 ; CHECK-NEXT: vmsr p0, r1
522 ; CHECK-NEXT: vpsel q0, q0, q1
525 %c1 = icmp eq <2 x i64> %a, zeroinitializer
526 %c2 = icmp eq <2 x i64> %b, %c
527 %o = xor <2 x i1> %c1, %c2
528 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b