| blob | 16689f1e7ecd175538a3564a783cf7c404c9cdde |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE
3 ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVEFP
5 define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
6 ; CHECK-MVE-LABEL: vcmp_oeq_v4f32:
7 ; CHECK-MVE: @ %bb.0: @ %entry
8 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
9 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
10 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
11 ; CHECK-MVE-NEXT: cset r0, eq
12 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
13 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
14 ; CHECK-MVE-NEXT: cset r1, eq
15 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
16 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
17 ; CHECK-MVE-NEXT: cset r2, eq
18 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
19 ; CHECK-MVE-NEXT: cset r3, eq
20 ; CHECK-MVE-NEXT: cmp r2, #0
21 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
22 ; CHECK-MVE-NEXT: cmp r3, #0
23 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
24 ; CHECK-MVE-NEXT: cmp r0, #0
25 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
26 ; CHECK-MVE-NEXT: cmp r1, #0
27 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
28 ; CHECK-MVE-NEXT: bx lr
29 ;
30 ; CHECK-MVEFP-LABEL: vcmp_oeq_v4f32:
31 ; CHECK-MVEFP: @ %bb.0: @ %entry
32 ; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, zr
33 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
34 ; CHECK-MVEFP-NEXT: bx lr
35 entry:
36 %c = fcmp oeq <4 x float> %src, zeroinitializer
37 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
38 ret <4 x float> %s
39 }
41 define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
42 ; CHECK-MVE-LABEL: vcmp_one_v4f32:
43 ; CHECK-MVE: @ %bb.0: @ %entry
44 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
45 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
46 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
47 ; CHECK-MVE-NEXT: cset r0, mi
48 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
49 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
50 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
51 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
52 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
53 ; CHECK-MVE-NEXT: cset r1, mi
54 ; CHECK-MVE-NEXT: csinc r1, r1, zr, le
55 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
56 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
57 ; CHECK-MVE-NEXT: cset r2, mi
58 ; CHECK-MVE-NEXT: csinc r2, r2, zr, le
59 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
60 ; CHECK-MVE-NEXT: cset r3, mi
61 ; CHECK-MVE-NEXT: csinc r3, r3, zr, le
62 ; CHECK-MVE-NEXT: cmp r2, #0
63 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
64 ; CHECK-MVE-NEXT: cmp r3, #0
65 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
66 ; CHECK-MVE-NEXT: cmp r0, #0
67 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
68 ; CHECK-MVE-NEXT: cmp r1, #0
69 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
70 ; CHECK-MVE-NEXT: bx lr
71 ;
72 ; CHECK-MVEFP-LABEL: vcmp_one_v4f32:
73 ; CHECK-MVEFP: @ %bb.0: @ %entry
74 ; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr
75 ; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, zr
76 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
77 ; CHECK-MVEFP-NEXT: bx lr
78 entry:
79 %c = fcmp one <4 x float> %src, zeroinitializer
80 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
81 ret <4 x float> %s
82 }
84 define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
85 ; CHECK-MVE-LABEL: vcmp_ogt_v4f32:
86 ; CHECK-MVE: @ %bb.0: @ %entry
87 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
88 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
89 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
90 ; CHECK-MVE-NEXT: cset r0, gt
91 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
92 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
93 ; CHECK-MVE-NEXT: cset r1, gt
94 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
95 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
96 ; CHECK-MVE-NEXT: cset r2, gt
97 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
98 ; CHECK-MVE-NEXT: cset r3, gt
99 ; CHECK-MVE-NEXT: cmp r2, #0
100 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
101 ; CHECK-MVE-NEXT: cmp r3, #0
102 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
103 ; CHECK-MVE-NEXT: cmp r0, #0
104 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
105 ; CHECK-MVE-NEXT: cmp r1, #0
106 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
107 ; CHECK-MVE-NEXT: bx lr
108 ;
109 ; CHECK-MVEFP-LABEL: vcmp_ogt_v4f32:
110 ; CHECK-MVEFP: @ %bb.0: @ %entry
111 ; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr
112 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
113 ; CHECK-MVEFP-NEXT: bx lr
114 entry:
115 %c = fcmp ogt <4 x float> %src, zeroinitializer
116 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
117 ret <4 x float> %s
118 }
120 define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
121 ; CHECK-MVE-LABEL: vcmp_oge_v4f32:
122 ; CHECK-MVE: @ %bb.0: @ %entry
123 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
124 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
125 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
126 ; CHECK-MVE-NEXT: cset r0, ge
127 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
128 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
129 ; CHECK-MVE-NEXT: cset r1, ge
130 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
131 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
132 ; CHECK-MVE-NEXT: cset r2, ge
133 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
134 ; CHECK-MVE-NEXT: cset r3, ge
135 ; CHECK-MVE-NEXT: cmp r2, #0
136 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
137 ; CHECK-MVE-NEXT: cmp r3, #0
138 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
139 ; CHECK-MVE-NEXT: cmp r0, #0
140 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
141 ; CHECK-MVE-NEXT: cmp r1, #0
142 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
143 ; CHECK-MVE-NEXT: bx lr
144 ;
145 ; CHECK-MVEFP-LABEL: vcmp_oge_v4f32:
146 ; CHECK-MVEFP: @ %bb.0: @ %entry
147 ; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr
148 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
149 ; CHECK-MVEFP-NEXT: bx lr
150 entry:
151 %c = fcmp oge <4 x float> %src, zeroinitializer
152 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
153 ret <4 x float> %s
154 }
156 define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
157 ; CHECK-MVE-LABEL: vcmp_olt_v4f32:
158 ; CHECK-MVE: @ %bb.0: @ %entry
159 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
160 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
161 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
162 ; CHECK-MVE-NEXT: cset r0, mi
163 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
164 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
165 ; CHECK-MVE-NEXT: cset r1, mi
166 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
167 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
168 ; CHECK-MVE-NEXT: cset r2, mi
169 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
170 ; CHECK-MVE-NEXT: cset r3, mi
171 ; CHECK-MVE-NEXT: cmp r2, #0
172 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
173 ; CHECK-MVE-NEXT: cmp r3, #0
174 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
175 ; CHECK-MVE-NEXT: cmp r0, #0
176 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
177 ; CHECK-MVE-NEXT: cmp r1, #0
178 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
179 ; CHECK-MVE-NEXT: bx lr
180 ;
181 ; CHECK-MVEFP-LABEL: vcmp_olt_v4f32:
182 ; CHECK-MVEFP: @ %bb.0: @ %entry
183 ; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr
184 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
185 ; CHECK-MVEFP-NEXT: bx lr
186 entry:
187 %c = fcmp olt <4 x float> %src, zeroinitializer
188 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
189 ret <4 x float> %s
190 }
192 define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
193 ; CHECK-MVE-LABEL: vcmp_ole_v4f32:
194 ; CHECK-MVE: @ %bb.0: @ %entry
195 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
196 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
197 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
198 ; CHECK-MVE-NEXT: cset r0, ls
199 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
200 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
201 ; CHECK-MVE-NEXT: cset r1, ls
202 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
203 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
204 ; CHECK-MVE-NEXT: cset r2, ls
205 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
206 ; CHECK-MVE-NEXT: cset r3, ls
207 ; CHECK-MVE-NEXT: cmp r2, #0
208 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
209 ; CHECK-MVE-NEXT: cmp r3, #0
210 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
211 ; CHECK-MVE-NEXT: cmp r0, #0
212 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
213 ; CHECK-MVE-NEXT: cmp r1, #0
214 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
215 ; CHECK-MVE-NEXT: bx lr
216 ;
217 ; CHECK-MVEFP-LABEL: vcmp_ole_v4f32:
218 ; CHECK-MVEFP: @ %bb.0: @ %entry
219 ; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr
220 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
221 ; CHECK-MVEFP-NEXT: bx lr
222 entry:
223 %c = fcmp ole <4 x float> %src, zeroinitializer
224 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
225 ret <4 x float> %s
226 }
228 define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
229 ; CHECK-MVE-LABEL: vcmp_ueq_v4f32:
230 ; CHECK-MVE: @ %bb.0: @ %entry
231 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
232 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
233 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
234 ; CHECK-MVE-NEXT: cset r0, eq
235 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
236 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
237 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
238 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
239 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
240 ; CHECK-MVE-NEXT: cset r1, eq
241 ; CHECK-MVE-NEXT: csinc r1, r1, zr, vc
242 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
243 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
244 ; CHECK-MVE-NEXT: cset r2, eq
245 ; CHECK-MVE-NEXT: csinc r2, r2, zr, vc
246 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
247 ; CHECK-MVE-NEXT: cset r3, eq
248 ; CHECK-MVE-NEXT: csinc r3, r3, zr, vc
249 ; CHECK-MVE-NEXT: cmp r2, #0
250 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
251 ; CHECK-MVE-NEXT: cmp r3, #0
252 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
253 ; CHECK-MVE-NEXT: cmp r0, #0
254 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
255 ; CHECK-MVE-NEXT: cmp r1, #0
256 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
257 ; CHECK-MVE-NEXT: bx lr
258 ;
259 ; CHECK-MVEFP-LABEL: vcmp_ueq_v4f32:
260 ; CHECK-MVEFP: @ %bb.0: @ %entry
261 ; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr
262 ; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, zr
263 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
264 ; CHECK-MVEFP-NEXT: bx lr
265 entry:
266 %c = fcmp ueq <4 x float> %src, zeroinitializer
267 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
268 ret <4 x float> %s
269 }
271 define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
272 ; CHECK-MVE-LABEL: vcmp_une_v4f32:
273 ; CHECK-MVE: @ %bb.0: @ %entry
274 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
275 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
276 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
277 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
278 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
279 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
280 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
281 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
282 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
283 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
284 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
285 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
286 ; CHECK-MVE-NEXT: bx lr
287 ;
288 ; CHECK-MVEFP-LABEL: vcmp_une_v4f32:
289 ; CHECK-MVEFP: @ %bb.0: @ %entry
290 ; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, zr
291 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
292 ; CHECK-MVEFP-NEXT: bx lr
293 entry:
294 %c = fcmp une <4 x float> %src, zeroinitializer
295 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
296 ret <4 x float> %s
297 }
299 define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
300 ; CHECK-MVE-LABEL: vcmp_ugt_v4f32:
301 ; CHECK-MVE: @ %bb.0: @ %entry
302 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
303 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
304 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
305 ; CHECK-MVE-NEXT: cset r0, hi
306 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
307 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
308 ; CHECK-MVE-NEXT: cset r1, hi
309 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
310 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
311 ; CHECK-MVE-NEXT: cset r2, hi
312 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
313 ; CHECK-MVE-NEXT: cset r3, hi
314 ; CHECK-MVE-NEXT: cmp r2, #0
315 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
316 ; CHECK-MVE-NEXT: cmp r3, #0
317 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
318 ; CHECK-MVE-NEXT: cmp r0, #0
319 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
320 ; CHECK-MVE-NEXT: cmp r1, #0
321 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
322 ; CHECK-MVE-NEXT: bx lr
323 ;
324 ; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32:
325 ; CHECK-MVEFP: @ %bb.0: @ %entry
326 ; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr
327 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
328 ; CHECK-MVEFP-NEXT: bx lr
329 entry:
330 %c = fcmp ugt <4 x float> %src, zeroinitializer
331 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
332 ret <4 x float> %s
333 }
335 define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
336 ; CHECK-MVE-LABEL: vcmp_uge_v4f32:
337 ; CHECK-MVE: @ %bb.0: @ %entry
338 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
339 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
340 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
341 ; CHECK-MVE-NEXT: cset r0, pl
342 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
343 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
344 ; CHECK-MVE-NEXT: cset r1, pl
345 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
346 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
347 ; CHECK-MVE-NEXT: cset r2, pl
348 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
349 ; CHECK-MVE-NEXT: cset r3, pl
350 ; CHECK-MVE-NEXT: cmp r2, #0
351 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
352 ; CHECK-MVE-NEXT: cmp r3, #0
353 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
354 ; CHECK-MVE-NEXT: cmp r0, #0
355 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
356 ; CHECK-MVE-NEXT: cmp r1, #0
357 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
358 ; CHECK-MVE-NEXT: bx lr
359 ;
360 ; CHECK-MVEFP-LABEL: vcmp_uge_v4f32:
361 ; CHECK-MVEFP: @ %bb.0: @ %entry
362 ; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr
363 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
364 ; CHECK-MVEFP-NEXT: bx lr
365 entry:
366 %c = fcmp uge <4 x float> %src, zeroinitializer
367 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
368 ret <4 x float> %s
369 }
371 define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
372 ; CHECK-MVE-LABEL: vcmp_ult_v4f32:
373 ; CHECK-MVE: @ %bb.0: @ %entry
374 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
375 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
376 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
377 ; CHECK-MVE-NEXT: cset r0, lt
378 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
379 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
380 ; CHECK-MVE-NEXT: cset r1, lt
381 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
382 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
383 ; CHECK-MVE-NEXT: cset r2, lt
384 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
385 ; CHECK-MVE-NEXT: cset r3, lt
386 ; CHECK-MVE-NEXT: cmp r2, #0
387 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
388 ; CHECK-MVE-NEXT: cmp r3, #0
389 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
390 ; CHECK-MVE-NEXT: cmp r0, #0
391 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
392 ; CHECK-MVE-NEXT: cmp r1, #0
393 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
394 ; CHECK-MVE-NEXT: bx lr
395 ;
396 ; CHECK-MVEFP-LABEL: vcmp_ult_v4f32:
397 ; CHECK-MVEFP: @ %bb.0: @ %entry
398 ; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr
399 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
400 ; CHECK-MVEFP-NEXT: bx lr
401 entry:
402 %c = fcmp ult <4 x float> %src, zeroinitializer
403 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
404 ret <4 x float> %s
405 }
407 define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
408 ; CHECK-MVE-LABEL: vcmp_ule_v4f32:
409 ; CHECK-MVE: @ %bb.0: @ %entry
410 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
411 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
412 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
413 ; CHECK-MVE-NEXT: cset r0, le
414 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
415 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
416 ; CHECK-MVE-NEXT: cset r1, le
417 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
418 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
419 ; CHECK-MVE-NEXT: cset r2, le
420 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
421 ; CHECK-MVE-NEXT: cset r3, le
422 ; CHECK-MVE-NEXT: cmp r2, #0
423 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
424 ; CHECK-MVE-NEXT: cmp r3, #0
425 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
426 ; CHECK-MVE-NEXT: cmp r0, #0
427 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
428 ; CHECK-MVE-NEXT: cmp r1, #0
429 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
430 ; CHECK-MVE-NEXT: bx lr
431 ;
432 ; CHECK-MVEFP-LABEL: vcmp_ule_v4f32:
433 ; CHECK-MVEFP: @ %bb.0: @ %entry
434 ; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr
435 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
436 ; CHECK-MVEFP-NEXT: bx lr
437 entry:
438 %c = fcmp ule <4 x float> %src, zeroinitializer
439 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
440 ret <4 x float> %s
441 }
443 define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
444 ; CHECK-MVE-LABEL: vcmp_ord_v4f32:
445 ; CHECK-MVE: @ %bb.0: @ %entry
446 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
447 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
448 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
449 ; CHECK-MVE-NEXT: cset r0, vc
450 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
451 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
452 ; CHECK-MVE-NEXT: cset r1, vc
453 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
454 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
455 ; CHECK-MVE-NEXT: cset r2, vc
456 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
457 ; CHECK-MVE-NEXT: cset r3, vc
458 ; CHECK-MVE-NEXT: cmp r2, #0
459 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
460 ; CHECK-MVE-NEXT: cmp r3, #0
461 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
462 ; CHECK-MVE-NEXT: cmp r0, #0
463 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
464 ; CHECK-MVE-NEXT: cmp r1, #0
465 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
466 ; CHECK-MVE-NEXT: bx lr
467 ;
468 ; CHECK-MVEFP-LABEL: vcmp_ord_v4f32:
469 ; CHECK-MVEFP: @ %bb.0: @ %entry
470 ; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr
471 ; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, zr
472 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
473 ; CHECK-MVEFP-NEXT: bx lr
474 entry:
475 %c = fcmp ord <4 x float> %src, zeroinitializer
476 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
477 ret <4 x float> %s
478 }
480 define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
481 ; CHECK-MVE-LABEL: vcmp_uno_v4f32:
482 ; CHECK-MVE: @ %bb.0: @ %entry
483 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
484 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
485 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
486 ; CHECK-MVE-NEXT: cset r0, vs
487 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
488 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
489 ; CHECK-MVE-NEXT: cset r1, vs
490 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
491 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
492 ; CHECK-MVE-NEXT: cset r2, vs
493 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
494 ; CHECK-MVE-NEXT: cset r3, vs
495 ; CHECK-MVE-NEXT: cmp r2, #0
496 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
497 ; CHECK-MVE-NEXT: cmp r3, #0
498 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
499 ; CHECK-MVE-NEXT: cmp r0, #0
500 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
501 ; CHECK-MVE-NEXT: cmp r1, #0
502 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
503 ; CHECK-MVE-NEXT: bx lr
504 ;
505 ; CHECK-MVEFP-LABEL: vcmp_uno_v4f32:
506 ; CHECK-MVEFP: @ %bb.0: @ %entry
507 ; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr
508 ; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, zr
509 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
510 ; CHECK-MVEFP-NEXT: bx lr
511 entry:
512 %c = fcmp uno <4 x float> %src, zeroinitializer
513 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
514 ret <4 x float> %s
515 }
519 define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
520 ; CHECK-MVE-LABEL: vcmp_oeq_v8f16:
521 ; CHECK-MVE: @ %bb.0: @ %entry
522 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
523 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
524 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
525 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
526 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
527 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
528 ; CHECK-MVE-NEXT: cset r0, eq
529 ; CHECK-MVE-NEXT: cmp r0, #0
530 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
531 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
532 ; CHECK-MVE-NEXT: cset r0, eq
533 ; CHECK-MVE-NEXT: cmp r0, #0
534 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
535 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
536 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
537 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
538 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
539 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
540 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
541 ; CHECK-MVE-NEXT: vins.f16 s0, s12
542 ; CHECK-MVE-NEXT: cset r0, eq
543 ; CHECK-MVE-NEXT: cmp r0, #0
544 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
545 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
546 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
547 ; CHECK-MVE-NEXT: cset r0, eq
548 ; CHECK-MVE-NEXT: cmp r0, #0
549 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
550 ; CHECK-MVE-NEXT: vins.f16 s1, s4
551 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
552 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
553 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
554 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
555 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
556 ; CHECK-MVE-NEXT: cset r0, eq
557 ; CHECK-MVE-NEXT: cmp r0, #0
558 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
559 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
560 ; CHECK-MVE-NEXT: cset r0, eq
561 ; CHECK-MVE-NEXT: cmp r0, #0
562 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
563 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
564 ; CHECK-MVE-NEXT: vins.f16 s2, s4
565 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
566 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
567 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
568 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
569 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
570 ; CHECK-MVE-NEXT: cset r0, eq
571 ; CHECK-MVE-NEXT: cmp r0, #0
572 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
573 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
574 ; CHECK-MVE-NEXT: cset r0, eq
575 ; CHECK-MVE-NEXT: cmp r0, #0
576 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
577 ; CHECK-MVE-NEXT: vins.f16 s3, s4
578 ; CHECK-MVE-NEXT: bx lr
579 ;
580 ; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16:
581 ; CHECK-MVEFP: @ %bb.0: @ %entry
582 ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr
583 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
584 ; CHECK-MVEFP-NEXT: bx lr
585 entry:
586 %c = fcmp oeq <8 x half> %src, zeroinitializer
587 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
588 ret <8 x half> %s
589 }
591 define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
592 ; CHECK-MVE-LABEL: vcmp_one_v8f16:
593 ; CHECK-MVE: @ %bb.0: @ %entry
594 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
595 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
596 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
597 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
598 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
599 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
600 ; CHECK-MVE-NEXT: cset r0, mi
601 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
602 ; CHECK-MVE-NEXT: cmp r0, #0
603 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
604 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
605 ; CHECK-MVE-NEXT: cset r0, mi
606 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
607 ; CHECK-MVE-NEXT: cmp r0, #0
608 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
609 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
610 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
611 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
612 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
613 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
614 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
615 ; CHECK-MVE-NEXT: vins.f16 s0, s12
616 ; CHECK-MVE-NEXT: cset r0, mi
617 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
618 ; CHECK-MVE-NEXT: cmp r0, #0
619 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
620 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
621 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
622 ; CHECK-MVE-NEXT: cset r0, mi
623 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
624 ; CHECK-MVE-NEXT: cmp r0, #0
625 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
626 ; CHECK-MVE-NEXT: vins.f16 s1, s4
627 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
628 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
629 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
630 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
631 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
632 ; CHECK-MVE-NEXT: cset r0, mi
633 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
634 ; CHECK-MVE-NEXT: cmp r0, #0
635 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
636 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
637 ; CHECK-MVE-NEXT: cset r0, mi
638 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
639 ; CHECK-MVE-NEXT: cmp r0, #0
640 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
641 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
642 ; CHECK-MVE-NEXT: vins.f16 s2, s4
643 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
644 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
645 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
646 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
647 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
648 ; CHECK-MVE-NEXT: cset r0, mi
649 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
650 ; CHECK-MVE-NEXT: cmp r0, #0
651 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
652 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
653 ; CHECK-MVE-NEXT: cset r0, mi
654 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
655 ; CHECK-MVE-NEXT: cmp r0, #0
656 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
657 ; CHECK-MVE-NEXT: vins.f16 s3, s4
658 ; CHECK-MVE-NEXT: bx lr
659 ;
660 ; CHECK-MVEFP-LABEL: vcmp_one_v8f16:
661 ; CHECK-MVEFP: @ %bb.0: @ %entry
662 ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
663 ; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr
664 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
665 ; CHECK-MVEFP-NEXT: bx lr
666 entry:
667 %c = fcmp one <8 x half> %src, zeroinitializer
668 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
669 ret <8 x half> %s
670 }
672 define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
673 ; CHECK-MVE-LABEL: vcmp_ogt_v8f16:
674 ; CHECK-MVE: @ %bb.0: @ %entry
675 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
676 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
677 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
678 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
679 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
680 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
681 ; CHECK-MVE-NEXT: cset r0, gt
682 ; CHECK-MVE-NEXT: cmp r0, #0
683 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
684 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
685 ; CHECK-MVE-NEXT: cset r0, gt
686 ; CHECK-MVE-NEXT: cmp r0, #0
687 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
688 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
689 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
690 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
691 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
692 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
693 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
694 ; CHECK-MVE-NEXT: vins.f16 s0, s12
695 ; CHECK-MVE-NEXT: cset r0, gt
696 ; CHECK-MVE-NEXT: cmp r0, #0
697 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
698 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
699 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
700 ; CHECK-MVE-NEXT: cset r0, gt
701 ; CHECK-MVE-NEXT: cmp r0, #0
702 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
703 ; CHECK-MVE-NEXT: vins.f16 s1, s4
704 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
705 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
706 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
707 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
708 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
709 ; CHECK-MVE-NEXT: cset r0, gt
710 ; CHECK-MVE-NEXT: cmp r0, #0
711 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
712 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
713 ; CHECK-MVE-NEXT: cset r0, gt
714 ; CHECK-MVE-NEXT: cmp r0, #0
715 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
716 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
717 ; CHECK-MVE-NEXT: vins.f16 s2, s4
718 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
719 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
720 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
721 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
722 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
723 ; CHECK-MVE-NEXT: cset r0, gt
724 ; CHECK-MVE-NEXT: cmp r0, #0
725 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
726 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
727 ; CHECK-MVE-NEXT: cset r0, gt
728 ; CHECK-MVE-NEXT: cmp r0, #0
729 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
730 ; CHECK-MVE-NEXT: vins.f16 s3, s4
731 ; CHECK-MVE-NEXT: bx lr
732 ;
733 ; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16:
734 ; CHECK-MVEFP: @ %bb.0: @ %entry
735 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
736 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
737 ; CHECK-MVEFP-NEXT: bx lr
738 entry:
739 %c = fcmp ogt <8 x half> %src, zeroinitializer
740 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
741 ret <8 x half> %s
742 }
744 define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
745 ; CHECK-MVE-LABEL: vcmp_oge_v8f16:
746 ; CHECK-MVE: @ %bb.0: @ %entry
747 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
748 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
749 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
750 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
751 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
752 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
753 ; CHECK-MVE-NEXT: cset r0, ge
754 ; CHECK-MVE-NEXT: cmp r0, #0
755 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
756 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
757 ; CHECK-MVE-NEXT: cset r0, ge
758 ; CHECK-MVE-NEXT: cmp r0, #0
759 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
760 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
761 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
762 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
763 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
764 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
765 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
766 ; CHECK-MVE-NEXT: vins.f16 s0, s12
767 ; CHECK-MVE-NEXT: cset r0, ge
768 ; CHECK-MVE-NEXT: cmp r0, #0
769 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
770 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
771 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
772 ; CHECK-MVE-NEXT: cset r0, ge
773 ; CHECK-MVE-NEXT: cmp r0, #0
774 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
775 ; CHECK-MVE-NEXT: vins.f16 s1, s4
776 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
777 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
778 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
779 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
780 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
781 ; CHECK-MVE-NEXT: cset r0, ge
782 ; CHECK-MVE-NEXT: cmp r0, #0
783 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
784 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
785 ; CHECK-MVE-NEXT: cset r0, ge
786 ; CHECK-MVE-NEXT: cmp r0, #0
787 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
788 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
789 ; CHECK-MVE-NEXT: vins.f16 s2, s4
790 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
791 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
792 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
793 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
794 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
795 ; CHECK-MVE-NEXT: cset r0, ge
796 ; CHECK-MVE-NEXT: cmp r0, #0
797 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
798 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
799 ; CHECK-MVE-NEXT: cset r0, ge
800 ; CHECK-MVE-NEXT: cmp r0, #0
801 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
802 ; CHECK-MVE-NEXT: vins.f16 s3, s4
803 ; CHECK-MVE-NEXT: bx lr
804 ;
805 ; CHECK-MVEFP-LABEL: vcmp_oge_v8f16:
806 ; CHECK-MVEFP: @ %bb.0: @ %entry
807 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
808 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
809 ; CHECK-MVEFP-NEXT: bx lr
810 entry:
811 %c = fcmp oge <8 x half> %src, zeroinitializer
812 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
813 ret <8 x half> %s
814 }
816 define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
817 ; CHECK-MVE-LABEL: vcmp_olt_v8f16:
818 ; CHECK-MVE: @ %bb.0: @ %entry
819 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
820 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
821 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
822 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
823 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
824 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
825 ; CHECK-MVE-NEXT: cset r0, mi
826 ; CHECK-MVE-NEXT: cmp r0, #0
827 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
828 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
829 ; CHECK-MVE-NEXT: cset r0, mi
830 ; CHECK-MVE-NEXT: cmp r0, #0
831 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
832 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
833 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
834 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
835 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
836 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
837 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
838 ; CHECK-MVE-NEXT: vins.f16 s0, s12
839 ; CHECK-MVE-NEXT: cset r0, mi
840 ; CHECK-MVE-NEXT: cmp r0, #0
841 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
842 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
843 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
844 ; CHECK-MVE-NEXT: cset r0, mi
845 ; CHECK-MVE-NEXT: cmp r0, #0
846 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
847 ; CHECK-MVE-NEXT: vins.f16 s1, s4
848 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
849 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
850 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
851 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
852 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
853 ; CHECK-MVE-NEXT: cset r0, mi
854 ; CHECK-MVE-NEXT: cmp r0, #0
855 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
856 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
857 ; CHECK-MVE-NEXT: cset r0, mi
858 ; CHECK-MVE-NEXT: cmp r0, #0
859 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
860 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
861 ; CHECK-MVE-NEXT: vins.f16 s2, s4
862 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
863 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
864 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
865 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
866 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
867 ; CHECK-MVE-NEXT: cset r0, mi
868 ; CHECK-MVE-NEXT: cmp r0, #0
869 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
870 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
871 ; CHECK-MVE-NEXT: cset r0, mi
872 ; CHECK-MVE-NEXT: cmp r0, #0
873 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
874 ; CHECK-MVE-NEXT: vins.f16 s3, s4
875 ; CHECK-MVE-NEXT: bx lr
876 ;
877 ; CHECK-MVEFP-LABEL: vcmp_olt_v8f16:
878 ; CHECK-MVEFP: @ %bb.0: @ %entry
879 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
880 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
881 ; CHECK-MVEFP-NEXT: bx lr
882 entry:
883 %c = fcmp olt <8 x half> %src, zeroinitializer
884 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
885 ret <8 x half> %s
886 }
888 define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
889 ; CHECK-MVE-LABEL: vcmp_ole_v8f16:
890 ; CHECK-MVE: @ %bb.0: @ %entry
891 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
892 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
893 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
894 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
895 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
896 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
897 ; CHECK-MVE-NEXT: cset r0, ls
898 ; CHECK-MVE-NEXT: cmp r0, #0
899 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
900 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
901 ; CHECK-MVE-NEXT: cset r0, ls
902 ; CHECK-MVE-NEXT: cmp r0, #0
903 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
904 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
905 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
906 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
907 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
908 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
909 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
910 ; CHECK-MVE-NEXT: vins.f16 s0, s12
911 ; CHECK-MVE-NEXT: cset r0, ls
912 ; CHECK-MVE-NEXT: cmp r0, #0
913 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
914 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
915 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
916 ; CHECK-MVE-NEXT: cset r0, ls
917 ; CHECK-MVE-NEXT: cmp r0, #0
918 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
919 ; CHECK-MVE-NEXT: vins.f16 s1, s4
920 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
921 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
922 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
923 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
924 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
925 ; CHECK-MVE-NEXT: cset r0, ls
926 ; CHECK-MVE-NEXT: cmp r0, #0
927 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
928 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
929 ; CHECK-MVE-NEXT: cset r0, ls
930 ; CHECK-MVE-NEXT: cmp r0, #0
931 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
932 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
933 ; CHECK-MVE-NEXT: vins.f16 s2, s4
934 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
935 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
936 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
937 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
938 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
939 ; CHECK-MVE-NEXT: cset r0, ls
940 ; CHECK-MVE-NEXT: cmp r0, #0
941 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
942 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
943 ; CHECK-MVE-NEXT: cset r0, ls
944 ; CHECK-MVE-NEXT: cmp r0, #0
945 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
946 ; CHECK-MVE-NEXT: vins.f16 s3, s4
947 ; CHECK-MVE-NEXT: bx lr
948 ;
949 ; CHECK-MVEFP-LABEL: vcmp_ole_v8f16:
950 ; CHECK-MVEFP: @ %bb.0: @ %entry
951 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
952 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
953 ; CHECK-MVEFP-NEXT: bx lr
954 entry:
955 %c = fcmp ole <8 x half> %src, zeroinitializer
956 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
957 ret <8 x half> %s
958 }
960 define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
961 ; CHECK-MVE-LABEL: vcmp_ueq_v8f16:
962 ; CHECK-MVE: @ %bb.0: @ %entry
963 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
964 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
965 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
966 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
967 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
968 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
969 ; CHECK-MVE-NEXT: cset r0, eq
970 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
971 ; CHECK-MVE-NEXT: cmp r0, #0
972 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
973 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
974 ; CHECK-MVE-NEXT: cset r0, eq
975 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
976 ; CHECK-MVE-NEXT: cmp r0, #0
977 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
978 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
979 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
980 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
981 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
982 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
983 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
984 ; CHECK-MVE-NEXT: vins.f16 s0, s12
985 ; CHECK-MVE-NEXT: cset r0, eq
986 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
987 ; CHECK-MVE-NEXT: cmp r0, #0
988 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
989 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
990 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
991 ; CHECK-MVE-NEXT: cset r0, eq
992 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
993 ; CHECK-MVE-NEXT: cmp r0, #0
994 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
995 ; CHECK-MVE-NEXT: vins.f16 s1, s4
996 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
997 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
998 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
999 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1000 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
1001 ; CHECK-MVE-NEXT: cset r0, eq
1002 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
1003 ; CHECK-MVE-NEXT: cmp r0, #0
1004 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
1005 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1006 ; CHECK-MVE-NEXT: cset r0, eq
1007 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
1008 ; CHECK-MVE-NEXT: cmp r0, #0
1009 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
1010 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
1011 ; CHECK-MVE-NEXT: vins.f16 s2, s4
1012 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
1013 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
1014 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
1015 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1016 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
1017 ; CHECK-MVE-NEXT: cset r0, eq
1018 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
1019 ; CHECK-MVE-NEXT: cmp r0, #0
1020 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
1021 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1022 ; CHECK-MVE-NEXT: cset r0, eq
1023 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
1024 ; CHECK-MVE-NEXT: cmp r0, #0
1025 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
1026 ; CHECK-MVE-NEXT: vins.f16 s3, s4
1027 ; CHECK-MVE-NEXT: bx lr
1028 ;
1029 ; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16:
1030 ; CHECK-MVEFP: @ %bb.0: @ %entry
1031 ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
1032 ; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr
1033 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1034 ; CHECK-MVEFP-NEXT: bx lr
1035 entry:
1036 %c = fcmp ueq <8 x half> %src, zeroinitializer
1037 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
1038 ret <8 x half> %s
1039 }
1041 define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
1042 ; CHECK-MVE-LABEL: vcmp_une_v8f16:
1043 ; CHECK-MVE: @ %bb.0: @ %entry
1044 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
1045 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
1046 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
1047 ; CHECK-MVE-NEXT: vmovx.f16 s13, s8
1048 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1049 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
1050 ; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s14
1051 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1052 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
1053 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
1054 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
1055 ; CHECK-MVE-NEXT: vins.f16 s0, s12
1056 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1057 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
1058 ; CHECK-MVE-NEXT: vmovx.f16 s12, s9
1059 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
1060 ; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s8
1061 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1062 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
1063 ; CHECK-MVE-NEXT: vmovx.f16 s12, s10
1064 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
1065 ; CHECK-MVE-NEXT: vins.f16 s1, s4
1066 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
1067 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
1068 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1069 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
1070 ; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s8
1071 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1072 ; CHECK-MVE-NEXT: vmovx.f16 s8, s11
1073 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
1074 ; CHECK-MVE-NEXT: vmovx.f16 s6, s7
1075 ; CHECK-MVE-NEXT: vins.f16 s2, s4
1076 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
1077 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
1078 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1079 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
1080 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s6
1081 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1082 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
1083 ; CHECK-MVE-NEXT: vins.f16 s3, s4
1084 ; CHECK-MVE-NEXT: bx lr
1085 ;
1086 ; CHECK-MVEFP-LABEL: vcmp_une_v8f16:
1087 ; CHECK-MVEFP: @ %bb.0: @ %entry
1088 ; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr
1089 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1090 ; CHECK-MVEFP-NEXT: bx lr
1091 entry:
1092 %c = fcmp une <8 x half> %src, zeroinitializer
1093 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
1094 ret <8 x half> %s
1095 }
1097 define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
1098 ; CHECK-MVE-LABEL: vcmp_ugt_v8f16:
1099 ; CHECK-MVE: @ %bb.0: @ %entry
1100 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
1101 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
1102 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
1103 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
1104 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1105 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
1106 ; CHECK-MVE-NEXT: cset r0, hi
1107 ; CHECK-MVE-NEXT: cmp r0, #0
1108 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
1109 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1110 ; CHECK-MVE-NEXT: cset r0, hi
1111 ; CHECK-MVE-NEXT: cmp r0, #0
1112 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
1113 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
1114 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
1115 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
1116 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1117 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
1118 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
1119 ; CHECK-MVE-NEXT: vins.f16 s0, s12
1120 ; CHECK-MVE-NEXT: cset r0, hi
1121 ; CHECK-MVE-NEXT: cmp r0, #0
1122 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
1123 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1124 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
1125 ; CHECK-MVE-NEXT: cset r0, hi
1126 ; CHECK-MVE-NEXT: cmp r0, #0
1127 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
1128 ; CHECK-MVE-NEXT: vins.f16 s1, s4
1129 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
1130 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
1131 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
1132 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1133 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
1134 ; CHECK-MVE-NEXT: cset r0, hi
1135 ; CHECK-MVE-NEXT: cmp r0, #0
1136 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
1137 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1138 ; CHECK-MVE-NEXT: cset r0, hi
1139 ; CHECK-MVE-NEXT: cmp r0, #0
1140 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
1141 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
1142 ; CHECK-MVE-NEXT: vins.f16 s2, s4
1143 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
1144 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
1145 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
1146 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1147 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
1148 ; CHECK-MVE-NEXT: cset r0, hi
1149 ; CHECK-MVE-NEXT: cmp r0, #0
1150 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
1151 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1152 ; CHECK-MVE-NEXT: cset r0, hi
1153 ; CHECK-MVE-NEXT: cmp r0, #0
1154 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
1155 ; CHECK-MVE-NEXT: vins.f16 s3, s4
1156 ; CHECK-MVE-NEXT: bx lr
1157 ;
1158 ; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16:
1159 ; CHECK-MVEFP: @ %bb.0: @ %entry
1160 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
1161 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1162 ; CHECK-MVEFP-NEXT: bx lr
1163 entry:
1164 %c = fcmp ugt <8 x half> %src, zeroinitializer
1165 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
1166 ret <8 x half> %s
1167 }
1169 define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
1170 ; CHECK-MVE-LABEL: vcmp_uge_v8f16:
1171 ; CHECK-MVE: @ %bb.0: @ %entry
1172 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
1173 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
1174 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
1175 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
1176 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1177 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
1178 ; CHECK-MVE-NEXT: cset r0, pl
1179 ; CHECK-MVE-NEXT: cmp r0, #0
1180 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
1181 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1182 ; CHECK-MVE-NEXT: cset r0, pl
1183 ; CHECK-MVE-NEXT: cmp r0, #0
1184 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
1185 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
1186 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
1187 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
1188 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1189 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
1190 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
1191 ; CHECK-MVE-NEXT: vins.f16 s0, s12
1192 ; CHECK-MVE-NEXT: cset r0, pl
1193 ; CHECK-MVE-NEXT: cmp r0, #0
1194 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
1195 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1196 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
1197 ; CHECK-MVE-NEXT: cset r0, pl
1198 ; CHECK-MVE-NEXT: cmp r0, #0
1199 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
1200 ; CHECK-MVE-NEXT: vins.f16 s1, s4
1201 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
1202 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
1203 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
1204 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1205 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
1206 ; CHECK-MVE-NEXT: cset r0, pl
1207 ; CHECK-MVE-NEXT: cmp r0, #0
1208 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
1209 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1210 ; CHECK-MVE-NEXT: cset r0, pl
1211 ; CHECK-MVE-NEXT: cmp r0, #0
1212 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
1213 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
1214 ; CHECK-MVE-NEXT: vins.f16 s2, s4
1215 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
1216 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
1217 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
1218 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1219 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
1220 ; CHECK-MVE-NEXT: cset r0, pl
1221 ; CHECK-MVE-NEXT: cmp r0, #0
1222 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
1223 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1224 ; CHECK-MVE-NEXT: cset r0, pl
1225 ; CHECK-MVE-NEXT: cmp r0, #0
1226 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
1227 ; CHECK-MVE-NEXT: vins.f16 s3, s4
1228 ; CHECK-MVE-NEXT: bx lr
1229 ;
1230 ; CHECK-MVEFP-LABEL: vcmp_uge_v8f16:
1231 ; CHECK-MVEFP: @ %bb.0: @ %entry
1232 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
1233 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1234 ; CHECK-MVEFP-NEXT: bx lr
1235 entry:
1236 %c = fcmp uge <8 x half> %src, zeroinitializer
1237 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
1238 ret <8 x half> %s
1239 }
1241 define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
1242 ; CHECK-MVE-LABEL: vcmp_ult_v8f16:
1243 ; CHECK-MVE: @ %bb.0: @ %entry
1244 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
1245 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
1246 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
1247 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
1248 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1249 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
1250 ; CHECK-MVE-NEXT: cset r0, lt
1251 ; CHECK-MVE-NEXT: cmp r0, #0
1252 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
1253 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1254 ; CHECK-MVE-NEXT: cset r0, lt
1255 ; CHECK-MVE-NEXT: cmp r0, #0
1256 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
1257 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
1258 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
1259 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
1260 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1261 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
1262 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
1263 ; CHECK-MVE-NEXT: vins.f16 s0, s12
1264 ; CHECK-MVE-NEXT: cset r0, lt
1265 ; CHECK-MVE-NEXT: cmp r0, #0
1266 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
1267 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1268 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
1269 ; CHECK-MVE-NEXT: cset r0, lt
1270 ; CHECK-MVE-NEXT: cmp r0, #0
1271 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
1272 ; CHECK-MVE-NEXT: vins.f16 s1, s4
1273 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
1274 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
1275 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
1276 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1277 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
1278 ; CHECK-MVE-NEXT: cset r0, lt
1279 ; CHECK-MVE-NEXT: cmp r0, #0
1280 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
1281 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1282 ; CHECK-MVE-NEXT: cset r0, lt
1283 ; CHECK-MVE-NEXT: cmp r0, #0
1284 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
1285 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
1286 ; CHECK-MVE-NEXT: vins.f16 s2, s4
1287 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
1288 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
1289 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
1290 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1291 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
1292 ; CHECK-MVE-NEXT: cset r0, lt
1293 ; CHECK-MVE-NEXT: cmp r0, #0
1294 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
1295 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1296 ; CHECK-MVE-NEXT: cset r0, lt
1297 ; CHECK-MVE-NEXT: cmp r0, #0
1298 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
1299 ; CHECK-MVE-NEXT: vins.f16 s3, s4
1300 ; CHECK-MVE-NEXT: bx lr
1301 ;
1302 ; CHECK-MVEFP-LABEL: vcmp_ult_v8f16:
1303 ; CHECK-MVEFP: @ %bb.0: @ %entry
1304 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
1305 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1306 ; CHECK-MVEFP-NEXT: bx lr
1307 entry:
1308 %c = fcmp ult <8 x half> %src, zeroinitializer
1309 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
1310 ret <8 x half> %s
1311 }
1313 define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
1314 ; CHECK-MVE-LABEL: vcmp_ule_v8f16:
1315 ; CHECK-MVE: @ %bb.0: @ %entry
1316 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
1317 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
1318 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
1319 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
1320 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1321 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
1322 ; CHECK-MVE-NEXT: cset r0, le
1323 ; CHECK-MVE-NEXT: cmp r0, #0
1324 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
1325 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1326 ; CHECK-MVE-NEXT: cset r0, le
1327 ; CHECK-MVE-NEXT: cmp r0, #0
1328 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
1329 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
1330 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
1331 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
1332 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1333 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
1334 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
1335 ; CHECK-MVE-NEXT: vins.f16 s0, s12
1336 ; CHECK-MVE-NEXT: cset r0, le
1337 ; CHECK-MVE-NEXT: cmp r0, #0
1338 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
1339 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1340 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
1341 ; CHECK-MVE-NEXT: cset r0, le
1342 ; CHECK-MVE-NEXT: cmp r0, #0
1343 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
1344 ; CHECK-MVE-NEXT: vins.f16 s1, s4
1345 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
1346 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
1347 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
1348 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1349 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
1350 ; CHECK-MVE-NEXT: cset r0, le
1351 ; CHECK-MVE-NEXT: cmp r0, #0
1352 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
1353 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1354 ; CHECK-MVE-NEXT: cset r0, le
1355 ; CHECK-MVE-NEXT: cmp r0, #0
1356 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
1357 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
1358 ; CHECK-MVE-NEXT: vins.f16 s2, s4
1359 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
1360 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
1361 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
1362 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1363 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
1364 ; CHECK-MVE-NEXT: cset r0, le
1365 ; CHECK-MVE-NEXT: cmp r0, #0
1366 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
1367 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1368 ; CHECK-MVE-NEXT: cset r0, le
1369 ; CHECK-MVE-NEXT: cmp r0, #0
1370 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
1371 ; CHECK-MVE-NEXT: vins.f16 s3, s4
1372 ; CHECK-MVE-NEXT: bx lr
1373 ;
1374 ; CHECK-MVEFP-LABEL: vcmp_ule_v8f16:
1375 ; CHECK-MVEFP: @ %bb.0: @ %entry
1376 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
1377 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1378 ; CHECK-MVEFP-NEXT: bx lr
1379 entry:
1380 %c = fcmp ule <8 x half> %src, zeroinitializer
1381 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
1382 ret <8 x half> %s
1383 }
1385 define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
1386 ; CHECK-MVE-LABEL: vcmp_ord_v8f16:
1387 ; CHECK-MVE: @ %bb.0: @ %entry
1388 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
1389 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
1390 ; CHECK-MVE-NEXT: vcmp.f16 s12, s12
1391 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
1392 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1393 ; CHECK-MVE-NEXT: vcmp.f16 s0, s0
1394 ; CHECK-MVE-NEXT: cset r0, vc
1395 ; CHECK-MVE-NEXT: cmp r0, #0
1396 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
1397 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1398 ; CHECK-MVE-NEXT: cset r0, vc
1399 ; CHECK-MVE-NEXT: cmp r0, #0
1400 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
1401 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
1402 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
1403 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
1404 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1405 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
1406 ; CHECK-MVE-NEXT: vcmp.f16 s1, s1
1407 ; CHECK-MVE-NEXT: vins.f16 s0, s12
1408 ; CHECK-MVE-NEXT: cset r0, vc
1409 ; CHECK-MVE-NEXT: cmp r0, #0
1410 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
1411 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1412 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
1413 ; CHECK-MVE-NEXT: cset r0, vc
1414 ; CHECK-MVE-NEXT: cmp r0, #0
1415 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
1416 ; CHECK-MVE-NEXT: vins.f16 s1, s4
1417 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
1418 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
1419 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
1420 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1421 ; CHECK-MVE-NEXT: vcmp.f16 s2, s2
1422 ; CHECK-MVE-NEXT: cset r0, vc
1423 ; CHECK-MVE-NEXT: cmp r0, #0
1424 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
1425 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1426 ; CHECK-MVE-NEXT: cset r0, vc
1427 ; CHECK-MVE-NEXT: cmp r0, #0
1428 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
1429 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
1430 ; CHECK-MVE-NEXT: vins.f16 s2, s4
1431 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
1432 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
1433 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
1434 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1435 ; CHECK-MVE-NEXT: vcmp.f16 s3, s3
1436 ; CHECK-MVE-NEXT: cset r0, vc
1437 ; CHECK-MVE-NEXT: cmp r0, #0
1438 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
1439 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1440 ; CHECK-MVE-NEXT: cset r0, vc
1441 ; CHECK-MVE-NEXT: cmp r0, #0
1442 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
1443 ; CHECK-MVE-NEXT: vins.f16 s3, s4
1444 ; CHECK-MVE-NEXT: bx lr
1445 ;
1446 ; CHECK-MVEFP-LABEL: vcmp_ord_v8f16:
1447 ; CHECK-MVEFP: @ %bb.0: @ %entry
1448 ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
1449 ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr
1450 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
1451 ; CHECK-MVEFP-NEXT: bx lr
1452 entry:
1453 %c = fcmp ord <8 x half> %src, zeroinitializer
1454 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
1455 ret <8 x half> %s
1456 }
1458 define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
1459 ; CHECK-MVE-LABEL: vcmp_uno_v8f16:
1460 ; CHECK-MVE: @ %bb.0: @ %entry
1461 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
1462 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
1463 ; CHECK-MVE-NEXT: vcmp.f16 s12, s12
1464 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
1465 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1466 ; CHECK-MVE-NEXT: vcmp.f16 s0, s0
1467 ; CHECK-MVE-NEXT: cset r0, vs
1468 ; CHECK-MVE-NEXT: cmp r0, #0
1469 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
1470 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1471 ; CHECK-MVE-NEXT: cset r0, vs
1472 ; CHECK-MVE-NEXT: cmp r0, #0
1473 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
1474 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
1475 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
1476 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
1477 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1478 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
1479 ; CHECK-MVE-NEXT: vcmp.f16 s1, s1
1480 ; CHECK-MVE-NEXT: vins.f16 s0, s12
1481 ; CHECK-MVE-NEXT: cset r0, vs
1482 ; CHECK-MVE-NEXT: cmp r0, #0
1483 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
1484 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1485 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
1486 ; CHECK-MVE-NEXT: cset r0, vs
1487 ; CHECK-MVE-NEXT: cmp r0, #0
1488 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
1489 ; CHECK-MVE-NEXT: vins.f16 s1, s4
1490 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
1491 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
1492 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
1493 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1494 ; CHECK-MVE-NEXT: vcmp.f16 s2, s2
1495 ; CHECK-MVE-NEXT: cset r0, vs
1496 ; CHECK-MVE-NEXT: cmp r0, #0
1497 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
1498 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1499 ; CHECK-MVE-NEXT: cset r0, vs
1500 ; CHECK-MVE-NEXT: cmp r0, #0
1501 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
1502 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
1503 ; CHECK-MVE-NEXT: vins.f16 s2, s4
1504 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
1505 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
1506 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
1507 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1508 ; CHECK-MVE-NEXT: vcmp.f16 s3, s3
1509 ; CHECK-MVE-NEXT: cset r0, vs
1510 ; CHECK-MVE-NEXT: cmp r0, #0
1511 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
1512 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1513 ; CHECK-MVE-NEXT: cset r0, vs
1514 ; CHECK-MVE-NEXT: cmp r0, #0
1515 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
1516 ; CHECK-MVE-NEXT: vins.f16 s3, s4
1517 ; CHECK-MVE-NEXT: bx lr
1518 ;
1519 ; CHECK-MVEFP-LABEL: vcmp_uno_v8f16:
1520 ; CHECK-MVEFP: @ %bb.0: @ %entry
1521 ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
1522 ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr
1523 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1524 ; CHECK-MVEFP-NEXT: bx lr
1525 entry:
1526 %c = fcmp uno <8 x half> %src, zeroinitializer
1527 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
1528 ret <8 x half> %s
1529 }
1532 ; Reversed
1534 define arm_aapcs_vfpcc <4 x float> @vcmp_r_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
1535 ; CHECK-MVE-LABEL: vcmp_r_oeq_v4f32:
1536 ; CHECK-MVE: @ %bb.0: @ %entry
1537 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
1538 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1539 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
1540 ; CHECK-MVE-NEXT: cset r0, eq
1541 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1542 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
1543 ; CHECK-MVE-NEXT: cset r1, eq
1544 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1545 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
1546 ; CHECK-MVE-NEXT: cset r2, eq
1547 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1548 ; CHECK-MVE-NEXT: cset r3, eq
1549 ; CHECK-MVE-NEXT: cmp r2, #0
1550 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
1551 ; CHECK-MVE-NEXT: cmp r3, #0
1552 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
1553 ; CHECK-MVE-NEXT: cmp r0, #0
1554 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
1555 ; CHECK-MVE-NEXT: cmp r1, #0
1556 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
1557 ; CHECK-MVE-NEXT: bx lr
1558 ;
1559 ; CHECK-MVEFP-LABEL: vcmp_r_oeq_v4f32:
1560 ; CHECK-MVEFP: @ %bb.0: @ %entry
1561 ; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, zr
1562 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1563 ; CHECK-MVEFP-NEXT: bx lr
1564 entry:
1565 %c = fcmp oeq <4 x float> zeroinitializer, %src
1566 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
1567 ret <4 x float> %s
1568 }
1570 define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
1571 ; CHECK-MVE-LABEL: vcmp_r_one_v4f32:
1572 ; CHECK-MVE: @ %bb.0: @ %entry
1573 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
1574 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1575 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
1576 ; CHECK-MVE-NEXT: cset r0, mi
1577 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1578 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
1579 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
1580 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1581 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
1582 ; CHECK-MVE-NEXT: cset r1, mi
1583 ; CHECK-MVE-NEXT: csinc r1, r1, zr, le
1584 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1585 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
1586 ; CHECK-MVE-NEXT: cset r2, mi
1587 ; CHECK-MVE-NEXT: csinc r2, r2, zr, le
1588 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1589 ; CHECK-MVE-NEXT: cset r3, mi
1590 ; CHECK-MVE-NEXT: csinc r3, r3, zr, le
1591 ; CHECK-MVE-NEXT: cmp r2, #0
1592 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
1593 ; CHECK-MVE-NEXT: cmp r3, #0
1594 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
1595 ; CHECK-MVE-NEXT: cmp r0, #0
1596 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
1597 ; CHECK-MVE-NEXT: cmp r1, #0
1598 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
1599 ; CHECK-MVE-NEXT: bx lr
1600 ;
1601 ; CHECK-MVEFP-LABEL: vcmp_r_one_v4f32:
1602 ; CHECK-MVEFP: @ %bb.0: @ %entry
1603 ; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr
1604 ; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, zr
1605 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
1606 ; CHECK-MVEFP-NEXT: bx lr
1607 entry:
1608 %c = fcmp one <4 x float> zeroinitializer, %src
1609 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
1610 ret <4 x float> %s
1611 }
1613 define arm_aapcs_vfpcc <4 x float> @vcmp_r_ogt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
1614 ; CHECK-MVE-LABEL: vcmp_r_ogt_v4f32:
1615 ; CHECK-MVE: @ %bb.0: @ %entry
1616 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
1617 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1618 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
1619 ; CHECK-MVE-NEXT: cset r0, mi
1620 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1621 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
1622 ; CHECK-MVE-NEXT: cset r1, mi
1623 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1624 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
1625 ; CHECK-MVE-NEXT: cset r2, mi
1626 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1627 ; CHECK-MVE-NEXT: cset r3, mi
1628 ; CHECK-MVE-NEXT: cmp r2, #0
1629 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
1630 ; CHECK-MVE-NEXT: cmp r3, #0
1631 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
1632 ; CHECK-MVE-NEXT: cmp r0, #0
1633 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
1634 ; CHECK-MVE-NEXT: cmp r1, #0
1635 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
1636 ; CHECK-MVE-NEXT: bx lr
1637 ;
1638 ; CHECK-MVEFP-LABEL: vcmp_r_ogt_v4f32:
1639 ; CHECK-MVEFP: @ %bb.0: @ %entry
1640 ; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr
1641 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1642 ; CHECK-MVEFP-NEXT: bx lr
1643 entry:
1644 %c = fcmp ogt <4 x float> zeroinitializer, %src
1645 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
1646 ret <4 x float> %s
1647 }
1649 define arm_aapcs_vfpcc <4 x float> @vcmp_r_oge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
1650 ; CHECK-MVE-LABEL: vcmp_r_oge_v4f32:
1651 ; CHECK-MVE: @ %bb.0: @ %entry
1652 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
1653 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1654 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
1655 ; CHECK-MVE-NEXT: cset r0, ls
1656 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1657 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
1658 ; CHECK-MVE-NEXT: cset r1, ls
1659 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1660 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
1661 ; CHECK-MVE-NEXT: cset r2, ls
1662 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1663 ; CHECK-MVE-NEXT: cset r3, ls
1664 ; CHECK-MVE-NEXT: cmp r2, #0
1665 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
1666 ; CHECK-MVE-NEXT: cmp r3, #0
1667 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
1668 ; CHECK-MVE-NEXT: cmp r0, #0
1669 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
1670 ; CHECK-MVE-NEXT: cmp r1, #0
1671 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
1672 ; CHECK-MVE-NEXT: bx lr
1673 ;
1674 ; CHECK-MVEFP-LABEL: vcmp_r_oge_v4f32:
1675 ; CHECK-MVEFP: @ %bb.0: @ %entry
1676 ; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr
1677 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1678 ; CHECK-MVEFP-NEXT: bx lr
1679 entry:
1680 %c = fcmp oge <4 x float> zeroinitializer, %src
1681 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
1682 ret <4 x float> %s
1683 }
1685 define arm_aapcs_vfpcc <4 x float> @vcmp_r_olt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
1686 ; CHECK-MVE-LABEL: vcmp_r_olt_v4f32:
1687 ; CHECK-MVE: @ %bb.0: @ %entry
1688 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
1689 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1690 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
1691 ; CHECK-MVE-NEXT: cset r0, gt
1692 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1693 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
1694 ; CHECK-MVE-NEXT: cset r1, gt
1695 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1696 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
1697 ; CHECK-MVE-NEXT: cset r2, gt
1698 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1699 ; CHECK-MVE-NEXT: cset r3, gt
1700 ; CHECK-MVE-NEXT: cmp r2, #0
1701 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
1702 ; CHECK-MVE-NEXT: cmp r3, #0
1703 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
1704 ; CHECK-MVE-NEXT: cmp r0, #0
1705 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
1706 ; CHECK-MVE-NEXT: cmp r1, #0
1707 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
1708 ; CHECK-MVE-NEXT: bx lr
1709 ;
1710 ; CHECK-MVEFP-LABEL: vcmp_r_olt_v4f32:
1711 ; CHECK-MVEFP: @ %bb.0: @ %entry
1712 ; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr
1713 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1714 ; CHECK-MVEFP-NEXT: bx lr
1715 entry:
1716 %c = fcmp olt <4 x float> zeroinitializer, %src
1717 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
1718 ret <4 x float> %s
1719 }
1721 define arm_aapcs_vfpcc <4 x float> @vcmp_r_ole_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
1722 ; CHECK-MVE-LABEL: vcmp_r_ole_v4f32:
1723 ; CHECK-MVE: @ %bb.0: @ %entry
1724 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
1725 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1726 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
1727 ; CHECK-MVE-NEXT: cset r0, ge
1728 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1729 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
1730 ; CHECK-MVE-NEXT: cset r1, ge
1731 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1732 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
1733 ; CHECK-MVE-NEXT: cset r2, ge
1734 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1735 ; CHECK-MVE-NEXT: cset r3, ge
1736 ; CHECK-MVE-NEXT: cmp r2, #0
1737 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
1738 ; CHECK-MVE-NEXT: cmp r3, #0
1739 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
1740 ; CHECK-MVE-NEXT: cmp r0, #0
1741 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
1742 ; CHECK-MVE-NEXT: cmp r1, #0
1743 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
1744 ; CHECK-MVE-NEXT: bx lr
1745 ;
1746 ; CHECK-MVEFP-LABEL: vcmp_r_ole_v4f32:
1747 ; CHECK-MVEFP: @ %bb.0: @ %entry
1748 ; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr
1749 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1750 ; CHECK-MVEFP-NEXT: bx lr
1751 entry:
1752 %c = fcmp ole <4 x float> zeroinitializer, %src
1753 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
1754 ret <4 x float> %s
1755 }
1757 define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
1758 ; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32:
1759 ; CHECK-MVE: @ %bb.0: @ %entry
1760 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
1761 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1762 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
1763 ; CHECK-MVE-NEXT: cset r0, eq
1764 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1765 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
1766 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
1767 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1768 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
1769 ; CHECK-MVE-NEXT: cset r1, eq
1770 ; CHECK-MVE-NEXT: csinc r1, r1, zr, vc
1771 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1772 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
1773 ; CHECK-MVE-NEXT: cset r2, eq
1774 ; CHECK-MVE-NEXT: csinc r2, r2, zr, vc
1775 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1776 ; CHECK-MVE-NEXT: cset r3, eq
1777 ; CHECK-MVE-NEXT: csinc r3, r3, zr, vc
1778 ; CHECK-MVE-NEXT: cmp r2, #0
1779 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
1780 ; CHECK-MVE-NEXT: cmp r3, #0
1781 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
1782 ; CHECK-MVE-NEXT: cmp r0, #0
1783 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
1784 ; CHECK-MVE-NEXT: cmp r1, #0
1785 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
1786 ; CHECK-MVE-NEXT: bx lr
1787 ;
1788 ; CHECK-MVEFP-LABEL: vcmp_r_ueq_v4f32:
1789 ; CHECK-MVEFP: @ %bb.0: @ %entry
1790 ; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr
1791 ; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, zr
1792 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1793 ; CHECK-MVEFP-NEXT: bx lr
1794 entry:
1795 %c = fcmp ueq <4 x float> zeroinitializer, %src
1796 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
1797 ret <4 x float> %s
1798 }
1800 define arm_aapcs_vfpcc <4 x float> @vcmp_r_une_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
1801 ; CHECK-MVE-LABEL: vcmp_r_une_v4f32:
1802 ; CHECK-MVE: @ %bb.0: @ %entry
1803 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
1804 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1805 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
1806 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
1807 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1808 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
1809 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
1810 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1811 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
1812 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
1813 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1814 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
1815 ; CHECK-MVE-NEXT: bx lr
1816 ;
1817 ; CHECK-MVEFP-LABEL: vcmp_r_une_v4f32:
1818 ; CHECK-MVEFP: @ %bb.0: @ %entry
1819 ; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, zr
1820 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1821 ; CHECK-MVEFP-NEXT: bx lr
1822 entry:
1823 %c = fcmp une <4 x float> zeroinitializer, %src
1824 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
1825 ret <4 x float> %s
1826 }
1828 define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
1829 ; CHECK-MVE-LABEL: vcmp_r_ugt_v4f32:
1830 ; CHECK-MVE: @ %bb.0: @ %entry
1831 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
1832 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1833 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
1834 ; CHECK-MVE-NEXT: cset r0, lt
1835 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1836 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
1837 ; CHECK-MVE-NEXT: cset r1, lt
1838 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1839 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
1840 ; CHECK-MVE-NEXT: cset r2, lt
1841 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1842 ; CHECK-MVE-NEXT: cset r3, lt
1843 ; CHECK-MVE-NEXT: cmp r2, #0
1844 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
1845 ; CHECK-MVE-NEXT: cmp r3, #0
1846 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
1847 ; CHECK-MVE-NEXT: cmp r0, #0
1848 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
1849 ; CHECK-MVE-NEXT: cmp r1, #0
1850 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
1851 ; CHECK-MVE-NEXT: bx lr
1852 ;
1853 ; CHECK-MVEFP-LABEL: vcmp_r_ugt_v4f32:
1854 ; CHECK-MVEFP: @ %bb.0: @ %entry
1855 ; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr
1856 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1857 ; CHECK-MVEFP-NEXT: bx lr
1858 entry:
1859 %c = fcmp ugt <4 x float> zeroinitializer, %src
1860 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
1861 ret <4 x float> %s
1862 }
1864 define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
1865 ; CHECK-MVE-LABEL: vcmp_r_uge_v4f32:
1866 ; CHECK-MVE: @ %bb.0: @ %entry
1867 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
1868 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1869 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
1870 ; CHECK-MVE-NEXT: cset r0, le
1871 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1872 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
1873 ; CHECK-MVE-NEXT: cset r1, le
1874 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1875 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
1876 ; CHECK-MVE-NEXT: cset r2, le
1877 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1878 ; CHECK-MVE-NEXT: cset r3, le
1879 ; CHECK-MVE-NEXT: cmp r2, #0
1880 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
1881 ; CHECK-MVE-NEXT: cmp r3, #0
1882 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
1883 ; CHECK-MVE-NEXT: cmp r0, #0
1884 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
1885 ; CHECK-MVE-NEXT: cmp r1, #0
1886 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
1887 ; CHECK-MVE-NEXT: bx lr
1888 ;
1889 ; CHECK-MVEFP-LABEL: vcmp_r_uge_v4f32:
1890 ; CHECK-MVEFP: @ %bb.0: @ %entry
1891 ; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr
1892 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1893 ; CHECK-MVEFP-NEXT: bx lr
1894 entry:
1895 %c = fcmp uge <4 x float> zeroinitializer, %src
1896 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
1897 ret <4 x float> %s
1898 }
1900 define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
1901 ; CHECK-MVE-LABEL: vcmp_r_ult_v4f32:
1902 ; CHECK-MVE: @ %bb.0: @ %entry
1903 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
1904 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1905 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
1906 ; CHECK-MVE-NEXT: cset r0, hi
1907 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1908 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
1909 ; CHECK-MVE-NEXT: cset r1, hi
1910 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1911 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
1912 ; CHECK-MVE-NEXT: cset r2, hi
1913 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1914 ; CHECK-MVE-NEXT: cset r3, hi
1915 ; CHECK-MVE-NEXT: cmp r2, #0
1916 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
1917 ; CHECK-MVE-NEXT: cmp r3, #0
1918 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
1919 ; CHECK-MVE-NEXT: cmp r0, #0
1920 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
1921 ; CHECK-MVE-NEXT: cmp r1, #0
1922 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
1923 ; CHECK-MVE-NEXT: bx lr
1924 ;
1925 ; CHECK-MVEFP-LABEL: vcmp_r_ult_v4f32:
1926 ; CHECK-MVEFP: @ %bb.0: @ %entry
1927 ; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr
1928 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1929 ; CHECK-MVEFP-NEXT: bx lr
1930 entry:
1931 %c = fcmp ult <4 x float> zeroinitializer, %src
1932 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
1933 ret <4 x float> %s
1934 }
1936 define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
1937 ; CHECK-MVE-LABEL: vcmp_r_ule_v4f32:
1938 ; CHECK-MVE: @ %bb.0: @ %entry
1939 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
1940 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1941 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
1942 ; CHECK-MVE-NEXT: cset r0, pl
1943 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1944 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
1945 ; CHECK-MVE-NEXT: cset r1, pl
1946 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1947 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
1948 ; CHECK-MVE-NEXT: cset r2, pl
1949 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1950 ; CHECK-MVE-NEXT: cset r3, pl
1951 ; CHECK-MVE-NEXT: cmp r2, #0
1952 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
1953 ; CHECK-MVE-NEXT: cmp r3, #0
1954 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
1955 ; CHECK-MVE-NEXT: cmp r0, #0
1956 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
1957 ; CHECK-MVE-NEXT: cmp r1, #0
1958 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
1959 ; CHECK-MVE-NEXT: bx lr
1960 ;
1961 ; CHECK-MVEFP-LABEL: vcmp_r_ule_v4f32:
1962 ; CHECK-MVEFP: @ %bb.0: @ %entry
1963 ; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr
1964 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
1965 ; CHECK-MVEFP-NEXT: bx lr
1966 entry:
1967 %c = fcmp ule <4 x float> zeroinitializer, %src
1968 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
1969 ret <4 x float> %s
1970 }
1972 define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
1973 ; CHECK-MVE-LABEL: vcmp_r_ord_v4f32:
1974 ; CHECK-MVE: @ %bb.0: @ %entry
1975 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
1976 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1977 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
1978 ; CHECK-MVE-NEXT: cset r0, vc
1979 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1980 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
1981 ; CHECK-MVE-NEXT: cset r1, vc
1982 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1983 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
1984 ; CHECK-MVE-NEXT: cset r2, vc
1985 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
1986 ; CHECK-MVE-NEXT: cset r3, vc
1987 ; CHECK-MVE-NEXT: cmp r2, #0
1988 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
1989 ; CHECK-MVE-NEXT: cmp r3, #0
1990 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
1991 ; CHECK-MVE-NEXT: cmp r0, #0
1992 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
1993 ; CHECK-MVE-NEXT: cmp r1, #0
1994 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
1995 ; CHECK-MVE-NEXT: bx lr
1996 ;
1997 ; CHECK-MVEFP-LABEL: vcmp_r_ord_v4f32:
1998 ; CHECK-MVEFP: @ %bb.0: @ %entry
1999 ; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr
2000 ; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, zr
2001 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
2002 ; CHECK-MVEFP-NEXT: bx lr
2003 entry:
2004 %c = fcmp ord <4 x float> zeroinitializer, %src
2005 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
2006 ret <4 x float> %s
2007 }
2009 define arm_aapcs_vfpcc <4 x float> @vcmp_r_uno_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
2010 ; CHECK-MVE-LABEL: vcmp_r_uno_v4f32:
2011 ; CHECK-MVE: @ %bb.0: @ %entry
2012 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
2013 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2014 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
2015 ; CHECK-MVE-NEXT: cset r0, vs
2016 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2017 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
2018 ; CHECK-MVE-NEXT: cset r1, vs
2019 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2020 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
2021 ; CHECK-MVE-NEXT: cset r2, vs
2022 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2023 ; CHECK-MVE-NEXT: cset r3, vs
2024 ; CHECK-MVE-NEXT: cmp r2, #0
2025 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
2026 ; CHECK-MVE-NEXT: cmp r3, #0
2027 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
2028 ; CHECK-MVE-NEXT: cmp r0, #0
2029 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
2030 ; CHECK-MVE-NEXT: cmp r1, #0
2031 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
2032 ; CHECK-MVE-NEXT: bx lr
2033 ;
2034 ; CHECK-MVEFP-LABEL: vcmp_r_uno_v4f32:
2035 ; CHECK-MVEFP: @ %bb.0: @ %entry
2036 ; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr
2037 ; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, zr
2038 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
2039 ; CHECK-MVEFP-NEXT: bx lr
2040 entry:
2041 %c = fcmp uno <4 x float> zeroinitializer, %src
2042 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
2043 ret <4 x float> %s
2044 }
2048 define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
2049 ; CHECK-MVE-LABEL: vcmp_r_oeq_v8f16:
2050 ; CHECK-MVE: @ %bb.0: @ %entry
2051 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
2052 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
2053 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
2054 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
2055 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2056 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
2057 ; CHECK-MVE-NEXT: cset r0, eq
2058 ; CHECK-MVE-NEXT: cmp r0, #0
2059 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
2060 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2061 ; CHECK-MVE-NEXT: cset r0, eq
2062 ; CHECK-MVE-NEXT: cmp r0, #0
2063 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
2064 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
2065 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2066 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
2067 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2068 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
2069 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
2070 ; CHECK-MVE-NEXT: vins.f16 s0, s12
2071 ; CHECK-MVE-NEXT: cset r0, eq
2072 ; CHECK-MVE-NEXT: cmp r0, #0
2073 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2074 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2075 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
2076 ; CHECK-MVE-NEXT: cset r0, eq
2077 ; CHECK-MVE-NEXT: cmp r0, #0
2078 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
2079 ; CHECK-MVE-NEXT: vins.f16 s1, s4
2080 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
2081 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2082 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
2083 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2084 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
2085 ; CHECK-MVE-NEXT: cset r0, eq
2086 ; CHECK-MVE-NEXT: cmp r0, #0
2087 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2088 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2089 ; CHECK-MVE-NEXT: cset r0, eq
2090 ; CHECK-MVE-NEXT: cmp r0, #0
2091 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
2092 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
2093 ; CHECK-MVE-NEXT: vins.f16 s2, s4
2094 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
2095 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2096 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
2097 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2098 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
2099 ; CHECK-MVE-NEXT: cset r0, eq
2100 ; CHECK-MVE-NEXT: cmp r0, #0
2101 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
2102 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2103 ; CHECK-MVE-NEXT: cset r0, eq
2104 ; CHECK-MVE-NEXT: cmp r0, #0
2105 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
2106 ; CHECK-MVE-NEXT: vins.f16 s3, s4
2107 ; CHECK-MVE-NEXT: bx lr
2108 ;
2109 ; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16:
2110 ; CHECK-MVEFP: @ %bb.0: @ %entry
2111 ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr
2112 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
2113 ; CHECK-MVEFP-NEXT: bx lr
2114 entry:
2115 %c = fcmp oeq <8 x half> zeroinitializer, %src
2116 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
2117 ret <8 x half> %s
2118 }
2120 define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
2121 ; CHECK-MVE-LABEL: vcmp_r_one_v8f16:
2122 ; CHECK-MVE: @ %bb.0: @ %entry
2123 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
2124 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
2125 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
2126 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
2127 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2128 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
2129 ; CHECK-MVE-NEXT: cset r0, mi
2130 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
2131 ; CHECK-MVE-NEXT: cmp r0, #0
2132 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
2133 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2134 ; CHECK-MVE-NEXT: cset r0, mi
2135 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
2136 ; CHECK-MVE-NEXT: cmp r0, #0
2137 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
2138 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
2139 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2140 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
2141 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2142 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
2143 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
2144 ; CHECK-MVE-NEXT: vins.f16 s0, s12
2145 ; CHECK-MVE-NEXT: cset r0, mi
2146 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
2147 ; CHECK-MVE-NEXT: cmp r0, #0
2148 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2149 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2150 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
2151 ; CHECK-MVE-NEXT: cset r0, mi
2152 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
2153 ; CHECK-MVE-NEXT: cmp r0, #0
2154 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
2155 ; CHECK-MVE-NEXT: vins.f16 s1, s4
2156 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
2157 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2158 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
2159 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2160 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
2161 ; CHECK-MVE-NEXT: cset r0, mi
2162 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
2163 ; CHECK-MVE-NEXT: cmp r0, #0
2164 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2165 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2166 ; CHECK-MVE-NEXT: cset r0, mi
2167 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
2168 ; CHECK-MVE-NEXT: cmp r0, #0
2169 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
2170 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
2171 ; CHECK-MVE-NEXT: vins.f16 s2, s4
2172 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
2173 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2174 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
2175 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2176 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
2177 ; CHECK-MVE-NEXT: cset r0, mi
2178 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
2179 ; CHECK-MVE-NEXT: cmp r0, #0
2180 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
2181 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2182 ; CHECK-MVE-NEXT: cset r0, mi
2183 ; CHECK-MVE-NEXT: csinc r0, r0, zr, le
2184 ; CHECK-MVE-NEXT: cmp r0, #0
2185 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
2186 ; CHECK-MVE-NEXT: vins.f16 s3, s4
2187 ; CHECK-MVE-NEXT: bx lr
2188 ;
2189 ; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16:
2190 ; CHECK-MVEFP: @ %bb.0: @ %entry
2191 ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
2192 ; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr
2193 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
2194 ; CHECK-MVEFP-NEXT: bx lr
2195 entry:
2196 %c = fcmp one <8 x half> zeroinitializer, %src
2197 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
2198 ret <8 x half> %s
2199 }
2201 define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
2202 ; CHECK-MVE-LABEL: vcmp_r_ogt_v8f16:
2203 ; CHECK-MVE: @ %bb.0: @ %entry
2204 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
2205 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
2206 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
2207 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
2208 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2209 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
2210 ; CHECK-MVE-NEXT: cset r0, mi
2211 ; CHECK-MVE-NEXT: cmp r0, #0
2212 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
2213 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2214 ; CHECK-MVE-NEXT: cset r0, mi
2215 ; CHECK-MVE-NEXT: cmp r0, #0
2216 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
2217 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
2218 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2219 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
2220 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2221 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
2222 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
2223 ; CHECK-MVE-NEXT: vins.f16 s0, s12
2224 ; CHECK-MVE-NEXT: cset r0, mi
2225 ; CHECK-MVE-NEXT: cmp r0, #0
2226 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2227 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2228 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
2229 ; CHECK-MVE-NEXT: cset r0, mi
2230 ; CHECK-MVE-NEXT: cmp r0, #0
2231 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
2232 ; CHECK-MVE-NEXT: vins.f16 s1, s4
2233 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
2234 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2235 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
2236 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2237 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
2238 ; CHECK-MVE-NEXT: cset r0, mi
2239 ; CHECK-MVE-NEXT: cmp r0, #0
2240 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2241 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2242 ; CHECK-MVE-NEXT: cset r0, mi
2243 ; CHECK-MVE-NEXT: cmp r0, #0
2244 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
2245 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
2246 ; CHECK-MVE-NEXT: vins.f16 s2, s4
2247 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
2248 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2249 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
2250 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2251 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
2252 ; CHECK-MVE-NEXT: cset r0, mi
2253 ; CHECK-MVE-NEXT: cmp r0, #0
2254 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
2255 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2256 ; CHECK-MVE-NEXT: cset r0, mi
2257 ; CHECK-MVE-NEXT: cmp r0, #0
2258 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
2259 ; CHECK-MVE-NEXT: vins.f16 s3, s4
2260 ; CHECK-MVE-NEXT: bx lr
2261 ;
2262 ; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16:
2263 ; CHECK-MVEFP: @ %bb.0: @ %entry
2264 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
2265 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
2266 ; CHECK-MVEFP-NEXT: bx lr
2267 entry:
2268 %c = fcmp ogt <8 x half> zeroinitializer, %src
2269 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
2270 ret <8 x half> %s
2271 }
2273 define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
2274 ; CHECK-MVE-LABEL: vcmp_r_oge_v8f16:
2275 ; CHECK-MVE: @ %bb.0: @ %entry
2276 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
2277 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
2278 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
2279 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
2280 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2281 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
2282 ; CHECK-MVE-NEXT: cset r0, ls
2283 ; CHECK-MVE-NEXT: cmp r0, #0
2284 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
2285 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2286 ; CHECK-MVE-NEXT: cset r0, ls
2287 ; CHECK-MVE-NEXT: cmp r0, #0
2288 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
2289 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
2290 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2291 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
2292 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2293 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
2294 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
2295 ; CHECK-MVE-NEXT: vins.f16 s0, s12
2296 ; CHECK-MVE-NEXT: cset r0, ls
2297 ; CHECK-MVE-NEXT: cmp r0, #0
2298 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2299 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2300 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
2301 ; CHECK-MVE-NEXT: cset r0, ls
2302 ; CHECK-MVE-NEXT: cmp r0, #0
2303 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
2304 ; CHECK-MVE-NEXT: vins.f16 s1, s4
2305 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
2306 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2307 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
2308 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2309 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
2310 ; CHECK-MVE-NEXT: cset r0, ls
2311 ; CHECK-MVE-NEXT: cmp r0, #0
2312 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2313 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2314 ; CHECK-MVE-NEXT: cset r0, ls
2315 ; CHECK-MVE-NEXT: cmp r0, #0
2316 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
2317 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
2318 ; CHECK-MVE-NEXT: vins.f16 s2, s4
2319 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
2320 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2321 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
2322 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2323 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
2324 ; CHECK-MVE-NEXT: cset r0, ls
2325 ; CHECK-MVE-NEXT: cmp r0, #0
2326 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
2327 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2328 ; CHECK-MVE-NEXT: cset r0, ls
2329 ; CHECK-MVE-NEXT: cmp r0, #0
2330 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
2331 ; CHECK-MVE-NEXT: vins.f16 s3, s4
2332 ; CHECK-MVE-NEXT: bx lr
2333 ;
2334 ; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16:
2335 ; CHECK-MVEFP: @ %bb.0: @ %entry
2336 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
2337 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
2338 ; CHECK-MVEFP-NEXT: bx lr
2339 entry:
2340 %c = fcmp oge <8 x half> zeroinitializer, %src
2341 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
2342 ret <8 x half> %s
2343 }
2345 define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
2346 ; CHECK-MVE-LABEL: vcmp_r_olt_v8f16:
2347 ; CHECK-MVE: @ %bb.0: @ %entry
2348 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
2349 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
2350 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
2351 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
2352 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2353 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
2354 ; CHECK-MVE-NEXT: cset r0, gt
2355 ; CHECK-MVE-NEXT: cmp r0, #0
2356 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
2357 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2358 ; CHECK-MVE-NEXT: cset r0, gt
2359 ; CHECK-MVE-NEXT: cmp r0, #0
2360 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
2361 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
2362 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2363 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
2364 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2365 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
2366 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
2367 ; CHECK-MVE-NEXT: vins.f16 s0, s12
2368 ; CHECK-MVE-NEXT: cset r0, gt
2369 ; CHECK-MVE-NEXT: cmp r0, #0
2370 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2371 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2372 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
2373 ; CHECK-MVE-NEXT: cset r0, gt
2374 ; CHECK-MVE-NEXT: cmp r0, #0
2375 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
2376 ; CHECK-MVE-NEXT: vins.f16 s1, s4
2377 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
2378 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2379 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
2380 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2381 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
2382 ; CHECK-MVE-NEXT: cset r0, gt
2383 ; CHECK-MVE-NEXT: cmp r0, #0
2384 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2385 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2386 ; CHECK-MVE-NEXT: cset r0, gt
2387 ; CHECK-MVE-NEXT: cmp r0, #0
2388 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
2389 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
2390 ; CHECK-MVE-NEXT: vins.f16 s2, s4
2391 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
2392 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2393 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
2394 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2395 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
2396 ; CHECK-MVE-NEXT: cset r0, gt
2397 ; CHECK-MVE-NEXT: cmp r0, #0
2398 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
2399 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2400 ; CHECK-MVE-NEXT: cset r0, gt
2401 ; CHECK-MVE-NEXT: cmp r0, #0
2402 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
2403 ; CHECK-MVE-NEXT: vins.f16 s3, s4
2404 ; CHECK-MVE-NEXT: bx lr
2405 ;
2406 ; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16:
2407 ; CHECK-MVEFP: @ %bb.0: @ %entry
2408 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
2409 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
2410 ; CHECK-MVEFP-NEXT: bx lr
2411 entry:
2412 %c = fcmp olt <8 x half> zeroinitializer, %src
2413 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
2414 ret <8 x half> %s
2415 }
2417 define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
2418 ; CHECK-MVE-LABEL: vcmp_r_ole_v8f16:
2419 ; CHECK-MVE: @ %bb.0: @ %entry
2420 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
2421 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
2422 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
2423 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
2424 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2425 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
2426 ; CHECK-MVE-NEXT: cset r0, ge
2427 ; CHECK-MVE-NEXT: cmp r0, #0
2428 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
2429 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2430 ; CHECK-MVE-NEXT: cset r0, ge
2431 ; CHECK-MVE-NEXT: cmp r0, #0
2432 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
2433 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
2434 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2435 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
2436 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2437 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
2438 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
2439 ; CHECK-MVE-NEXT: vins.f16 s0, s12
2440 ; CHECK-MVE-NEXT: cset r0, ge
2441 ; CHECK-MVE-NEXT: cmp r0, #0
2442 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2443 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2444 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
2445 ; CHECK-MVE-NEXT: cset r0, ge
2446 ; CHECK-MVE-NEXT: cmp r0, #0
2447 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
2448 ; CHECK-MVE-NEXT: vins.f16 s1, s4
2449 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
2450 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2451 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
2452 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2453 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
2454 ; CHECK-MVE-NEXT: cset r0, ge
2455 ; CHECK-MVE-NEXT: cmp r0, #0
2456 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2457 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2458 ; CHECK-MVE-NEXT: cset r0, ge
2459 ; CHECK-MVE-NEXT: cmp r0, #0
2460 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
2461 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
2462 ; CHECK-MVE-NEXT: vins.f16 s2, s4
2463 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
2464 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2465 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
2466 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2467 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
2468 ; CHECK-MVE-NEXT: cset r0, ge
2469 ; CHECK-MVE-NEXT: cmp r0, #0
2470 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
2471 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2472 ; CHECK-MVE-NEXT: cset r0, ge
2473 ; CHECK-MVE-NEXT: cmp r0, #0
2474 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
2475 ; CHECK-MVE-NEXT: vins.f16 s3, s4
2476 ; CHECK-MVE-NEXT: bx lr
2477 ;
2478 ; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16:
2479 ; CHECK-MVEFP: @ %bb.0: @ %entry
2480 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
2481 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
2482 ; CHECK-MVEFP-NEXT: bx lr
2483 entry:
2484 %c = fcmp ole <8 x half> zeroinitializer, %src
2485 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
2486 ret <8 x half> %s
2487 }
2489 define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
2490 ; CHECK-MVE-LABEL: vcmp_r_ueq_v8f16:
2491 ; CHECK-MVE: @ %bb.0: @ %entry
2492 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
2493 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
2494 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
2495 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
2496 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2497 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
2498 ; CHECK-MVE-NEXT: cset r0, eq
2499 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
2500 ; CHECK-MVE-NEXT: cmp r0, #0
2501 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
2502 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2503 ; CHECK-MVE-NEXT: cset r0, eq
2504 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
2505 ; CHECK-MVE-NEXT: cmp r0, #0
2506 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
2507 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
2508 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2509 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
2510 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2511 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
2512 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
2513 ; CHECK-MVE-NEXT: vins.f16 s0, s12
2514 ; CHECK-MVE-NEXT: cset r0, eq
2515 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
2516 ; CHECK-MVE-NEXT: cmp r0, #0
2517 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2518 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2519 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
2520 ; CHECK-MVE-NEXT: cset r0, eq
2521 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
2522 ; CHECK-MVE-NEXT: cmp r0, #0
2523 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
2524 ; CHECK-MVE-NEXT: vins.f16 s1, s4
2525 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
2526 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2527 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
2528 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2529 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
2530 ; CHECK-MVE-NEXT: cset r0, eq
2531 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
2532 ; CHECK-MVE-NEXT: cmp r0, #0
2533 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2534 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2535 ; CHECK-MVE-NEXT: cset r0, eq
2536 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
2537 ; CHECK-MVE-NEXT: cmp r0, #0
2538 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
2539 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
2540 ; CHECK-MVE-NEXT: vins.f16 s2, s4
2541 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
2542 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2543 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
2544 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2545 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
2546 ; CHECK-MVE-NEXT: cset r0, eq
2547 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
2548 ; CHECK-MVE-NEXT: cmp r0, #0
2549 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
2550 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2551 ; CHECK-MVE-NEXT: cset r0, eq
2552 ; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
2553 ; CHECK-MVE-NEXT: cmp r0, #0
2554 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
2555 ; CHECK-MVE-NEXT: vins.f16 s3, s4
2556 ; CHECK-MVE-NEXT: bx lr
2557 ;
2558 ; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16:
2559 ; CHECK-MVEFP: @ %bb.0: @ %entry
2560 ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
2561 ; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr
2562 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
2563 ; CHECK-MVEFP-NEXT: bx lr
2564 entry:
2565 %c = fcmp ueq <8 x half> zeroinitializer, %src
2566 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
2567 ret <8 x half> %s
2568 }
2570 define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
2571 ; CHECK-MVE-LABEL: vcmp_r_une_v8f16:
2572 ; CHECK-MVE: @ %bb.0: @ %entry
2573 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
2574 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
2575 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
2576 ; CHECK-MVE-NEXT: vmovx.f16 s13, s8
2577 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2578 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
2579 ; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s14
2580 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2581 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
2582 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
2583 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2584 ; CHECK-MVE-NEXT: vins.f16 s0, s12
2585 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2586 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
2587 ; CHECK-MVE-NEXT: vmovx.f16 s12, s9
2588 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
2589 ; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s8
2590 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2591 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
2592 ; CHECK-MVE-NEXT: vmovx.f16 s12, s10
2593 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
2594 ; CHECK-MVE-NEXT: vins.f16 s1, s4
2595 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
2596 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2597 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2598 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
2599 ; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s8
2600 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2601 ; CHECK-MVE-NEXT: vmovx.f16 s8, s11
2602 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
2603 ; CHECK-MVE-NEXT: vmovx.f16 s6, s7
2604 ; CHECK-MVE-NEXT: vins.f16 s2, s4
2605 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
2606 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2607 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2608 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
2609 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s6
2610 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2611 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
2612 ; CHECK-MVE-NEXT: vins.f16 s3, s4
2613 ; CHECK-MVE-NEXT: bx lr
2614 ;
2615 ; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16:
2616 ; CHECK-MVEFP: @ %bb.0: @ %entry
2617 ; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr
2618 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
2619 ; CHECK-MVEFP-NEXT: bx lr
2620 entry:
2621 %c = fcmp une <8 x half> zeroinitializer, %src
2622 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
2623 ret <8 x half> %s
2624 }
2626 define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
2627 ; CHECK-MVE-LABEL: vcmp_r_ugt_v8f16:
2628 ; CHECK-MVE: @ %bb.0: @ %entry
2629 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
2630 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
2631 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
2632 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
2633 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2634 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
2635 ; CHECK-MVE-NEXT: cset r0, lt
2636 ; CHECK-MVE-NEXT: cmp r0, #0
2637 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
2638 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2639 ; CHECK-MVE-NEXT: cset r0, lt
2640 ; CHECK-MVE-NEXT: cmp r0, #0
2641 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
2642 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
2643 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2644 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
2645 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2646 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
2647 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
2648 ; CHECK-MVE-NEXT: vins.f16 s0, s12
2649 ; CHECK-MVE-NEXT: cset r0, lt
2650 ; CHECK-MVE-NEXT: cmp r0, #0
2651 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2652 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2653 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
2654 ; CHECK-MVE-NEXT: cset r0, lt
2655 ; CHECK-MVE-NEXT: cmp r0, #0
2656 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
2657 ; CHECK-MVE-NEXT: vins.f16 s1, s4
2658 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
2659 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2660 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
2661 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2662 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
2663 ; CHECK-MVE-NEXT: cset r0, lt
2664 ; CHECK-MVE-NEXT: cmp r0, #0
2665 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2666 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2667 ; CHECK-MVE-NEXT: cset r0, lt
2668 ; CHECK-MVE-NEXT: cmp r0, #0
2669 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
2670 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
2671 ; CHECK-MVE-NEXT: vins.f16 s2, s4
2672 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
2673 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2674 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
2675 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2676 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
2677 ; CHECK-MVE-NEXT: cset r0, lt
2678 ; CHECK-MVE-NEXT: cmp r0, #0
2679 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
2680 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2681 ; CHECK-MVE-NEXT: cset r0, lt
2682 ; CHECK-MVE-NEXT: cmp r0, #0
2683 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
2684 ; CHECK-MVE-NEXT: vins.f16 s3, s4
2685 ; CHECK-MVE-NEXT: bx lr
2686 ;
2687 ; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16:
2688 ; CHECK-MVEFP: @ %bb.0: @ %entry
2689 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
2690 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
2691 ; CHECK-MVEFP-NEXT: bx lr
2692 entry:
2693 %c = fcmp ugt <8 x half> zeroinitializer, %src
2694 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
2695 ret <8 x half> %s
2696 }
2698 define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
2699 ; CHECK-MVE-LABEL: vcmp_r_uge_v8f16:
2700 ; CHECK-MVE: @ %bb.0: @ %entry
2701 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
2702 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
2703 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
2704 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
2705 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2706 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
2707 ; CHECK-MVE-NEXT: cset r0, le
2708 ; CHECK-MVE-NEXT: cmp r0, #0
2709 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
2710 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2711 ; CHECK-MVE-NEXT: cset r0, le
2712 ; CHECK-MVE-NEXT: cmp r0, #0
2713 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
2714 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
2715 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2716 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
2717 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2718 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
2719 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
2720 ; CHECK-MVE-NEXT: vins.f16 s0, s12
2721 ; CHECK-MVE-NEXT: cset r0, le
2722 ; CHECK-MVE-NEXT: cmp r0, #0
2723 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2724 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2725 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
2726 ; CHECK-MVE-NEXT: cset r0, le
2727 ; CHECK-MVE-NEXT: cmp r0, #0
2728 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
2729 ; CHECK-MVE-NEXT: vins.f16 s1, s4
2730 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
2731 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2732 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
2733 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2734 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
2735 ; CHECK-MVE-NEXT: cset r0, le
2736 ; CHECK-MVE-NEXT: cmp r0, #0
2737 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2738 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2739 ; CHECK-MVE-NEXT: cset r0, le
2740 ; CHECK-MVE-NEXT: cmp r0, #0
2741 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
2742 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
2743 ; CHECK-MVE-NEXT: vins.f16 s2, s4
2744 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
2745 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2746 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
2747 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2748 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
2749 ; CHECK-MVE-NEXT: cset r0, le
2750 ; CHECK-MVE-NEXT: cmp r0, #0
2751 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
2752 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2753 ; CHECK-MVE-NEXT: cset r0, le
2754 ; CHECK-MVE-NEXT: cmp r0, #0
2755 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
2756 ; CHECK-MVE-NEXT: vins.f16 s3, s4
2757 ; CHECK-MVE-NEXT: bx lr
2758 ;
2759 ; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16:
2760 ; CHECK-MVEFP: @ %bb.0: @ %entry
2761 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
2762 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
2763 ; CHECK-MVEFP-NEXT: bx lr
2764 entry:
2765 %c = fcmp uge <8 x half> zeroinitializer, %src
2766 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
2767 ret <8 x half> %s
2768 }
2770 define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
2771 ; CHECK-MVE-LABEL: vcmp_r_ult_v8f16:
2772 ; CHECK-MVE: @ %bb.0: @ %entry
2773 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
2774 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
2775 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
2776 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
2777 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2778 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
2779 ; CHECK-MVE-NEXT: cset r0, hi
2780 ; CHECK-MVE-NEXT: cmp r0, #0
2781 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
2782 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2783 ; CHECK-MVE-NEXT: cset r0, hi
2784 ; CHECK-MVE-NEXT: cmp r0, #0
2785 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
2786 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
2787 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2788 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
2789 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2790 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
2791 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
2792 ; CHECK-MVE-NEXT: vins.f16 s0, s12
2793 ; CHECK-MVE-NEXT: cset r0, hi
2794 ; CHECK-MVE-NEXT: cmp r0, #0
2795 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2796 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2797 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
2798 ; CHECK-MVE-NEXT: cset r0, hi
2799 ; CHECK-MVE-NEXT: cmp r0, #0
2800 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
2801 ; CHECK-MVE-NEXT: vins.f16 s1, s4
2802 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
2803 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2804 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
2805 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2806 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
2807 ; CHECK-MVE-NEXT: cset r0, hi
2808 ; CHECK-MVE-NEXT: cmp r0, #0
2809 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2810 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2811 ; CHECK-MVE-NEXT: cset r0, hi
2812 ; CHECK-MVE-NEXT: cmp r0, #0
2813 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
2814 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
2815 ; CHECK-MVE-NEXT: vins.f16 s2, s4
2816 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
2817 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2818 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
2819 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2820 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
2821 ; CHECK-MVE-NEXT: cset r0, hi
2822 ; CHECK-MVE-NEXT: cmp r0, #0
2823 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
2824 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2825 ; CHECK-MVE-NEXT: cset r0, hi
2826 ; CHECK-MVE-NEXT: cmp r0, #0
2827 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
2828 ; CHECK-MVE-NEXT: vins.f16 s3, s4
2829 ; CHECK-MVE-NEXT: bx lr
2830 ;
2831 ; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16:
2832 ; CHECK-MVEFP: @ %bb.0: @ %entry
2833 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
2834 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
2835 ; CHECK-MVEFP-NEXT: bx lr
2836 entry:
2837 %c = fcmp ult <8 x half> zeroinitializer, %src
2838 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
2839 ret <8 x half> %s
2840 }
2842 define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
2843 ; CHECK-MVE-LABEL: vcmp_r_ule_v8f16:
2844 ; CHECK-MVE: @ %bb.0: @ %entry
2845 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
2846 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
2847 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
2848 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
2849 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2850 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
2851 ; CHECK-MVE-NEXT: cset r0, pl
2852 ; CHECK-MVE-NEXT: cmp r0, #0
2853 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
2854 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2855 ; CHECK-MVE-NEXT: cset r0, pl
2856 ; CHECK-MVE-NEXT: cmp r0, #0
2857 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
2858 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
2859 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2860 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
2861 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2862 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
2863 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
2864 ; CHECK-MVE-NEXT: vins.f16 s0, s12
2865 ; CHECK-MVE-NEXT: cset r0, pl
2866 ; CHECK-MVE-NEXT: cmp r0, #0
2867 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2868 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2869 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
2870 ; CHECK-MVE-NEXT: cset r0, pl
2871 ; CHECK-MVE-NEXT: cmp r0, #0
2872 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
2873 ; CHECK-MVE-NEXT: vins.f16 s1, s4
2874 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
2875 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2876 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
2877 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2878 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
2879 ; CHECK-MVE-NEXT: cset r0, pl
2880 ; CHECK-MVE-NEXT: cmp r0, #0
2881 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2882 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2883 ; CHECK-MVE-NEXT: cset r0, pl
2884 ; CHECK-MVE-NEXT: cmp r0, #0
2885 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
2886 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
2887 ; CHECK-MVE-NEXT: vins.f16 s2, s4
2888 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
2889 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
2890 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
2891 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2892 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
2893 ; CHECK-MVE-NEXT: cset r0, pl
2894 ; CHECK-MVE-NEXT: cmp r0, #0
2895 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
2896 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2897 ; CHECK-MVE-NEXT: cset r0, pl
2898 ; CHECK-MVE-NEXT: cmp r0, #0
2899 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
2900 ; CHECK-MVE-NEXT: vins.f16 s3, s4
2901 ; CHECK-MVE-NEXT: bx lr
2902 ;
2903 ; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16:
2904 ; CHECK-MVEFP: @ %bb.0: @ %entry
2905 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
2906 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
2907 ; CHECK-MVEFP-NEXT: bx lr
2908 entry:
2909 %c = fcmp ule <8 x half> zeroinitializer, %src
2910 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
2911 ret <8 x half> %s
2912 }
2914 define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
2915 ; CHECK-MVE-LABEL: vcmp_r_ord_v8f16:
2916 ; CHECK-MVE: @ %bb.0: @ %entry
2917 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
2918 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
2919 ; CHECK-MVE-NEXT: vcmp.f16 s12, s12
2920 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
2921 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2922 ; CHECK-MVE-NEXT: vcmp.f16 s0, s0
2923 ; CHECK-MVE-NEXT: cset r0, vc
2924 ; CHECK-MVE-NEXT: cmp r0, #0
2925 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
2926 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2927 ; CHECK-MVE-NEXT: cset r0, vc
2928 ; CHECK-MVE-NEXT: cmp r0, #0
2929 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
2930 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
2931 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
2932 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
2933 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2934 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
2935 ; CHECK-MVE-NEXT: vcmp.f16 s1, s1
2936 ; CHECK-MVE-NEXT: vins.f16 s0, s12
2937 ; CHECK-MVE-NEXT: cset r0, vc
2938 ; CHECK-MVE-NEXT: cmp r0, #0
2939 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2940 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2941 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
2942 ; CHECK-MVE-NEXT: cset r0, vc
2943 ; CHECK-MVE-NEXT: cmp r0, #0
2944 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
2945 ; CHECK-MVE-NEXT: vins.f16 s1, s4
2946 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
2947 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
2948 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
2949 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2950 ; CHECK-MVE-NEXT: vcmp.f16 s2, s2
2951 ; CHECK-MVE-NEXT: cset r0, vc
2952 ; CHECK-MVE-NEXT: cmp r0, #0
2953 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
2954 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2955 ; CHECK-MVE-NEXT: cset r0, vc
2956 ; CHECK-MVE-NEXT: cmp r0, #0
2957 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
2958 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
2959 ; CHECK-MVE-NEXT: vins.f16 s2, s4
2960 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
2961 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
2962 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
2963 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2964 ; CHECK-MVE-NEXT: vcmp.f16 s3, s3
2965 ; CHECK-MVE-NEXT: cset r0, vc
2966 ; CHECK-MVE-NEXT: cmp r0, #0
2967 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
2968 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2969 ; CHECK-MVE-NEXT: cset r0, vc
2970 ; CHECK-MVE-NEXT: cmp r0, #0
2971 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
2972 ; CHECK-MVE-NEXT: vins.f16 s3, s4
2973 ; CHECK-MVE-NEXT: bx lr
2974 ;
2975 ; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16:
2976 ; CHECK-MVEFP: @ %bb.0: @ %entry
2977 ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
2978 ; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr
2979 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
2980 ; CHECK-MVEFP-NEXT: bx lr
2981 entry:
2982 %c = fcmp ord <8 x half> zeroinitializer, %src
2983 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
2984 ret <8 x half> %s
2985 }
2987 define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
2988 ; CHECK-MVE-LABEL: vcmp_r_uno_v8f16:
2989 ; CHECK-MVE: @ %bb.0: @ %entry
2990 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
2991 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
2992 ; CHECK-MVE-NEXT: vcmp.f16 s12, s12
2993 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
2994 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
2995 ; CHECK-MVE-NEXT: vcmp.f16 s0, s0
2996 ; CHECK-MVE-NEXT: cset r0, vs
2997 ; CHECK-MVE-NEXT: cmp r0, #0
2998 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
2999 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3000 ; CHECK-MVE-NEXT: cset r0, vs
3001 ; CHECK-MVE-NEXT: cmp r0, #0
3002 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
3003 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
3004 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
3005 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
3006 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3007 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
3008 ; CHECK-MVE-NEXT: vcmp.f16 s1, s1
3009 ; CHECK-MVE-NEXT: vins.f16 s0, s12
3010 ; CHECK-MVE-NEXT: cset r0, vs
3011 ; CHECK-MVE-NEXT: cmp r0, #0
3012 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
3013 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3014 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
3015 ; CHECK-MVE-NEXT: cset r0, vs
3016 ; CHECK-MVE-NEXT: cmp r0, #0
3017 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
3018 ; CHECK-MVE-NEXT: vins.f16 s1, s4
3019 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
3020 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
3021 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
3022 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3023 ; CHECK-MVE-NEXT: vcmp.f16 s2, s2
3024 ; CHECK-MVE-NEXT: cset r0, vs
3025 ; CHECK-MVE-NEXT: cmp r0, #0
3026 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
3027 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3028 ; CHECK-MVE-NEXT: cset r0, vs
3029 ; CHECK-MVE-NEXT: cmp r0, #0
3030 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
3031 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
3032 ; CHECK-MVE-NEXT: vins.f16 s2, s4
3033 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
3034 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
3035 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
3036 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3037 ; CHECK-MVE-NEXT: vcmp.f16 s3, s3
3038 ; CHECK-MVE-NEXT: cset r0, vs
3039 ; CHECK-MVE-NEXT: cmp r0, #0
3040 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
3041 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
3042 ; CHECK-MVE-NEXT: cset r0, vs
3043 ; CHECK-MVE-NEXT: cmp r0, #0
3044 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
3045 ; CHECK-MVE-NEXT: vins.f16 s3, s4
3046 ; CHECK-MVE-NEXT: bx lr
3047 ;
3048 ; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16:
3049 ; CHECK-MVEFP: @ %bb.0: @ %entry
3050 ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
3051 ; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr
3052 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
3053 ; CHECK-MVEFP-NEXT: bx lr
3054 entry:
3055 %c = fcmp uno <8 x half> zeroinitializer, %src
3056 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
3057 ret <8 x half> %s
3058 }