| blob | 2fa71386c8056dcbbd06a2dfee6dd1b22f4080f0 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=ALL,VZ
3 ; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=ALL,VZ
4 ; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx,-vzeroupper | FileCheck %s --check-prefixes=ALL,DISABLE-VZ
5 ; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mcpu=bdver2 | FileCheck %s --check-prefixes=ALL,BDVER2
6 ; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mcpu=btver2 | FileCheck %s --check-prefixes=ALL,BTVER2
8 declare dso_local i32 @foo()
9 declare dso_local <4 x float> @do_sse(<4 x float>)
10 declare dso_local <8 x float> @do_avx(<8 x float>)
11 declare dso_local <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone
12 @x = common dso_local global <4 x float> zeroinitializer, align 16
13 @g = common dso_local global <8 x float> zeroinitializer, align 32
15 ;; Basic checking - don't emit any vzeroupper instruction
17 define <4 x float> @test00(<4 x float> %a, <4 x float> %b) nounwind {
18 ; ALL-LABEL: test00:
19 ; ALL: # %bb.0:
20 ; ALL-NEXT: pushq %rax
21 ; ALL-NEXT: vaddps %xmm1, %xmm0, %xmm0
22 ; ALL-NEXT: callq do_sse
23 ; ALL-NEXT: popq %rax
24 ; ALL-NEXT: retq
25 %add.i = fadd <4 x float> %a, %b
26 %call3 = call <4 x float> @do_sse(<4 x float> %add.i) nounwind
27 ret <4 x float> %call3
28 }
30 ;; Check parameter 256-bit parameter passing
32 define <8 x float> @test01(<4 x float> %a, <4 x float> %b, <8 x float> %c) nounwind {
33 ; VZ-LABEL: test01:
34 ; VZ: # %bb.0:
35 ; VZ-NEXT: subq $40, %rsp
36 ; VZ-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill
37 ; VZ-NEXT: vmovaps x(%rip), %xmm0
38 ; VZ-NEXT: vzeroupper
39 ; VZ-NEXT: callq do_sse
40 ; VZ-NEXT: vmovaps %xmm0, x(%rip)
41 ; VZ-NEXT: callq do_sse
42 ; VZ-NEXT: vmovaps %xmm0, x(%rip)
43 ; VZ-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
44 ; VZ-NEXT: addq $40, %rsp
45 ; VZ-NEXT: retq
46 ;
47 ; DISABLE-VZ-LABEL: test01:
48 ; DISABLE-VZ: # %bb.0:
49 ; DISABLE-VZ-NEXT: subq $40, %rsp
50 ; DISABLE-VZ-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill
51 ; DISABLE-VZ-NEXT: vmovaps x(%rip), %xmm0
52 ; DISABLE-VZ-NEXT: callq do_sse
53 ; DISABLE-VZ-NEXT: vmovaps %xmm0, x(%rip)
54 ; DISABLE-VZ-NEXT: callq do_sse
55 ; DISABLE-VZ-NEXT: vmovaps %xmm0, x(%rip)
56 ; DISABLE-VZ-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
57 ; DISABLE-VZ-NEXT: addq $40, %rsp
58 ; DISABLE-VZ-NEXT: retq
59 ;
60 ; BDVER2-LABEL: test01:
61 ; BDVER2: # %bb.0:
62 ; BDVER2-NEXT: subq $40, %rsp
63 ; BDVER2-NEXT: vmovaps x(%rip), %xmm0
64 ; BDVER2-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill
65 ; BDVER2-NEXT: vzeroupper
66 ; BDVER2-NEXT: callq do_sse
67 ; BDVER2-NEXT: vmovaps %xmm0, x(%rip)
68 ; BDVER2-NEXT: callq do_sse
69 ; BDVER2-NEXT: vmovaps %xmm0, x(%rip)
70 ; BDVER2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
71 ; BDVER2-NEXT: addq $40, %rsp
72 ; BDVER2-NEXT: retq
73 ;
74 ; BTVER2-LABEL: test01:
75 ; BTVER2: # %bb.0:
76 ; BTVER2-NEXT: subq $40, %rsp
77 ; BTVER2-NEXT: vmovaps x(%rip), %xmm0
78 ; BTVER2-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill
79 ; BTVER2-NEXT: callq do_sse
80 ; BTVER2-NEXT: vmovaps %xmm0, x(%rip)
81 ; BTVER2-NEXT: callq do_sse
82 ; BTVER2-NEXT: vmovaps %xmm0, x(%rip)
83 ; BTVER2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
84 ; BTVER2-NEXT: addq $40, %rsp
85 ; BTVER2-NEXT: retq
86 %tmp = load <4 x float>, ptr @x, align 16
87 %call = tail call <4 x float> @do_sse(<4 x float> %tmp) nounwind
88 store <4 x float> %call, ptr @x, align 16
89 %call2 = tail call <4 x float> @do_sse(<4 x float> %call) nounwind
90 store <4 x float> %call2, ptr @x, align 16
91 ret <8 x float> %c
92 }
94 ;; Check that vzeroupper is emitted for tail calls.
96 define <4 x float> @test02(<8 x float> %a, <8 x float> %b) nounwind {
97 ; VZ-LABEL: test02:
98 ; VZ: # %bb.0:
99 ; VZ-NEXT: vaddps %xmm1, %xmm0, %xmm0
100 ; VZ-NEXT: vzeroupper
101 ; VZ-NEXT: jmp do_sse # TAILCALL
102 ;
103 ; DISABLE-VZ-LABEL: test02:
104 ; DISABLE-VZ: # %bb.0:
105 ; DISABLE-VZ-NEXT: vaddps %xmm1, %xmm0, %xmm0
106 ; DISABLE-VZ-NEXT: jmp do_sse # TAILCALL
107 ;
108 ; BDVER2-LABEL: test02:
109 ; BDVER2: # %bb.0:
110 ; BDVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0
111 ; BDVER2-NEXT: vzeroupper
112 ; BDVER2-NEXT: jmp do_sse # TAILCALL
113 ;
114 ; BTVER2-LABEL: test02:
115 ; BTVER2: # %bb.0:
116 ; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0
117 ; BTVER2-NEXT: jmp do_sse # TAILCALL
118 %add.i = fadd <8 x float> %a, %b
119 %add.low = call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %add.i, i8 0)
120 %call3 = tail call <4 x float> @do_sse(<4 x float> %add.low) nounwind
121 ret <4 x float> %call3
122 }
124 ;; Test the pass convergence and also that vzeroupper is only issued when necessary,
125 ;; for this function it should be only once
127 define <4 x float> @test03(<4 x float> %a, <4 x float> %b) nounwind {
128 ; VZ-LABEL: test03:
129 ; VZ: # %bb.0: # %entry
130 ; VZ-NEXT: pushq %rbx
131 ; VZ-NEXT: subq $16, %rsp
132 ; VZ-NEXT: vaddps %xmm1, %xmm0, %xmm0
133 ; VZ-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
134 ; VZ-NEXT: .p2align 4, 0x90
135 ; VZ-NEXT: .LBB3_1: # %while.cond
136 ; VZ-NEXT: # =>This Inner Loop Header: Depth=1
137 ; VZ-NEXT: callq foo
138 ; VZ-NEXT: testl %eax, %eax
139 ; VZ-NEXT: jne .LBB3_1
140 ; VZ-NEXT: # %bb.2: # %for.body.preheader
141 ; VZ-NEXT: movl $4, %ebx
142 ; VZ-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
143 ; VZ-NEXT: .p2align 4, 0x90
144 ; VZ-NEXT: .LBB3_3: # %for.body
145 ; VZ-NEXT: # =>This Inner Loop Header: Depth=1
146 ; VZ-NEXT: callq do_sse
147 ; VZ-NEXT: callq do_sse
148 ; VZ-NEXT: vmovaps g+16(%rip), %xmm0
149 ; VZ-NEXT: callq do_sse
150 ; VZ-NEXT: decl %ebx
151 ; VZ-NEXT: jne .LBB3_3
152 ; VZ-NEXT: # %bb.4: # %for.end
153 ; VZ-NEXT: addq $16, %rsp
154 ; VZ-NEXT: popq %rbx
155 ; VZ-NEXT: retq
156 ;
157 ; DISABLE-VZ-LABEL: test03:
158 ; DISABLE-VZ: # %bb.0: # %entry
159 ; DISABLE-VZ-NEXT: pushq %rbx
160 ; DISABLE-VZ-NEXT: subq $16, %rsp
161 ; DISABLE-VZ-NEXT: vaddps %xmm1, %xmm0, %xmm0
162 ; DISABLE-VZ-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
163 ; DISABLE-VZ-NEXT: .p2align 4, 0x90
164 ; DISABLE-VZ-NEXT: .LBB3_1: # %while.cond
165 ; DISABLE-VZ-NEXT: # =>This Inner Loop Header: Depth=1
166 ; DISABLE-VZ-NEXT: callq foo
167 ; DISABLE-VZ-NEXT: testl %eax, %eax
168 ; DISABLE-VZ-NEXT: jne .LBB3_1
169 ; DISABLE-VZ-NEXT: # %bb.2: # %for.body.preheader
170 ; DISABLE-VZ-NEXT: movl $4, %ebx
171 ; DISABLE-VZ-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
172 ; DISABLE-VZ-NEXT: .p2align 4, 0x90
173 ; DISABLE-VZ-NEXT: .LBB3_3: # %for.body
174 ; DISABLE-VZ-NEXT: # =>This Inner Loop Header: Depth=1
175 ; DISABLE-VZ-NEXT: callq do_sse
176 ; DISABLE-VZ-NEXT: callq do_sse
177 ; DISABLE-VZ-NEXT: vmovaps g+16(%rip), %xmm0
178 ; DISABLE-VZ-NEXT: callq do_sse
179 ; DISABLE-VZ-NEXT: decl %ebx
180 ; DISABLE-VZ-NEXT: jne .LBB3_3
181 ; DISABLE-VZ-NEXT: # %bb.4: # %for.end
182 ; DISABLE-VZ-NEXT: addq $16, %rsp
183 ; DISABLE-VZ-NEXT: popq %rbx
184 ; DISABLE-VZ-NEXT: retq
185 ;
186 ; BDVER2-LABEL: test03:
187 ; BDVER2: # %bb.0: # %entry
188 ; BDVER2-NEXT: pushq %rbx
189 ; BDVER2-NEXT: subq $16, %rsp
190 ; BDVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0
191 ; BDVER2-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
192 ; BDVER2-NEXT: .p2align 4, 0x90
193 ; BDVER2-NEXT: .LBB3_1: # %while.cond
194 ; BDVER2-NEXT: # =>This Inner Loop Header: Depth=1
195 ; BDVER2-NEXT: callq foo
196 ; BDVER2-NEXT: testl %eax, %eax
197 ; BDVER2-NEXT: jne .LBB3_1
198 ; BDVER2-NEXT: # %bb.2: # %for.body.preheader
199 ; BDVER2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
200 ; BDVER2-NEXT: movl $4, %ebx
201 ; BDVER2-NEXT: .p2align 4, 0x90
202 ; BDVER2-NEXT: .LBB3_3: # %for.body
203 ; BDVER2-NEXT: # =>This Inner Loop Header: Depth=1
204 ; BDVER2-NEXT: callq do_sse
205 ; BDVER2-NEXT: callq do_sse
206 ; BDVER2-NEXT: vmovaps g+16(%rip), %xmm0
207 ; BDVER2-NEXT: callq do_sse
208 ; BDVER2-NEXT: decl %ebx
209 ; BDVER2-NEXT: jne .LBB3_3
210 ; BDVER2-NEXT: # %bb.4: # %for.end
211 ; BDVER2-NEXT: addq $16, %rsp
212 ; BDVER2-NEXT: popq %rbx
213 ; BDVER2-NEXT: retq
214 ;
215 ; BTVER2-LABEL: test03:
216 ; BTVER2: # %bb.0: # %entry
217 ; BTVER2-NEXT: pushq %rbx
218 ; BTVER2-NEXT: subq $16, %rsp
219 ; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0
220 ; BTVER2-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
221 ; BTVER2-NEXT: .p2align 4, 0x90
222 ; BTVER2-NEXT: .LBB3_1: # %while.cond
223 ; BTVER2-NEXT: # =>This Inner Loop Header: Depth=1
224 ; BTVER2-NEXT: callq foo
225 ; BTVER2-NEXT: testl %eax, %eax
226 ; BTVER2-NEXT: jne .LBB3_1
227 ; BTVER2-NEXT: # %bb.2: # %for.body.preheader
228 ; BTVER2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
229 ; BTVER2-NEXT: movl $4, %ebx
230 ; BTVER2-NEXT: .p2align 4, 0x90
231 ; BTVER2-NEXT: .LBB3_3: # %for.body
232 ; BTVER2-NEXT: # =>This Inner Loop Header: Depth=1
233 ; BTVER2-NEXT: callq do_sse
234 ; BTVER2-NEXT: callq do_sse
235 ; BTVER2-NEXT: vmovaps g+16(%rip), %xmm0
236 ; BTVER2-NEXT: callq do_sse
237 ; BTVER2-NEXT: decl %ebx
238 ; BTVER2-NEXT: jne .LBB3_3
239 ; BTVER2-NEXT: # %bb.4: # %for.end
240 ; BTVER2-NEXT: addq $16, %rsp
241 ; BTVER2-NEXT: popq %rbx
242 ; BTVER2-NEXT: retq
243 entry:
244 %add.i = fadd <4 x float> %a, %b
245 br label %while.cond
247 while.cond:
248 %call = tail call i32 @foo()
249 %tobool = icmp eq i32 %call, 0
250 br i1 %tobool, label %for.body, label %while.cond
252 for.body:
253 %i.018 = phi i32 [ 0, %while.cond ], [ %1, %for.body ]
254 %c.017 = phi <4 x float> [ %add.i, %while.cond ], [ %call14, %for.body ]
255 %call5 = tail call <4 x float> @do_sse(<4 x float> %c.017) nounwind
256 %call7 = tail call <4 x float> @do_sse(<4 x float> %call5) nounwind
257 %tmp11 = load <8 x float>, ptr @g, align 32
258 %0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %tmp11, i8 1) nounwind
259 %call14 = tail call <4 x float> @do_sse(<4 x float> %0) nounwind
260 %1 = add nsw i32 %i.018, 1
261 %exitcond = icmp eq i32 %1, 4
262 br i1 %exitcond, label %for.end, label %for.body
264 for.end:
265 ret <4 x float> %call14
266 }
268 ;; Check that we also perform vzeroupper when we return from a function.
270 define <4 x float> @test04(<4 x float> %a, <4 x float> %b) nounwind {
271 ; VZ-LABEL: test04:
272 ; VZ: # %bb.0:
273 ; VZ-NEXT: pushq %rax
274 ; VZ-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
275 ; VZ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
276 ; VZ-NEXT: callq do_avx
277 ; VZ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
278 ; VZ-NEXT: popq %rax
279 ; VZ-NEXT: vzeroupper
280 ; VZ-NEXT: retq
281 ;
282 ; DISABLE-VZ-LABEL: test04:
283 ; DISABLE-VZ: # %bb.0:
284 ; DISABLE-VZ-NEXT: pushq %rax
285 ; DISABLE-VZ-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
286 ; DISABLE-VZ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
287 ; DISABLE-VZ-NEXT: callq do_avx
288 ; DISABLE-VZ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
289 ; DISABLE-VZ-NEXT: popq %rax
290 ; DISABLE-VZ-NEXT: retq
291 ;
292 ; BDVER2-LABEL: test04:
293 ; BDVER2: # %bb.0:
294 ; BDVER2-NEXT: pushq %rax
295 ; BDVER2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
296 ; BDVER2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
297 ; BDVER2-NEXT: callq do_avx
298 ; BDVER2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
299 ; BDVER2-NEXT: popq %rax
300 ; BDVER2-NEXT: vzeroupper
301 ; BDVER2-NEXT: retq
302 ;
303 ; BTVER2-LABEL: test04:
304 ; BTVER2: # %bb.0:
305 ; BTVER2-NEXT: pushq %rax
306 ; BTVER2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
307 ; BTVER2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
308 ; BTVER2-NEXT: callq do_avx
309 ; BTVER2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
310 ; BTVER2-NEXT: popq %rax
311 ; BTVER2-NEXT: retq
312 %shuf = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
313 %call = call <8 x float> @do_avx(<8 x float> %shuf) nounwind
314 %shuf2 = shufflevector <8 x float> %call, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
315 ret <4 x float> %shuf2
316 }