1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX512F,X86-AVX512F
3 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX512F,X64-AVX512F
4 ; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX512BW,X86-AVX512BW
5 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX512BW,X64-AVX512BW
7 define <16 x i32> @shuffle_v8i64(<16 x i32> %t0, <16 x i32> %t1) {
8 ; CHECK-LABEL: shuffle_v8i64:
9 ; CHECK: # %bb.0: # %entry
10 ; CHECK-NEXT: vpaddd %zmm1, %zmm0, %zmm2
11 ; CHECK-NEXT: vpsubd %zmm1, %zmm0, %zmm0
12 ; CHECK-NEXT: vshufps {{.*#+}} zmm0 = zmm2[0,1],zmm0[2,3],zmm2[4,5],zmm0[6,7],zmm2[8,9],zmm0[10,11],zmm2[12,13],zmm0[14,15]
13 ; CHECK-NEXT: ret{{[l|q]}}
15 %t2 = add nsw <16 x i32> %t0, %t1
16 %t3 = sub nsw <16 x i32> %t0, %t1
17 %t4 = shufflevector <16 x i32> %t2, <16 x i32> %t3, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 4, i32 5, i32 22, i32 23, i32 8, i32 9, i32 26, i32 27, i32 12, i32 13, i32 30, i32 31>
21 define <8 x i32> @shuffle_v4i64(<8 x i32> %t0, <8 x i32> %t1) {
22 ; CHECK-LABEL: shuffle_v4i64:
23 ; CHECK: # %bb.0: # %entry
24 ; CHECK-NEXT: vpaddd %ymm1, %ymm0, %ymm2
25 ; CHECK-NEXT: vpsubd %ymm1, %ymm0, %ymm0
26 ; CHECK-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1],ymm0[2,3],ymm2[4,5],ymm0[6,7]
27 ; CHECK-NEXT: ret{{[l|q]}}
29 %t2 = add nsw <8 x i32> %t0, %t1
30 %t3 = sub nsw <8 x i32> %t0, %t1
31 %t4 = shufflevector <8 x i32> %t2, <8 x i32> %t3, <8 x i32> <i32 0, i32 1, i32 10, i32 11, i32 4, i32 5, i32 14, i32 15>
35 define <4 x i32> @shuffle_v2i64(<4 x i32> %t0, <4 x i32> %t1) {
36 ; CHECK-LABEL: shuffle_v2i64:
37 ; CHECK: # %bb.0: # %entry
38 ; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm2
39 ; CHECK-NEXT: vpsubd %xmm1, %xmm0, %xmm0
40 ; CHECK-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3]
41 ; CHECK-NEXT: ret{{[l|q]}}
43 %t2 = add nsw <4 x i32> %t0, %t1
44 %t3 = sub nsw <4 x i32> %t0, %t1
45 %t4 = shufflevector <4 x i32> %t2, <4 x i32> %t3, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
49 define <2 x i32> @shuffle_v2i32(<2 x i32> %t0, <2 x i32> %t1) {
50 ; CHECK-LABEL: shuffle_v2i32:
51 ; CHECK: # %bb.0: # %entry
52 ; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm2
53 ; CHECK-NEXT: vpsubd %xmm1, %xmm0, %xmm0
54 ; CHECK-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2,3]
55 ; CHECK-NEXT: ret{{[l|q]}}
57 %t2 = add nsw <2 x i32> %t0, %t1
58 %t3 = sub nsw <2 x i32> %t0, %t1
59 %t4 = shufflevector <2 x i32> %t2, <2 x i32> %t3, <2 x i32> <i32 0, i32 3>
63 define <64 x i8> @addb_selectw_64xi8(<64 x i8> %t0, <64 x i8> %t1) {
64 ; X86-AVX512F-LABEL: addb_selectw_64xi8:
65 ; X86-AVX512F: # %bb.0:
66 ; X86-AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2
67 ; X86-AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm3
68 ; X86-AVX512F-NEXT: vpaddb %ymm2, %ymm3, %ymm2
69 ; X86-AVX512F-NEXT: vpaddb %ymm1, %ymm0, %ymm3
70 ; X86-AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
71 ; X86-AVX512F-NEXT: vpsubb %ymm1, %ymm0, %ymm0
72 ; X86-AVX512F-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}, %zmm2, %zmm0
73 ; X86-AVX512F-NEXT: retl
75 ; X64-AVX512F-LABEL: addb_selectw_64xi8:
76 ; X64-AVX512F: # %bb.0:
77 ; X64-AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2
78 ; X64-AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm3
79 ; X64-AVX512F-NEXT: vpaddb %ymm2, %ymm3, %ymm2
80 ; X64-AVX512F-NEXT: vpaddb %ymm1, %ymm0, %ymm3
81 ; X64-AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
82 ; X64-AVX512F-NEXT: vpsubb %ymm1, %ymm0, %ymm0
83 ; X64-AVX512F-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
84 ; X64-AVX512F-NEXT: retq
86 ; X86-AVX512BW-LABEL: addb_selectw_64xi8:
87 ; X86-AVX512BW: # %bb.0:
88 ; X86-AVX512BW-NEXT: vpaddb %zmm1, %zmm0, %zmm2
89 ; X86-AVX512BW-NEXT: movl $3, %eax
90 ; X86-AVX512BW-NEXT: kmovd %eax, %k0
91 ; X86-AVX512BW-NEXT: kmovd %k0, %k1
92 ; X86-AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm2 {%k1}
93 ; X86-AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm0
94 ; X86-AVX512BW-NEXT: retl
96 ; X64-AVX512BW-LABEL: addb_selectw_64xi8:
97 ; X64-AVX512BW: # %bb.0:
98 ; X64-AVX512BW-NEXT: vpaddb %zmm1, %zmm0, %zmm2
99 ; X64-AVX512BW-NEXT: movl $3, %eax
100 ; X64-AVX512BW-NEXT: kmovq %rax, %k1
101 ; X64-AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm2 {%k1}
102 ; X64-AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm0
103 ; X64-AVX512BW-NEXT: retq
104 %t2 = add nsw <64 x i8> %t0, %t1
105 %t3 = sub nsw <64 x i8> %t0, %t1
106 %t4 = shufflevector <64 x i8> %t2, <64 x i8> %t3, <64 x i32> <i32 64, i32 65, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
110 define <32 x i8> @addb_selectw_32xi8(<32 x i8> %t0, <32 x i8> %t1) {
111 ; CHECK-LABEL: addb_selectw_32xi8:
113 ; CHECK-NEXT: vpaddb %ymm1, %ymm0, %ymm2
114 ; CHECK-NEXT: vpsubb %xmm1, %xmm0, %xmm0
115 ; CHECK-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3,4,5,6,7]
116 ; CHECK-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm2[4,5,6,7]
117 ; CHECK-NEXT: ret{{[l|q]}}
118 %t2 = add nsw <32 x i8> %t0, %t1
119 %t3 = sub nsw <32 x i8> %t0, %t1
120 %t4 = shufflevector <32 x i8> %t2, <32 x i8> %t3, <32 x i32> <i32 32, i32 33, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
124 define <16 x i8> @addb_selectw_16xi8(<16 x i8> %t0, <16 x i8> %t1) {
125 ; CHECK-LABEL: addb_selectw_16xi8:
127 ; CHECK-NEXT: vpaddb %xmm1, %xmm0, %xmm2
128 ; CHECK-NEXT: vpsubb %xmm1, %xmm0, %xmm0
129 ; CHECK-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3,4,5,6,7]
130 ; CHECK-NEXT: ret{{[l|q]}}
131 %t2 = add nsw <16 x i8> %t0, %t1
132 %t3 = sub nsw <16 x i8> %t0, %t1
133 %t4 = shufflevector <16 x i8> %t2, <16 x i8> %t3, <16 x i32> <i32 16, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
137 define <8 x i8> @addb_selectw_8xi8(<8 x i8> %t0, <8 x i8> %t1) {
138 ; CHECK-LABEL: addb_selectw_8xi8:
140 ; CHECK-NEXT: vpaddb %xmm1, %xmm0, %xmm2
141 ; CHECK-NEXT: vpsubb %xmm1, %xmm0, %xmm0
142 ; CHECK-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3,4,5,6,7]
143 ; CHECK-NEXT: ret{{[l|q]}}
144 %t2 = add nsw <8 x i8> %t0, %t1
145 %t3 = sub nsw <8 x i8> %t0, %t1
146 %t4 = shufflevector <8 x i8> %t2, <8 x i8> %t3, <8 x i32> <i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
150 define <32 x i16> @addw_selectd_32xi16(<32 x i16> %t0, <32 x i16> %t1) {
151 ; AVX512F-LABEL: addw_selectd_32xi16:
153 ; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2
154 ; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm3
155 ; AVX512F-NEXT: vpaddw %ymm2, %ymm3, %ymm2
156 ; AVX512F-NEXT: vpaddw %ymm1, %ymm0, %ymm3
157 ; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
158 ; AVX512F-NEXT: vpsubw %ymm1, %ymm0, %ymm0
159 ; AVX512F-NEXT: movw $1, %ax
160 ; AVX512F-NEXT: kmovw %eax, %k1
161 ; AVX512F-NEXT: vmovdqa32 %zmm0, %zmm2 {%k1}
162 ; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm0
163 ; AVX512F-NEXT: ret{{[l|q]}}
165 ; AVX512BW-LABEL: addw_selectd_32xi16:
167 ; AVX512BW-NEXT: vpaddw %zmm1, %zmm0, %zmm2
168 ; AVX512BW-NEXT: movl $3, %eax
169 ; AVX512BW-NEXT: kmovd %eax, %k1
170 ; AVX512BW-NEXT: vpsubw %zmm1, %zmm0, %zmm2 {%k1}
171 ; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm0
172 ; AVX512BW-NEXT: ret{{[l|q]}}
173 %t2 = add nsw <32 x i16> %t0, %t1
174 %t3 = sub nsw <32 x i16> %t0, %t1
175 %t4 = shufflevector <32 x i16> %t2, <32 x i16> %t3, <32 x i32> <i32 32, i32 33, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
179 define <16 x i16> @addw_selectd_16xi16(<16 x i16> %t0, <16 x i16> %t1) {
180 ; CHECK-LABEL: addw_selectd_16xi16:
182 ; CHECK-NEXT: vpaddw %ymm1, %ymm0, %ymm2
183 ; CHECK-NEXT: vpsubw %ymm1, %ymm0, %ymm0
184 ; CHECK-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm2[1,2,3,4,5,6,7]
185 ; CHECK-NEXT: ret{{[l|q]}}
186 %t2 = add nsw <16 x i16> %t0, %t1
187 %t3 = sub nsw <16 x i16> %t0, %t1
188 %t4 = shufflevector <16 x i16> %t2, <16 x i16> %t3, <16 x i32> <i32 16, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
192 define <16 x i32> @addd_selectq_16xi32(<16 x i32> %t0, <16 x i32> %t1) {
193 ; AVX512F-LABEL: addd_selectq_16xi32:
195 ; AVX512F-NEXT: vpaddd %zmm1, %zmm0, %zmm2
196 ; AVX512F-NEXT: movw $3, %ax
197 ; AVX512F-NEXT: kmovw %eax, %k1
198 ; AVX512F-NEXT: vpsubd %zmm1, %zmm0, %zmm2 {%k1}
199 ; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm0
200 ; AVX512F-NEXT: ret{{[l|q]}}
202 ; AVX512BW-LABEL: addd_selectq_16xi32:
204 ; AVX512BW-NEXT: vpaddd %zmm1, %zmm0, %zmm2
205 ; AVX512BW-NEXT: movw $3, %ax
206 ; AVX512BW-NEXT: kmovd %eax, %k1
207 ; AVX512BW-NEXT: vpsubd %zmm1, %zmm0, %zmm2 {%k1}
208 ; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm0
209 ; AVX512BW-NEXT: ret{{[l|q]}}
210 %t2 = add nsw <16 x i32> %t0, %t1
211 %t3 = sub nsw <16 x i32> %t0, %t1
212 %t4 = shufflevector <16 x i32> %t2, <16 x i32> %t3, <16 x i32> <i32 16, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
217 define <8 x i32> @addd_selectq_8xi32(<8 x i32> %t0, <8 x i32> %t1) {
218 ; CHECK-LABEL: addd_selectq_8xi32:
220 ; CHECK-NEXT: vpaddd %ymm1, %ymm0, %ymm2
221 ; CHECK-NEXT: vpsubd %ymm1, %ymm0, %ymm0
222 ; CHECK-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm2[2,3,4,5,6,7]
223 ; CHECK-NEXT: ret{{[l|q]}}
224 %t2 = add nsw <8 x i32> %t0, %t1
225 %t3 = sub nsw <8 x i32> %t0, %t1
226 %t4 = shufflevector <8 x i32> %t2, <8 x i32> %t3, <8 x i32> <i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
231 define <4 x i32> @addd_selectq_4xi32(<4 x i32> %t0, <4 x i32> %t1) {
232 ; CHECK-LABEL: addd_selectq_4xi32:
234 ; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm2
235 ; CHECK-NEXT: vpsubd %xmm1, %xmm0, %xmm0
236 ; CHECK-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3]
237 ; CHECK-NEXT: ret{{[l|q]}}
238 %t2 = add nsw <4 x i32> %t0, %t1
239 %t3 = sub nsw <4 x i32> %t0, %t1
240 %t4 = shufflevector <4 x i32> %t2, <4 x i32> %t3, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
245 define <8 x i32> @shuffle_undef_8xi32(<8 x i32> %0, <8 x i32> %1) {
246 ; CHECK-LABEL: shuffle_undef_8xi32:
247 ; CHECK: # %bb.0: # %entry
248 ; CHECK-NEXT: vpaddd %ymm1, %ymm0, %ymm0
249 ; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
250 ; CHECK-NEXT: ret{{[l|q]}}
252 %2 = add <8 x i32> %0, %1
253 %3 = shufflevector <8 x i32> %2, <8 x i32> <i32 undef,i32 undef,i32 undef,i32 undef,i32 undef,i32 undef,i32 undef,i32 undef>, <8 x i32> <i32 0,i32 1,i32 4,i32 5,i32 2,i32 3,i32 6,i32 7>
257 define <16 x i16> @shuffle_undef_16xi16(<16 x i16> %0, <16 x i16> %1) {
258 ; CHECK-LABEL: shuffle_undef_16xi16:
259 ; CHECK: # %bb.0: # %entry
260 ; CHECK-NEXT: vpaddw %ymm1, %ymm0, %ymm0
261 ; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,1,0,3]
262 ; CHECK-NEXT: ret{{[l|q]}}
264 %2 = add <16 x i16> %0, %1
265 %3 = shufflevector <16 x i16> %2, <16 x i16> <i16 undef,i16 undef,i16 undef,i16 undef,i16 undef,i16 undef,i16 undef,i16 undef,i16 undef,i16 undef,i16 undef,i16 undef,i16 undef,i16 undef,i16 undef,i16 undef>, <16 x i32> <i32 8,i32 9,i32 10,i32 11,i32 4,i32 5,i32 6,i32 7,i32 0,i32 1,i32 2,i32 3,i32 12,i32 13,i32 14,i32 15>