clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_mullb.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // REQUIRES: aarch64-registered-target
   3
   4 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
   5 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
   6 // RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
   7 // RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
   8
   9 #include <arm_sve.h>
  10
  11 #ifdef SVE_OVERLOADED_FORMS
  12 // A simple used,unused... macro, long enough to represent any SVE builtin.
  13 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
  14 #else
  15 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
  16 #endif
  17
  18 // CHECK-LABEL: @test_svmullb_s16(
  19 // CHECK-NEXT:  entry:
  20 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.smullb.nxv8i16(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]])
  21 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  22 //
  23 // CPP-CHECK-LABEL: @_Z16test_svmullb_s16u10__SVInt8_tS_(
  24 // CPP-CHECK-NEXT:  entry:
  25 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.smullb.nxv8i16(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]])
  26 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  27 //
  28 svint16_t test_svmullb_s16(svint8_t op1, svint8_t op2)
  29 {
  30   return SVE_ACLE_FUNC(svmullb,_s16,,)(op1, op2);
  31 }
  32
  33 // CHECK-LABEL: @test_svmullb_s32(
  34 // CHECK-NEXT:  entry:
  35 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smullb.nxv4i32(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]])
  36 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  37 //
  38 // CPP-CHECK-LABEL: @_Z16test_svmullb_s32u11__SVInt16_tS_(
  39 // CPP-CHECK-NEXT:  entry:
  40 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smullb.nxv4i32(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]])
  41 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  42 //
  43 svint32_t test_svmullb_s32(svint16_t op1, svint16_t op2)
  44 {
  45   return SVE_ACLE_FUNC(svmullb,_s32,,)(op1, op2);
  46 }
  47
  48 // CHECK-LABEL: @test_svmullb_s64(
  49 // CHECK-NEXT:  entry:
  50 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.smullb.nxv2i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]])
  51 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
  52 //
  53 // CPP-CHECK-LABEL: @_Z16test_svmullb_s64u11__SVInt32_tS_(
  54 // CPP-CHECK-NEXT:  entry:
  55 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.smullb.nxv2i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]])
  56 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
  57 //
  58 svint64_t test_svmullb_s64(svint32_t op1, svint32_t op2)
  59 {
  60   return SVE_ACLE_FUNC(svmullb,_s64,,)(op1, op2);
  61 }
  62
  63 // CHECK-LABEL: @test_svmullb_u16(
  64 // CHECK-NEXT:  entry:
  65 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.umullb.nxv8i16(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]])
  66 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  67 //
  68 // CPP-CHECK-LABEL: @_Z16test_svmullb_u16u11__SVUint8_tS_(
  69 // CPP-CHECK-NEXT:  entry:
  70 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.umullb.nxv8i16(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]])
  71 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  72 //
  73 svuint16_t test_svmullb_u16(svuint8_t op1, svuint8_t op2)
  74 {
  75   return SVE_ACLE_FUNC(svmullb,_u16,,)(op1, op2);
  76 }
  77
  78 // CHECK-LABEL: @test_svmullb_u32(
  79 // CHECK-NEXT:  entry:
  80 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umullb.nxv4i32(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]])
  81 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  82 //
  83 // CPP-CHECK-LABEL: @_Z16test_svmullb_u32u12__SVUint16_tS_(
  84 // CPP-CHECK-NEXT:  entry:
  85 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umullb.nxv4i32(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]])
  86 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  87 //
  88 svuint32_t test_svmullb_u32(svuint16_t op1, svuint16_t op2)
  89 {
  90   return SVE_ACLE_FUNC(svmullb,_u32,,)(op1, op2);
  91 }
  92
  93 // CHECK-LABEL: @test_svmullb_u64(
  94 // CHECK-NEXT:  entry:
  95 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.umullb.nxv2i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]])
  96 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
  97 //
  98 // CPP-CHECK-LABEL: @_Z16test_svmullb_u64u12__SVUint32_tS_(
  99 // CPP-CHECK-NEXT:  entry:
 100 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.umullb.nxv2i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]])
 101 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 102 //
 103 svuint64_t test_svmullb_u64(svuint32_t op1, svuint32_t op2)
 104 {
 105   return SVE_ACLE_FUNC(svmullb,_u64,,)(op1, op2);
 106 }
 107
 108 // CHECK-LABEL: @test_svmullb_n_s16(
 109 // CHECK-NEXT:  entry:
 110 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP2:%.*]], i64 0
 111 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
 112 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.smullb.nxv8i16(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
 113 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 114 //
 115 // CPP-CHECK-LABEL: @_Z18test_svmullb_n_s16u10__SVInt8_ta(
 116 // CPP-CHECK-NEXT:  entry:
 117 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP2:%.*]], i64 0
 118 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
 119 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.smullb.nxv8i16(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
 120 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 121 //
 122 svint16_t test_svmullb_n_s16(svint8_t op1, int8_t op2)
 123 {
 124   return SVE_ACLE_FUNC(svmullb,_n_s16,,)(op1, op2);
 125 }
 126
 127 // CHECK-LABEL: @test_svmullb_n_s32(
 128 // CHECK-NEXT:  entry:
 129 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP2:%.*]], i64 0
 130 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
 131 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smullb.nxv4i32(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])
 132 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 133 //
 134 // CPP-CHECK-LABEL: @_Z18test_svmullb_n_s32u11__SVInt16_ts(
 135 // CPP-CHECK-NEXT:  entry:
 136 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP2:%.*]], i64 0
 137 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
 138 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smullb.nxv4i32(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])
 139 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 140 //
 141 svint32_t test_svmullb_n_s32(svint16_t op1, int16_t op2)
 142 {
 143   return SVE_ACLE_FUNC(svmullb,_n_s32,,)(op1, op2);
 144 }
 145
 146 // CHECK-LABEL: @test_svmullb_n_s64(
 147 // CHECK-NEXT:  entry:
 148 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP2:%.*]], i64 0
 149 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
 150 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.smullb.nxv2i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[DOTSPLAT]])
 151 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 152 //
 153 // CPP-CHECK-LABEL: @_Z18test_svmullb_n_s64u11__SVInt32_ti(
 154 // CPP-CHECK-NEXT:  entry:
 155 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP2:%.*]], i64 0
 156 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
 157 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.smullb.nxv2i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[DOTSPLAT]])
 158 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 159 //
 160 svint64_t test_svmullb_n_s64(svint32_t op1, int32_t op2)
 161 {
 162   return SVE_ACLE_FUNC(svmullb,_n_s64,,)(op1, op2);
 163 }
 164
 165 // CHECK-LABEL: @test_svmullb_n_u16(
 166 // CHECK-NEXT:  entry:
 167 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP2:%.*]], i64 0
 168 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
 169 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.umullb.nxv8i16(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
 170 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 171 //
 172 // CPP-CHECK-LABEL: @_Z18test_svmullb_n_u16u11__SVUint8_th(
 173 // CPP-CHECK-NEXT:  entry:
 174 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP2:%.*]], i64 0
 175 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
 176 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.umullb.nxv8i16(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
 177 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 178 //
 179 svuint16_t test_svmullb_n_u16(svuint8_t op1, uint8_t op2)
 180 {
 181   return SVE_ACLE_FUNC(svmullb,_n_u16,,)(op1, op2);
 182 }
 183
 184 // CHECK-LABEL: @test_svmullb_n_u32(
 185 // CHECK-NEXT:  entry:
 186 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP2:%.*]], i64 0
 187 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
 188 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umullb.nxv4i32(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])
 189 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 190 //
 191 // CPP-CHECK-LABEL: @_Z18test_svmullb_n_u32u12__SVUint16_tt(
 192 // CPP-CHECK-NEXT:  entry:
 193 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP2:%.*]], i64 0
 194 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
 195 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umullb.nxv4i32(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])
 196 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 197 //
 198 svuint32_t test_svmullb_n_u32(svuint16_t op1, uint16_t op2)
 199 {
 200   return SVE_ACLE_FUNC(svmullb,_n_u32,,)(op1, op2);
 201 }
 202
 203 // CHECK-LABEL: @test_svmullb_n_u64(
 204 // CHECK-NEXT:  entry:
 205 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP2:%.*]], i64 0
 206 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
 207 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.umullb.nxv2i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[DOTSPLAT]])
 208 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 209 //
 210 // CPP-CHECK-LABEL: @_Z18test_svmullb_n_u64u12__SVUint32_tj(
 211 // CPP-CHECK-NEXT:  entry:
 212 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP2:%.*]], i64 0
 213 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
 214 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.umullb.nxv2i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[DOTSPLAT]])
 215 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 216 //
 217 svuint64_t test_svmullb_n_u64(svuint32_t op1, uint32_t op2)
 218 {
 219   return SVE_ACLE_FUNC(svmullb,_n_u64,,)(op1, op2);
 220 }
 221
 222 // CHECK-LABEL: @test_svmullb_lane_s32(
 223 // CHECK-NEXT:  entry:
 224 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smullb.lane.nxv4i32(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 0)
 225 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 226 //
 227 // CPP-CHECK-LABEL: @_Z21test_svmullb_lane_s32u11__SVInt16_tS_(
 228 // CPP-CHECK-NEXT:  entry:
 229 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smullb.lane.nxv4i32(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 0)
 230 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 231 //
 232 svint32_t test_svmullb_lane_s32(svint16_t op1, svint16_t op2)
 233 {
 234   return SVE_ACLE_FUNC(svmullb_lane,_s32,,)(op1, op2, 0);
 235 }
 236
 237 // CHECK-LABEL: @test_svmullb_lane_s32_1(
 238 // CHECK-NEXT:  entry:
 239 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smullb.lane.nxv4i32(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 7)
 240 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 241 //
 242 // CPP-CHECK-LABEL: @_Z23test_svmullb_lane_s32_1u11__SVInt16_tS_(
 243 // CPP-CHECK-NEXT:  entry:
 244 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smullb.lane.nxv4i32(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 7)
 245 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 246 //
 247 svint32_t test_svmullb_lane_s32_1(svint16_t op1, svint16_t op2)
 248 {
 249   return SVE_ACLE_FUNC(svmullb_lane,_s32,,)(op1, op2, 7);
 250 }
 251
 252 // CHECK-LABEL: @test_svmullb_lane_s64(
 253 // CHECK-NEXT:  entry:
 254 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.smullb.lane.nxv2i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 0)
 255 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 256 //
 257 // CPP-CHECK-LABEL: @_Z21test_svmullb_lane_s64u11__SVInt32_tS_(
 258 // CPP-CHECK-NEXT:  entry:
 259 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.smullb.lane.nxv2i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 0)
 260 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 261 //
 262 svint64_t test_svmullb_lane_s64(svint32_t op1, svint32_t op2)
 263 {
 264   return SVE_ACLE_FUNC(svmullb_lane,_s64,,)(op1, op2, 0);
 265 }
 266
 267 // CHECK-LABEL: @test_svmullb_lane_s64_1(
 268 // CHECK-NEXT:  entry:
 269 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.smullb.lane.nxv2i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 3)
 270 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 271 //
 272 // CPP-CHECK-LABEL: @_Z23test_svmullb_lane_s64_1u11__SVInt32_tS_(
 273 // CPP-CHECK-NEXT:  entry:
 274 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.smullb.lane.nxv2i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 3)
 275 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 276 //
 277 svint64_t test_svmullb_lane_s64_1(svint32_t op1, svint32_t op2)
 278 {
 279   return SVE_ACLE_FUNC(svmullb_lane,_s64,,)(op1, op2, 3);
 280 }
 281
 282 // CHECK-LABEL: @test_svmullb_lane_u32(
 283 // CHECK-NEXT:  entry:
 284 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umullb.lane.nxv4i32(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 0)
 285 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 286 //
 287 // CPP-CHECK-LABEL: @_Z21test_svmullb_lane_u32u12__SVUint16_tS_(
 288 // CPP-CHECK-NEXT:  entry:
 289 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umullb.lane.nxv4i32(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 0)
 290 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 291 //
 292 svuint32_t test_svmullb_lane_u32(svuint16_t op1, svuint16_t op2)
 293 {
 294   return SVE_ACLE_FUNC(svmullb_lane,_u32,,)(op1, op2, 0);
 295 }
 296
 297 // CHECK-LABEL: @test_svmullb_lane_u32_1(
 298 // CHECK-NEXT:  entry:
 299 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umullb.lane.nxv4i32(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 7)
 300 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 301 //
 302 // CPP-CHECK-LABEL: @_Z23test_svmullb_lane_u32_1u12__SVUint16_tS_(
 303 // CPP-CHECK-NEXT:  entry:
 304 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umullb.lane.nxv4i32(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 7)
 305 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 306 //
 307 svuint32_t test_svmullb_lane_u32_1(svuint16_t op1, svuint16_t op2)
 308 {
 309   return SVE_ACLE_FUNC(svmullb_lane,_u32,,)(op1, op2, 7);
 310 }
 311
 312 // CHECK-LABEL: @test_svmullb_lane_u64(
 313 // CHECK-NEXT:  entry:
 314 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.umullb.lane.nxv2i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 0)
 315 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 316 //
 317 // CPP-CHECK-LABEL: @_Z21test_svmullb_lane_u64u12__SVUint32_tS_(
 318 // CPP-CHECK-NEXT:  entry:
 319 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.umullb.lane.nxv2i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 0)
 320 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 321 //
 322 svuint64_t test_svmullb_lane_u64(svuint32_t op1, svuint32_t op2)
 323 {
 324   return SVE_ACLE_FUNC(svmullb_lane,_u64,,)(op1, op2, 0);
 325 }
 326
 327 // CHECK-LABEL: @test_svmullb_lane_u64_1(
 328 // CHECK-NEXT:  entry:
 329 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.umullb.lane.nxv2i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 3)
 330 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 331 //
 332 // CPP-CHECK-LABEL: @_Z23test_svmullb_lane_u64_1u12__SVUint32_tS_(
 333 // CPP-CHECK-NEXT:  entry:
 334 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.umullb.lane.nxv2i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 3)
 335 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 336 //
 337 svuint64_t test_svmullb_lane_u64_1(svuint32_t op1, svuint32_t op2)
 338 {
 339   return SVE_ACLE_FUNC(svmullb_lane,_u64,,)(op1, op2, 3);
 340 }