clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s
   3 // RUN: %clang_cc1 -DPOLYMORPHIC -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s
   4
   5 // REQUIRES: aarch64-registered-target || arm-registered-target
   6
   7 #include <arm_mve.h>
   8
   9 // CHECK-LABEL: @test_vcvtaq_s16_f16(
  10 // CHECK-NEXT:  entry:
  11 // CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 0, <8 x half> [[A:%.*]])
  12 // CHECK-NEXT:    ret <8 x i16> [[TMP0]]
  13 //
  14 int16x8_t test_vcvtaq_s16_f16(float16x8_t a)
  15 {
  16     return vcvtaq_s16_f16(a);
  17 }
  18
  19 // CHECK-LABEL: @test_vcvtaq_s32_f32(
  20 // CHECK-NEXT:  entry:
  21 // CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 0, <4 x float> [[A:%.*]])
  22 // CHECK-NEXT:    ret <4 x i32> [[TMP0]]
  23 //
  24 int32x4_t test_vcvtaq_s32_f32(float32x4_t a)
  25 {
  26     return vcvtaq_s32_f32(a);
  27 }
  28
  29 // CHECK-LABEL: @test_vcvtaq_u16_f16(
  30 // CHECK-NEXT:  entry:
  31 // CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 1, <8 x half> [[A:%.*]])
  32 // CHECK-NEXT:    ret <8 x i16> [[TMP0]]
  33 //
  34 uint16x8_t test_vcvtaq_u16_f16(float16x8_t a)
  35 {
  36     return vcvtaq_u16_f16(a);
  37 }
  38
  39 // CHECK-LABEL: @test_vcvtaq_u32_f32(
  40 // CHECK-NEXT:  entry:
  41 // CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 1, <4 x float> [[A:%.*]])
  42 // CHECK-NEXT:    ret <4 x i32> [[TMP0]]
  43 //
  44 uint32x4_t test_vcvtaq_u32_f32(float32x4_t a)
  45 {
  46     return vcvtaq_u32_f32(a);
  47 }
  48
  49 // CHECK-LABEL: @test_vcvtmq_s16_f16(
  50 // CHECK-NEXT:  entry:
  51 // CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 0, <8 x half> [[A:%.*]])
  52 // CHECK-NEXT:    ret <8 x i16> [[TMP0]]
  53 //
  54 int16x8_t test_vcvtmq_s16_f16(float16x8_t a)
  55 {
  56     return vcvtmq_s16_f16(a);
  57 }
  58
  59 // CHECK-LABEL: @test_vcvtmq_s32_f32(
  60 // CHECK-NEXT:  entry:
  61 // CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 0, <4 x float> [[A:%.*]])
  62 // CHECK-NEXT:    ret <4 x i32> [[TMP0]]
  63 //
  64 int32x4_t test_vcvtmq_s32_f32(float32x4_t a)
  65 {
  66     return vcvtmq_s32_f32(a);
  67 }
  68
  69 // CHECK-LABEL: @test_vcvtmq_u16_f16(
  70 // CHECK-NEXT:  entry:
  71 // CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 1, <8 x half> [[A:%.*]])
  72 // CHECK-NEXT:    ret <8 x i16> [[TMP0]]
  73 //
  74 uint16x8_t test_vcvtmq_u16_f16(float16x8_t a)
  75 {
  76     return vcvtmq_u16_f16(a);
  77 }
  78
  79 // CHECK-LABEL: @test_vcvtmq_u32_f32(
  80 // CHECK-NEXT:  entry:
  81 // CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 1, <4 x float> [[A:%.*]])
  82 // CHECK-NEXT:    ret <4 x i32> [[TMP0]]
  83 //
  84 uint32x4_t test_vcvtmq_u32_f32(float32x4_t a)
  85 {
  86     return vcvtmq_u32_f32(a);
  87 }
  88
  89 // CHECK-LABEL: @test_vcvtnq_s16_f16(
  90 // CHECK-NEXT:  entry:
  91 // CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 0, <8 x half> [[A:%.*]])
  92 // CHECK-NEXT:    ret <8 x i16> [[TMP0]]
  93 //
  94 int16x8_t test_vcvtnq_s16_f16(float16x8_t a)
  95 {
  96     return vcvtnq_s16_f16(a);
  97 }
  98
  99 // CHECK-LABEL: @test_vcvtnq_s32_f32(
 100 // CHECK-NEXT:  entry:
 101 // CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 0, <4 x float> [[A:%.*]])
 102 // CHECK-NEXT:    ret <4 x i32> [[TMP0]]
 103 //
 104 int32x4_t test_vcvtnq_s32_f32(float32x4_t a)
 105 {
 106     return vcvtnq_s32_f32(a);
 107 }
 108
 109 // CHECK-LABEL: @test_vcvtnq_u16_f16(
 110 // CHECK-NEXT:  entry:
 111 // CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 1, <8 x half> [[A:%.*]])
 112 // CHECK-NEXT:    ret <8 x i16> [[TMP0]]
 113 //
 114 uint16x8_t test_vcvtnq_u16_f16(float16x8_t a)
 115 {
 116     return vcvtnq_u16_f16(a);
 117 }
 118
 119 // CHECK-LABEL: @test_vcvtnq_u32_f32(
 120 // CHECK-NEXT:  entry:
 121 // CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 1, <4 x float> [[A:%.*]])
 122 // CHECK-NEXT:    ret <4 x i32> [[TMP0]]
 123 //
 124 uint32x4_t test_vcvtnq_u32_f32(float32x4_t a)
 125 {
 126     return vcvtnq_u32_f32(a);
 127 }
 128
 129 // CHECK-LABEL: @test_vcvtpq_s16_f16(
 130 // CHECK-NEXT:  entry:
 131 // CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 0, <8 x half> [[A:%.*]])
 132 // CHECK-NEXT:    ret <8 x i16> [[TMP0]]
 133 //
 134 int16x8_t test_vcvtpq_s16_f16(float16x8_t a)
 135 {
 136     return vcvtpq_s16_f16(a);
 137 }
 138
 139 // CHECK-LABEL: @test_vcvtpq_s32_f32(
 140 // CHECK-NEXT:  entry:
 141 // CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 0, <4 x float> [[A:%.*]])
 142 // CHECK-NEXT:    ret <4 x i32> [[TMP0]]
 143 //
 144 int32x4_t test_vcvtpq_s32_f32(float32x4_t a)
 145 {
 146     return vcvtpq_s32_f32(a);
 147 }
 148
 149 // CHECK-LABEL: @test_vcvtpq_u16_f16(
 150 // CHECK-NEXT:  entry:
 151 // CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 1, <8 x half> [[A:%.*]])
 152 // CHECK-NEXT:    ret <8 x i16> [[TMP0]]
 153 //
 154 uint16x8_t test_vcvtpq_u16_f16(float16x8_t a)
 155 {
 156     return vcvtpq_u16_f16(a);
 157 }
 158
 159 // CHECK-LABEL: @test_vcvtpq_u32_f32(
 160 // CHECK-NEXT:  entry:
 161 // CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 1, <4 x float> [[A:%.*]])
 162 // CHECK-NEXT:    ret <4 x i32> [[TMP0]]
 163 //
 164 uint32x4_t test_vcvtpq_u32_f32(float32x4_t a)
 165 {
 166     return vcvtpq_u32_f32(a);
 167 }
 168
 169 // CHECK-LABEL: @test_vcvtaq_m_s16_f16(
 170 // CHECK-NEXT:  entry:
 171 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 172 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 173 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
 174 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 175 //
 176 int16x8_t test_vcvtaq_m_s16_f16(int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 177 {
 178 #ifdef POLYMORPHIC
 179     return vcvtaq_m(inactive, a, p);
 180 #else /* POLYMORPHIC */
 181     return vcvtaq_m_s16_f16(inactive, a, p);
 182 #endif /* POLYMORPHIC */
 183 }
 184
 185 // CHECK-LABEL: @test_vcvtaq_m_s32_f32(
 186 // CHECK-NEXT:  entry:
 187 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 188 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 189 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
 190 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 191 //
 192 int32x4_t test_vcvtaq_m_s32_f32(int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 193 {
 194 #ifdef POLYMORPHIC
 195     return vcvtaq_m(inactive, a, p);
 196 #else /* POLYMORPHIC */
 197     return vcvtaq_m_s32_f32(inactive, a, p);
 198 #endif /* POLYMORPHIC */
 199 }
 200
 201 // CHECK-LABEL: @test_vcvtaq_m_u16_f16(
 202 // CHECK-NEXT:  entry:
 203 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 204 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 205 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
 206 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 207 //
 208 uint16x8_t test_vcvtaq_m_u16_f16(uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 209 {
 210 #ifdef POLYMORPHIC
 211     return vcvtaq_m(inactive, a, p);
 212 #else /* POLYMORPHIC */
 213     return vcvtaq_m_u16_f16(inactive, a, p);
 214 #endif /* POLYMORPHIC */
 215 }
 216
 217 // CHECK-LABEL: @test_vcvtaq_m_u32_f32(
 218 // CHECK-NEXT:  entry:
 219 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 220 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 221 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
 222 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 223 //
 224 uint32x4_t test_vcvtaq_m_u32_f32(uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 225 {
 226 #ifdef POLYMORPHIC
 227     return vcvtaq_m(inactive, a, p);
 228 #else /* POLYMORPHIC */
 229     return vcvtaq_m_u32_f32(inactive, a, p);
 230 #endif /* POLYMORPHIC */
 231 }
 232
 233 // CHECK-LABEL: @test_vcvtmq_m_s16_f16(
 234 // CHECK-NEXT:  entry:
 235 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 236 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 237 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtm.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
 238 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 239 //
 240 int16x8_t test_vcvtmq_m_s16_f16(int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 241 {
 242 #ifdef POLYMORPHIC
 243     return vcvtmq_m(inactive, a, p);
 244 #else /* POLYMORPHIC */
 245     return vcvtmq_m_s16_f16(inactive, a, p);
 246 #endif /* POLYMORPHIC */
 247 }
 248
 249 // CHECK-LABEL: @test_vcvtmq_m_s32_f32(
 250 // CHECK-NEXT:  entry:
 251 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 252 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 253 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtm.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
 254 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 255 //
 256 int32x4_t test_vcvtmq_m_s32_f32(int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 257 {
 258 #ifdef POLYMORPHIC
 259     return vcvtmq_m(inactive, a, p);
 260 #else /* POLYMORPHIC */
 261     return vcvtmq_m_s32_f32(inactive, a, p);
 262 #endif /* POLYMORPHIC */
 263 }
 264
 265 // CHECK-LABEL: @test_vcvtmq_m_u16_f16(
 266 // CHECK-NEXT:  entry:
 267 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 268 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 269 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtm.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
 270 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 271 //
 272 uint16x8_t test_vcvtmq_m_u16_f16(uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 273 {
 274 #ifdef POLYMORPHIC
 275     return vcvtmq_m(inactive, a, p);
 276 #else /* POLYMORPHIC */
 277     return vcvtmq_m_u16_f16(inactive, a, p);
 278 #endif /* POLYMORPHIC */
 279 }
 280
 281 // CHECK-LABEL: @test_vcvtmq_m_u32_f32(
 282 // CHECK-NEXT:  entry:
 283 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 284 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 285 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtm.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
 286 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 287 //
 288 uint32x4_t test_vcvtmq_m_u32_f32(uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 289 {
 290 #ifdef POLYMORPHIC
 291     return vcvtmq_m(inactive, a, p);
 292 #else /* POLYMORPHIC */
 293     return vcvtmq_m_u32_f32(inactive, a, p);
 294 #endif /* POLYMORPHIC */
 295 }
 296
 297 // CHECK-LABEL: @test_vcvtnq_m_s16_f16(
 298 // CHECK-NEXT:  entry:
 299 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 300 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 301 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtn.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
 302 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 303 //
 304 int16x8_t test_vcvtnq_m_s16_f16(int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 305 {
 306 #ifdef POLYMORPHIC
 307     return vcvtnq_m(inactive, a, p);
 308 #else /* POLYMORPHIC */
 309     return vcvtnq_m_s16_f16(inactive, a, p);
 310 #endif /* POLYMORPHIC */
 311 }
 312
 313 // CHECK-LABEL: @test_vcvtnq_m_s32_f32(
 314 // CHECK-NEXT:  entry:
 315 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 316 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 317 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtn.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
 318 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 319 //
 320 int32x4_t test_vcvtnq_m_s32_f32(int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 321 {
 322 #ifdef POLYMORPHIC
 323     return vcvtnq_m(inactive, a, p);
 324 #else /* POLYMORPHIC */
 325     return vcvtnq_m_s32_f32(inactive, a, p);
 326 #endif /* POLYMORPHIC */
 327 }
 328
 329 // CHECK-LABEL: @test_vcvtnq_m_u16_f16(
 330 // CHECK-NEXT:  entry:
 331 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 332 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 333 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtn.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
 334 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 335 //
 336 uint16x8_t test_vcvtnq_m_u16_f16(uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 337 {
 338 #ifdef POLYMORPHIC
 339     return vcvtnq_m(inactive, a, p);
 340 #else /* POLYMORPHIC */
 341     return vcvtnq_m_u16_f16(inactive, a, p);
 342 #endif /* POLYMORPHIC */
 343 }
 344
 345 // CHECK-LABEL: @test_vcvtnq_m_u32_f32(
 346 // CHECK-NEXT:  entry:
 347 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 348 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 349 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtn.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
 350 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 351 //
 352 uint32x4_t test_vcvtnq_m_u32_f32(uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 353 {
 354 #ifdef POLYMORPHIC
 355     return vcvtnq_m(inactive, a, p);
 356 #else /* POLYMORPHIC */
 357     return vcvtnq_m_u32_f32(inactive, a, p);
 358 #endif /* POLYMORPHIC */
 359 }
 360
 361 // CHECK-LABEL: @test_vcvtpq_m_s16_f16(
 362 // CHECK-NEXT:  entry:
 363 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 364 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 365 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtp.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
 366 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 367 //
 368 int16x8_t test_vcvtpq_m_s16_f16(int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 369 {
 370 #ifdef POLYMORPHIC
 371     return vcvtpq_m(inactive, a, p);
 372 #else /* POLYMORPHIC */
 373     return vcvtpq_m_s16_f16(inactive, a, p);
 374 #endif /* POLYMORPHIC */
 375 }
 376
 377 // CHECK-LABEL: @test_vcvtpq_m_s32_f32(
 378 // CHECK-NEXT:  entry:
 379 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 380 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 381 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtp.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
 382 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 383 //
 384 int32x4_t test_vcvtpq_m_s32_f32(int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 385 {
 386 #ifdef POLYMORPHIC
 387     return vcvtpq_m(inactive, a, p);
 388 #else /* POLYMORPHIC */
 389     return vcvtpq_m_s32_f32(inactive, a, p);
 390 #endif /* POLYMORPHIC */
 391 }
 392
 393 // CHECK-LABEL: @test_vcvtpq_m_u16_f16(
 394 // CHECK-NEXT:  entry:
 395 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 396 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 397 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtp.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
 398 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 399 //
 400 uint16x8_t test_vcvtpq_m_u16_f16(uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 401 {
 402 #ifdef POLYMORPHIC
 403     return vcvtpq_m(inactive, a, p);
 404 #else /* POLYMORPHIC */
 405     return vcvtpq_m_u16_f16(inactive, a, p);
 406 #endif /* POLYMORPHIC */
 407 }
 408
 409 // CHECK-LABEL: @test_vcvtpq_m_u32_f32(
 410 // CHECK-NEXT:  entry:
 411 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 412 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 413 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtp.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
 414 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 415 //
 416 uint32x4_t test_vcvtpq_m_u32_f32(uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 417 {
 418 #ifdef POLYMORPHIC
 419     return vcvtpq_m(inactive, a, p);
 420 #else /* POLYMORPHIC */
 421     return vcvtpq_m_u32_f32(inactive, a, p);
 422 #endif /* POLYMORPHIC */
 423 }
 424
 425 // CHECK-LABEL: @test_vcvtaq_x_s16_f16(
 426 // CHECK-NEXT:  entry:
 427 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 428 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 429 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> undef, <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
 430 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 431 //
 432 int16x8_t test_vcvtaq_x_s16_f16(float16x8_t a, mve_pred16_t p)
 433 {
 434     return vcvtaq_x_s16_f16(a, p);
 435 }
 436
 437 // CHECK-LABEL: @test_vcvtaq_x_s32_f32(
 438 // CHECK-NEXT:  entry:
 439 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 440 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 441 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> undef, <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
 442 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 443 //
 444 int32x4_t test_vcvtaq_x_s32_f32(float32x4_t a, mve_pred16_t p)
 445 {
 446     return vcvtaq_x_s32_f32(a, p);
 447 }
 448
 449 // CHECK-LABEL: @test_vcvtaq_x_u16_f16(
 450 // CHECK-NEXT:  entry:
 451 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 452 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 453 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> undef, <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
 454 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 455 //
 456 uint16x8_t test_vcvtaq_x_u16_f16(float16x8_t a, mve_pred16_t p)
 457 {
 458     return vcvtaq_x_u16_f16(a, p);
 459 }
 460
 461 // CHECK-LABEL: @test_vcvtaq_x_u32_f32(
 462 // CHECK-NEXT:  entry:
 463 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 464 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 465 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> undef, <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
 466 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 467 //
 468 uint32x4_t test_vcvtaq_x_u32_f32(float32x4_t a, mve_pred16_t p)
 469 {
 470     return vcvtaq_x_u32_f32(a, p);
 471 }
 472
 473 // CHECK-LABEL: @test_vcvtmq_x_s16_f16(
 474 // CHECK-NEXT:  entry:
 475 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 476 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 477 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtm.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> undef, <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
 478 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 479 //
 480 int16x8_t test_vcvtmq_x_s16_f16(float16x8_t a, mve_pred16_t p)
 481 {
 482     return vcvtmq_x_s16_f16(a, p);
 483 }
 484
 485 // CHECK-LABEL: @test_vcvtmq_x_s32_f32(
 486 // CHECK-NEXT:  entry:
 487 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 488 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 489 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtm.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> undef, <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
 490 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 491 //
 492 int32x4_t test_vcvtmq_x_s32_f32(float32x4_t a, mve_pred16_t p)
 493 {
 494     return vcvtmq_x_s32_f32(a, p);
 495 }
 496
 497 // CHECK-LABEL: @test_vcvtmq_x_u16_f16(
 498 // CHECK-NEXT:  entry:
 499 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 500 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 501 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtm.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> undef, <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
 502 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 503 //
 504 uint16x8_t test_vcvtmq_x_u16_f16(float16x8_t a, mve_pred16_t p)
 505 {
 506     return vcvtmq_x_u16_f16(a, p);
 507 }
 508
 509 // CHECK-LABEL: @test_vcvtmq_x_u32_f32(
 510 // CHECK-NEXT:  entry:
 511 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 512 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 513 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtm.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> undef, <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
 514 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 515 //
 516 uint32x4_t test_vcvtmq_x_u32_f32(float32x4_t a, mve_pred16_t p)
 517 {
 518     return vcvtmq_x_u32_f32(a, p);
 519 }
 520
 521 // CHECK-LABEL: @test_vcvtnq_x_s16_f16(
 522 // CHECK-NEXT:  entry:
 523 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 524 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 525 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtn.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> undef, <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
 526 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 527 //
 528 int16x8_t test_vcvtnq_x_s16_f16(float16x8_t a, mve_pred16_t p)
 529 {
 530     return vcvtnq_x_s16_f16(a, p);
 531 }
 532
 533 // CHECK-LABEL: @test_vcvtnq_x_s32_f32(
 534 // CHECK-NEXT:  entry:
 535 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 536 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 537 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtn.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> undef, <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
 538 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 539 //
 540 int32x4_t test_vcvtnq_x_s32_f32(float32x4_t a, mve_pred16_t p)
 541 {
 542     return vcvtnq_x_s32_f32(a, p);
 543 }
 544
 545 // CHECK-LABEL: @test_vcvtnq_x_u16_f16(
 546 // CHECK-NEXT:  entry:
 547 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 548 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 549 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtn.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> undef, <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
 550 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 551 //
 552 uint16x8_t test_vcvtnq_x_u16_f16(float16x8_t a, mve_pred16_t p)
 553 {
 554     return vcvtnq_x_u16_f16(a, p);
 555 }
 556
 557 // CHECK-LABEL: @test_vcvtnq_x_u32_f32(
 558 // CHECK-NEXT:  entry:
 559 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 560 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 561 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtn.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> undef, <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
 562 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 563 //
 564 uint32x4_t test_vcvtnq_x_u32_f32(float32x4_t a, mve_pred16_t p)
 565 {
 566     return vcvtnq_x_u32_f32(a, p);
 567 }
 568
 569 // CHECK-LABEL: @test_vcvtpq_x_s16_f16(
 570 // CHECK-NEXT:  entry:
 571 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 572 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 573 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtp.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> undef, <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
 574 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 575 //
 576 int16x8_t test_vcvtpq_x_s16_f16(float16x8_t a, mve_pred16_t p)
 577 {
 578     return vcvtpq_x_s16_f16(a, p);
 579 }
 580
 581 // CHECK-LABEL: @test_vcvtpq_x_s32_f32(
 582 // CHECK-NEXT:  entry:
 583 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 584 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 585 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtp.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> undef, <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
 586 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 587 //
 588 int32x4_t test_vcvtpq_x_s32_f32(float32x4_t a, mve_pred16_t p)
 589 {
 590     return vcvtpq_x_s32_f32(a, p);
 591 }
 592
 593 // CHECK-LABEL: @test_vcvtpq_x_u16_f16(
 594 // CHECK-NEXT:  entry:
 595 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 596 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 597 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtp.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> undef, <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
 598 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 599 //
 600 uint16x8_t test_vcvtpq_x_u16_f16(float16x8_t a, mve_pred16_t p)
 601 {
 602     return vcvtpq_x_u16_f16(a, p);
 603 }
 604
 605 // CHECK-LABEL: @test_vcvtpq_x_u32_f32(
 606 // CHECK-NEXT:  entry:
 607 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 608 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 609 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtp.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> undef, <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
 610 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 611 //
 612 uint32x4_t test_vcvtpq_x_u32_f32(float32x4_t a, mve_pred16_t p)
 613 {
 614     return vcvtpq_x_u32_f32(a, p);
 615 }
 616