clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s
   3 // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s
   4
   5 // REQUIRES: aarch64-registered-target || arm-registered-target
   6
   7 #include <arm_mve.h>
   8
   9 // CHECK-LABEL: @test_vhcaddq_rot90_s8(
  10 // CHECK-NEXT:  entry:
  11 // CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 0, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])
  12 // CHECK-NEXT:    ret <16 x i8> [[TMP0]]
  13 //
  14 int8x16_t test_vhcaddq_rot90_s8(int8x16_t a, int8x16_t b)
  15 {
  16 #ifdef POLYMORPHIC
  17     return vhcaddq_rot90(a, b);
  18 #else
  19     return vhcaddq_rot90_s8(a, b);
  20 #endif
  21 }
  22
  23 // CHECK-LABEL: @test_vhcaddq_rot90_s16(
  24 // CHECK-NEXT:  entry:
  25 // CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])
  26 // CHECK-NEXT:    ret <8 x i16> [[TMP0]]
  27 //
  28 int16x8_t test_vhcaddq_rot90_s16(int16x8_t a, int16x8_t b)
  29 {
  30 #ifdef POLYMORPHIC
  31     return vhcaddq_rot90(a, b);
  32 #else
  33     return vhcaddq_rot90_s16(a, b);
  34 #endif
  35 }
  36
  37 // CHECK-LABEL: @test_vhcaddq_rot90_s32(
  38 // CHECK-NEXT:  entry:
  39 // CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])
  40 // CHECK-NEXT:    ret <4 x i32> [[TMP0]]
  41 //
  42 int32x4_t test_vhcaddq_rot90_s32(int32x4_t a, int32x4_t b)
  43 {
  44 #ifdef POLYMORPHIC
  45     return vhcaddq_rot90(a, b);
  46 #else
  47     return vhcaddq_rot90_s32(a, b);
  48 #endif
  49 }
  50
  51 // CHECK-LABEL: @test_vhcaddq_rot270_s8(
  52 // CHECK-NEXT:  entry:
  53 // CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 1, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])
  54 // CHECK-NEXT:    ret <16 x i8> [[TMP0]]
  55 //
  56 int8x16_t test_vhcaddq_rot270_s8(int8x16_t a, int8x16_t b)
  57 {
  58 #ifdef POLYMORPHIC
  59     return vhcaddq_rot270(a, b);
  60 #else
  61     return vhcaddq_rot270_s8(a, b);
  62 #endif
  63 }
  64
  65 // CHECK-LABEL: @test_vhcaddq_rot270_s16(
  66 // CHECK-NEXT:  entry:
  67 // CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 1, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])
  68 // CHECK-NEXT:    ret <8 x i16> [[TMP0]]
  69 //
  70 int16x8_t test_vhcaddq_rot270_s16(int16x8_t a, int16x8_t b)
  71 {
  72 #ifdef POLYMORPHIC
  73     return vhcaddq_rot270(a, b);
  74 #else
  75     return vhcaddq_rot270_s16(a, b);
  76 #endif
  77 }
  78
  79 // CHECK-LABEL: @test_vhcaddq_rot270_s32(
  80 // CHECK-NEXT:  entry:
  81 // CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])
  82 // CHECK-NEXT:    ret <4 x i32> [[TMP0]]
  83 //
  84 int32x4_t test_vhcaddq_rot270_s32(int32x4_t a, int32x4_t b)
  85 {
  86 #ifdef POLYMORPHIC
  87     return vhcaddq_rot270(a, b);
  88 #else
  89     return vhcaddq_rot270_s32(a, b);
  90 #endif
  91 }
  92
  93 // CHECK-LABEL: @test_vhcaddq_rot90_x_s8(
  94 // CHECK-NEXT:  entry:
  95 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
  96 // CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
  97 // CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])
  98 // CHECK-NEXT:    ret <16 x i8> [[TMP2]]
  99 //
 100 int8x16_t test_vhcaddq_rot90_x_s8(int8x16_t a, int8x16_t b, mve_pred16_t p)
 101 {
 102 #ifdef POLYMORPHIC
 103     return vhcaddq_rot90_x(a, b, p);
 104 #else
 105     return vhcaddq_rot90_x_s8(a, b, p);
 106 #endif
 107 }
 108
 109 // CHECK-LABEL: @test_vhcaddq_rot90_x_s16(
 110 // CHECK-NEXT:  entry:
 111 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 112 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 113 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> undef, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])
 114 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 115 //
 116 int16x8_t test_vhcaddq_rot90_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
 117 {
 118 #ifdef POLYMORPHIC
 119     return vhcaddq_rot90_x(a, b, p);
 120 #else
 121     return vhcaddq_rot90_x_s16(a, b, p);
 122 #endif
 123 }
 124
 125 // CHECK-LABEL: @test_vhcaddq_rot90_x_s32(
 126 // CHECK-NEXT:  entry:
 127 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 128 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 129 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> undef, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])
 130 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 131 //
 132 int32x4_t test_vhcaddq_rot90_x_s32(int32x4_t a, int32x4_t b, mve_pred16_t p)
 133 {
 134 #ifdef POLYMORPHIC
 135     return vhcaddq_rot90_x(a, b, p);
 136 #else
 137     return vhcaddq_rot90_x_s32(a, b, p);
 138 #endif
 139 }
 140
 141 // CHECK-LABEL: @test_vhcaddq_rot270_x_s8(
 142 // CHECK-NEXT:  entry:
 143 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 144 // CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
 145 // CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])
 146 // CHECK-NEXT:    ret <16 x i8> [[TMP2]]
 147 //
 148 int8x16_t test_vhcaddq_rot270_x_s8(int8x16_t a, int8x16_t b, mve_pred16_t p)
 149 {
 150 #ifdef POLYMORPHIC
 151     return vhcaddq_rot270_x(a, b, p);
 152 #else
 153     return vhcaddq_rot270_x_s8(a, b, p);
 154 #endif
 155 }
 156
 157 // CHECK-LABEL: @test_vhcaddq_rot270_x_s16(
 158 // CHECK-NEXT:  entry:
 159 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 160 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 161 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> undef, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])
 162 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 163 //
 164 int16x8_t test_vhcaddq_rot270_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
 165 {
 166 #ifdef POLYMORPHIC
 167     return vhcaddq_rot270_x(a, b, p);
 168 #else
 169     return vhcaddq_rot270_x_s16(a, b, p);
 170 #endif
 171 }
 172
 173 // CHECK-LABEL: @test_vhcaddq_rot270_x_s32(
 174 // CHECK-NEXT:  entry:
 175 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 176 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 177 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> undef, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])
 178 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 179 //
 180 int32x4_t test_vhcaddq_rot270_x_s32(int32x4_t a, int32x4_t b, mve_pred16_t p)
 181 {
 182 #ifdef POLYMORPHIC
 183     return vhcaddq_rot270_x(a, b, p);
 184 #else
 185     return vhcaddq_rot270_x_s32(a, b, p);
 186 #endif
 187 }
 188
 189 // CHECK-LABEL: @test_vhcaddq_rot90_m_s8(
 190 // CHECK-NEXT:  entry:
 191 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 192 // CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
 193 // CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])
 194 // CHECK-NEXT:    ret <16 x i8> [[TMP2]]
 195 //
 196 int8x16_t test_vhcaddq_rot90_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 197 {
 198 #ifdef POLYMORPHIC
 199     return vhcaddq_rot90_m(inactive, a, b, p);
 200 #else
 201     return vhcaddq_rot90_m_s8(inactive, a, b, p);
 202 #endif
 203 }
 204
 205 // CHECK-LABEL: @test_vhcaddq_rot90_m_s16(
 206 // CHECK-NEXT:  entry:
 207 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 208 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 209 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])
 210 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 211 //
 212 int16x8_t test_vhcaddq_rot90_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 213 {
 214 #ifdef POLYMORPHIC
 215     return vhcaddq_rot90_m(inactive, a, b, p);
 216 #else
 217     return vhcaddq_rot90_m_s16(inactive, a, b, p);
 218 #endif
 219 }
 220
 221 // CHECK-LABEL: @test_vhcaddq_rot90_m_s32(
 222 // CHECK-NEXT:  entry:
 223 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 224 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 225 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])
 226 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 227 //
 228 int32x4_t test_vhcaddq_rot90_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 229 {
 230 #ifdef POLYMORPHIC
 231     return vhcaddq_rot90_m(inactive, a, b, p);
 232 #else
 233     return vhcaddq_rot90_m_s32(inactive, a, b, p);
 234 #endif
 235 }
 236
 237 // CHECK-LABEL: @test_vhcaddq_rot270_m_s8(
 238 // CHECK-NEXT:  entry:
 239 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 240 // CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
 241 // CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])
 242 // CHECK-NEXT:    ret <16 x i8> [[TMP2]]
 243 //
 244 int8x16_t test_vhcaddq_rot270_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 245 {
 246 #ifdef POLYMORPHIC
 247     return vhcaddq_rot270_m(inactive, a, b, p);
 248 #else
 249     return vhcaddq_rot270_m_s8(inactive, a, b, p);
 250 #endif
 251 }
 252
 253 // CHECK-LABEL: @test_vhcaddq_rot270_m_s16(
 254 // CHECK-NEXT:  entry:
 255 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 256 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
 257 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])
 258 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 259 //
 260 int16x8_t test_vhcaddq_rot270_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 261 {
 262 #ifdef POLYMORPHIC
 263     return vhcaddq_rot270_m(inactive, a, b, p);
 264 #else
 265     return vhcaddq_rot270_m_s16(inactive, a, b, p);
 266 #endif
 267 }
 268
 269 // CHECK-LABEL: @test_vhcaddq_rot270_m_s32(
 270 // CHECK-NEXT:  entry:
 271 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 272 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
 273 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])
 274 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 275 //
 276 int32x4_t test_vhcaddq_rot270_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 277 {
 278 #ifdef POLYMORPHIC
 279     return vhcaddq_rot270_m(inactive, a, b, p);
 280 #else
 281     return vhcaddq_rot270_m_s32(inactive, a, b, p);
 282 #endif
 283 }