clang/test/CodeGen/arm-mve-intrinsics/vldr.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s
   3
   4 // REQUIRES: aarch64-registered-target || arm-registered-target
   5
   6 #include <arm_mve.h>
   7
   8 // CHECK-LABEL: @test_vldrwq_gather_base_wb_s32(
   9 // CHECK-NEXT:  entry:
  10 // CHECK-NEXT:    [[TMP0:%.*]] = load <4 x i32>, ptr [[ADDR:%.*]], align 8
  11 // CHECK-NEXT:    [[TMP1:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32> [[TMP0]], i32 80)
  12 // CHECK-NEXT:    [[TMP2:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[TMP1]], 1
  13 // CHECK-NEXT:    store <4 x i32> [[TMP2]], ptr [[ADDR]], align 8
  14 // CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[TMP1]], 0
  15 // CHECK-NEXT:    ret <4 x i32> [[TMP3]]
  16 //
  17 int32x4_t test_vldrwq_gather_base_wb_s32(uint32x4_t *addr)
  18 {
  19     return vldrwq_gather_base_wb_s32(addr, 0x50);
  20 }
  21
  22 // CHECK-LABEL: @test_vldrwq_gather_base_wb_f32(
  23 // CHECK-NEXT:  entry:
  24 // CHECK-NEXT:    [[TMP0:%.*]] = load <4 x i32>, ptr [[ADDR:%.*]], align 8
  25 // CHECK-NEXT:    [[TMP1:%.*]] = call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32> [[TMP0]], i32 64)
  26 // CHECK-NEXT:    [[TMP2:%.*]] = extractvalue { <4 x float>, <4 x i32> } [[TMP1]], 1
  27 // CHECK-NEXT:    store <4 x i32> [[TMP2]], ptr [[ADDR]], align 8
  28 // CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <4 x float>, <4 x i32> } [[TMP1]], 0
  29 // CHECK-NEXT:    ret <4 x float> [[TMP3]]
  30 //
  31 float32x4_t test_vldrwq_gather_base_wb_f32(uint32x4_t *addr)
  32 {
  33     return vldrwq_gather_base_wb_f32(addr, 0x40);
  34 }
  35
  36 // CHECK-LABEL: @test_vldrdq_gather_base_wb_z_u64(
  37 // CHECK-NEXT:  entry:
  38 // CHECK-NEXT:    [[TMP0:%.*]] = load <2 x i64>, ptr [[ADDR:%.*]], align 8
  39 // CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
  40 // CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 [[TMP1]])
  41 // CHECK-NEXT:    [[TMP3:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64> [[TMP0]], i32 656, <2 x i1> [[TMP2]])
  42 // CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[TMP3]], 1
  43 // CHECK-NEXT:    store <2 x i64> [[TMP4]], ptr [[ADDR]], align 8
  44 // CHECK-NEXT:    [[TMP5:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[TMP3]], 0
  45 // CHECK-NEXT:    ret <2 x i64> [[TMP5]]
  46 //
  47 uint64x2_t test_vldrdq_gather_base_wb_z_u64(uint64x2_t *addr, mve_pred16_t p)
  48 {
  49     return vldrdq_gather_base_wb_z_u64(addr, 0x290, p);
  50 }