clang/test/OpenMP/ordered_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK1
   3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
   4 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK1
   5
   6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK1-IRBUILDER
   7 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
   8 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK1-IRBUILDER
   9
  10 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -fopenmp-version=45 -o - | FileCheck %s --check-prefixes=CHECK3
  11 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -fopenmp-version=45 -o %t %s
  12 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK3
  13
  14 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -fopenmp-version=45 -o - | FileCheck %s --check-prefixes=CHECK3-IRBUILDER
  15 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -fopenmp-version=45 -o %t %s
  16 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK3-IRBUILDER
  17
  18 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5
  19 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
  20 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5
  21 // expected-no-diagnostics
  22 #ifndef HEADER
  23 #define HEADER
  24
  25 void static_not_chunked(float *a, float *b, float *c, float *d) {
  26   #pragma omp for schedule(static) ordered
  27
  28 // Loop header
  29
  30   for (int i = 32000000; i > 33; i += -7) {
  31 // Start of body: calculate i from IV:
  32
  33 // ... start of ordered region ...
  34 // ... loop body ...
  35 // End of body: store into a[i]:
  36 // ... end of ordered region ...
  37     #pragma omp ordered
  38     a[i] = b[i] * c[i] * d[i];
  39   }
  40 }
  41
  42 void dynamic1(float *a, float *b, float *c, float *d) {
  43   #pragma omp for schedule(dynamic) ordered
  44
  45 // Loop header
  46
  47   for (unsigned long long i = 131071; i < 2147483647; i += 127) {
  48 // Start of body: calculate i from IV:
  49
  50 // ... start of ordered region ...
  51 // ... loop body ...
  52 // End of body: store into a[i]:
  53 // ... end of ordered region ...
  54     #pragma omp ordered threads
  55     a[i] = b[i] * c[i] * d[i];
  56
  57 // ... end iteration for ordered loop ...
  58   }
  59 }
  60
  61 void test_auto(float *a, float *b, float *c, float *d) {
  62   unsigned int x = 0;
  63   unsigned int y = 0;
  64   #pragma omp for schedule(auto) collapse(2) ordered
  65
  66 // Loop header
  67
  68 // FIXME: When the iteration count of some nested loop is not a known constant,
  69 // we should pre-calculate it, like we do for the total number of iterations!
  70   for (char i = static_cast<char>(y); i <= '9'; ++i)
  71     for (x = 11; x > 0; --x) {
  72 // Start of body: indices are calculated from IV:
  73
  74 // ... start of ordered region ...
  75 // ... loop body ...
  76 // End of body: store into a[i]:
  77 // ... end of ordered region ...
  78     #pragma omp ordered
  79     a[i] = b[i] * c[i] * d[i];
  80
  81 // ... end iteration for ordered loop ...
  82   }
  83 }
  84
  85 void runtime(float *a, float *b, float *c, float *d) {
  86   int x = 0;
  87   #pragma omp for collapse(2) schedule(runtime) ordered
  88
  89 // Loop header
  90
  91   for (unsigned char i = '0' ; i <= '9'; ++i)
  92     for (x = -10; x < 10; ++x) {
  93 // Start of body: indices are calculated from IV:
  94
  95 // ... start of ordered region ...
  96 // ... loop body ...
  97 // End of body: store into a[i]:
  98 // ... end of ordered region ...
  99     #pragma omp ordered threads
 100     a[i] = b[i] * c[i] * d[i];
 101
 102 // ... end iteration for ordered loop ...
 103   }
 104 }
 105
 106 float f[10];
 107 void foo_simd(int low, int up) {
 108 #pragma omp simd
 109   for (int i = low; i < up; ++i) {
 110     f[i] = 0.0;
 111 #pragma omp ordered simd
 112     f[i] = 1.0;
 113   }
 114 #pragma omp for simd ordered
 115   for (int i = low; i < up; ++i) {
 116     f[i] = 0.0;
 117 #pragma omp ordered simd
 118     f[i] = 1.0;
 119   }
 120 }
 121
 122
 123 #endif // HEADER
 124
 125 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
 126 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
 127 // CHECK1-NEXT:  entry:
 128 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 129 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 130 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 131 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 132 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 133 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 134 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 135 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 136 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 137 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 138 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 139 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
 140 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 141 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 142 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 143 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 144 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 145 // CHECK1-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
 146 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 147 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 148 // CHECK1-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1)
 149 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 150 // CHECK1:       omp.dispatch.cond:
 151 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 152 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
 153 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 154 // CHECK1:       omp.dispatch.body:
 155 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 156 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_IV]], align 4
 157 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 158 // CHECK1:       omp.inner.for.cond:
 159 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 160 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 161 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]]
 162 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 163 // CHECK1:       omp.inner.for.body:
 164 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 165 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP5]], 7
 166 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
 167 // CHECK1-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
 168 // CHECK1-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
 169 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 170 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4
 171 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64
 172 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i64 [[IDXPROM]]
 173 // CHECK1-NEXT:    [[TMP8:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 174 // CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 175 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[I]], align 4
 176 // CHECK1-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i64
 177 // CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i64 [[IDXPROM1]]
 178 // CHECK1-NEXT:    [[TMP11:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
 179 // CHECK1-NEXT:    [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]]
 180 // CHECK1-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 181 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
 182 // CHECK1-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64
 183 // CHECK1-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM4]]
 184 // CHECK1-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX5]], align 4
 185 // CHECK1-NEXT:    [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]]
 186 // CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 187 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
 188 // CHECK1-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64
 189 // CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM7]]
 190 // CHECK1-NEXT:    store float [[MUL6]], ptr [[ARRAYIDX8]], align 4
 191 // CHECK1-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
 192 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 193 // CHECK1:       omp.body.continue:
 194 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 195 // CHECK1:       omp.inner.for.inc:
 196 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 197 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP17]], 1
 198 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
 199 // CHECK1-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP0]])
 200 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 201 // CHECK1:       omp.inner.for.end:
 202 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 203 // CHECK1:       omp.dispatch.inc:
 204 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
 205 // CHECK1:       omp.dispatch.end:
 206 // CHECK1-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])
 207 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP0]])
 208 // CHECK1-NEXT:    ret void
 209 //
 210 //
 211 // CHECK1-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_
 212 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 213 // CHECK1-NEXT:  entry:
 214 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 215 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 216 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 217 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 218 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
 219 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i64, align 8
 220 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
 221 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
 222 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
 223 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 224 // CHECK1-NEXT:    [[I:%.*]] = alloca i64, align 8
 225 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 226 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 227 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 228 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 229 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 230 // CHECK1-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
 231 // CHECK1-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8
 232 // CHECK1-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
 233 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 234 // CHECK1-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB1]], i32 [[TMP0]], i32 1073741891, i64 0, i64 16908287, i64 1, i64 1)
 235 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 236 // CHECK1:       omp.dispatch.cond:
 237 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 238 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
 239 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 240 // CHECK1:       omp.dispatch.body:
 241 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
 242 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[DOTOMP_IV]], align 8
 243 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 244 // CHECK1:       omp.inner.for.cond:
 245 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 246 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 247 // CHECK1-NEXT:    [[ADD:%.*]] = add i64 [[TMP4]], 1
 248 // CHECK1-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]]
 249 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 250 // CHECK1:       omp.inner.for.body:
 251 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 252 // CHECK1-NEXT:    [[MUL:%.*]] = mul i64 [[TMP5]], 127
 253 // CHECK1-NEXT:    [[ADD1:%.*]] = add i64 131071, [[MUL]]
 254 // CHECK1-NEXT:    store i64 [[ADD1]], ptr [[I]], align 8
 255 // CHECK1-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
 256 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 257 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[I]], align 8
 258 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP6]], i64 [[TMP7]]
 259 // CHECK1-NEXT:    [[TMP8:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 260 // CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 261 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[I]], align 8
 262 // CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP9]], i64 [[TMP10]]
 263 // CHECK1-NEXT:    [[TMP11:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
 264 // CHECK1-NEXT:    [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]]
 265 // CHECK1-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 266 // CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[I]], align 8
 267 // CHECK1-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP12]], i64 [[TMP13]]
 268 // CHECK1-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
 269 // CHECK1-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]]
 270 // CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 271 // CHECK1-NEXT:    [[TMP16:%.*]] = load i64, ptr [[I]], align 8
 272 // CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP15]], i64 [[TMP16]]
 273 // CHECK1-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4
 274 // CHECK1-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
 275 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 276 // CHECK1:       omp.body.continue:
 277 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 278 // CHECK1:       omp.inner.for.inc:
 279 // CHECK1-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 280 // CHECK1-NEXT:    [[ADD7:%.*]] = add i64 [[TMP17]], 1
 281 // CHECK1-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8
 282 // CHECK1-NEXT:    call void @__kmpc_dispatch_fini_8u(ptr @[[GLOB1]], i32 [[TMP0]])
 283 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 284 // CHECK1:       omp.inner.for.end:
 285 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 286 // CHECK1:       omp.dispatch.inc:
 287 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
 288 // CHECK1:       omp.dispatch.end:
 289 // CHECK1-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])
 290 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])
 291 // CHECK1-NEXT:    ret void
 292 //
 293 //
 294 // CHECK1-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_
 295 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 296 // CHECK1-NEXT:  entry:
 297 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 298 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 299 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 300 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 301 // CHECK1-NEXT:    [[X:%.*]] = alloca i32, align 4
 302 // CHECK1-NEXT:    [[Y:%.*]] = alloca i32, align 4
 303 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
 304 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i8, align 1
 305 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 306 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
 307 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
 308 // CHECK1-NEXT:    [[I:%.*]] = alloca i8, align 1
 309 // CHECK1-NEXT:    [[X6:%.*]] = alloca i32, align 4
 310 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
 311 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
 312 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
 313 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 314 // CHECK1-NEXT:    [[I8:%.*]] = alloca i8, align 1
 315 // CHECK1-NEXT:    [[X9:%.*]] = alloca i32, align 4
 316 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 317 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 318 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 319 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 320 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 321 // CHECK1-NEXT:    store i32 0, ptr [[X]], align 4
 322 // CHECK1-NEXT:    store i32 0, ptr [[Y]], align 4
 323 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[Y]], align 4
 324 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP1]] to i8
 325 // CHECK1-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1
 326 // CHECK1-NEXT:    [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 327 // CHECK1-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
 328 // CHECK1-NEXT:    [[SUB:%.*]] = sub i32 57, [[CONV3]]
 329 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], 1
 330 // CHECK1-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
 331 // CHECK1-NEXT:    [[CONV4:%.*]] = zext i32 [[DIV]] to i64
 332 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11
 333 // CHECK1-NEXT:    [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1
 334 // CHECK1-NEXT:    store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8
 335 // CHECK1-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 336 // CHECK1-NEXT:    store i8 [[TMP3]], ptr [[I]], align 1
 337 // CHECK1-NEXT:    store i32 11, ptr [[X6]], align 4
 338 // CHECK1-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 339 // CHECK1-NEXT:    [[CONV7:%.*]] = sext i8 [[TMP4]] to i32
 340 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57
 341 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
 342 // CHECK1:       omp.precond.then:
 343 // CHECK1-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
 344 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
 345 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[DOTOMP_UB]], align 8
 346 // CHECK1-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
 347 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 348 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
 349 // CHECK1-NEXT:    call void @__kmpc_dispatch_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 1073741894, i64 0, i64 [[TMP6]], i64 1, i64 1)
 350 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 351 // CHECK1:       omp.dispatch.cond:
 352 // CHECK1-NEXT:    [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 353 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
 354 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 355 // CHECK1:       omp.dispatch.body:
 356 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
 357 // CHECK1-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
 358 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 359 // CHECK1:       omp.inner.for.cond:
 360 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 361 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 362 // CHECK1-NEXT:    [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]]
 363 // CHECK1-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 364 // CHECK1:       omp.inner.for.body:
 365 // CHECK1-NEXT:    [[TMP11:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 366 // CHECK1-NEXT:    [[CONV11:%.*]] = sext i8 [[TMP11]] to i64
 367 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 368 // CHECK1-NEXT:    [[DIV12:%.*]] = sdiv i64 [[TMP12]], 11
 369 // CHECK1-NEXT:    [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1
 370 // CHECK1-NEXT:    [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]]
 371 // CHECK1-NEXT:    [[CONV15:%.*]] = trunc i64 [[ADD14]] to i8
 372 // CHECK1-NEXT:    store i8 [[CONV15]], ptr [[I8]], align 1
 373 // CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 374 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 375 // CHECK1-NEXT:    [[DIV16:%.*]] = sdiv i64 [[TMP14]], 11
 376 // CHECK1-NEXT:    [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11
 377 // CHECK1-NEXT:    [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]]
 378 // CHECK1-NEXT:    [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 1
 379 // CHECK1-NEXT:    [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]]
 380 // CHECK1-NEXT:    [[CONV21:%.*]] = trunc i64 [[SUB20]] to i32
 381 // CHECK1-NEXT:    store i32 [[CONV21]], ptr [[X9]], align 4
 382 // CHECK1-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
 383 // CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 384 // CHECK1-NEXT:    [[TMP16:%.*]] = load i8, ptr [[I8]], align 1
 385 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i64
 386 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM]]
 387 // CHECK1-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 388 // CHECK1-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 389 // CHECK1-NEXT:    [[TMP19:%.*]] = load i8, ptr [[I8]], align 1
 390 // CHECK1-NEXT:    [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i64
 391 // CHECK1-NEXT:    [[ARRAYIDX23:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM22]]
 392 // CHECK1-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX23]], align 4
 393 // CHECK1-NEXT:    [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]]
 394 // CHECK1-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 395 // CHECK1-NEXT:    [[TMP22:%.*]] = load i8, ptr [[I8]], align 1
 396 // CHECK1-NEXT:    [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i64
 397 // CHECK1-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM25]]
 398 // CHECK1-NEXT:    [[TMP23:%.*]] = load float, ptr [[ARRAYIDX26]], align 4
 399 // CHECK1-NEXT:    [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]]
 400 // CHECK1-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 401 // CHECK1-NEXT:    [[TMP25:%.*]] = load i8, ptr [[I8]], align 1
 402 // CHECK1-NEXT:    [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i64
 403 // CHECK1-NEXT:    [[ARRAYIDX29:%.*]] = getelementptr inbounds float, ptr [[TMP24]], i64 [[IDXPROM28]]
 404 // CHECK1-NEXT:    store float [[MUL27]], ptr [[ARRAYIDX29]], align 4
 405 // CHECK1-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
 406 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 407 // CHECK1:       omp.body.continue:
 408 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 409 // CHECK1:       omp.inner.for.inc:
 410 // CHECK1-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 411 // CHECK1-NEXT:    [[ADD30:%.*]] = add nsw i64 [[TMP26]], 1
 412 // CHECK1-NEXT:    store i64 [[ADD30]], ptr [[DOTOMP_IV]], align 8
 413 // CHECK1-NEXT:    call void @__kmpc_dispatch_fini_8(ptr @[[GLOB1]], i32 [[TMP0]])
 414 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 415 // CHECK1:       omp.inner.for.end:
 416 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 417 // CHECK1:       omp.dispatch.inc:
 418 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
 419 // CHECK1:       omp.dispatch.end:
 420 // CHECK1-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])
 421 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
 422 // CHECK1:       omp.precond.end:
 423 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])
 424 // CHECK1-NEXT:    ret void
 425 //
 426 //
 427 // CHECK1-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_
 428 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 429 // CHECK1-NEXT:  entry:
 430 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 431 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 432 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 433 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 434 // CHECK1-NEXT:    [[X:%.*]] = alloca i32, align 4
 435 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 436 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i8, align 1
 437 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 438 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 439 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 440 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 441 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 442 // CHECK1-NEXT:    [[I:%.*]] = alloca i8, align 1
 443 // CHECK1-NEXT:    [[X2:%.*]] = alloca i32, align 4
 444 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 445 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 446 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 447 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 448 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 449 // CHECK1-NEXT:    store i32 0, ptr [[X]], align 4
 450 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 451 // CHECK1-NEXT:    store i32 199, ptr [[DOTOMP_UB]], align 4
 452 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 453 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 454 // CHECK1-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 1073741893, i32 0, i32 199, i32 1, i32 1)
 455 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 456 // CHECK1:       omp.dispatch.cond:
 457 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 458 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
 459 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 460 // CHECK1:       omp.dispatch.body:
 461 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 462 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_IV]], align 4
 463 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 464 // CHECK1:       omp.inner.for.cond:
 465 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 466 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 467 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]]
 468 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 469 // CHECK1:       omp.inner.for.body:
 470 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 471 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP5]], 20
 472 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
 473 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 48, [[MUL]]
 474 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i8
 475 // CHECK1-NEXT:    store i8 [[CONV]], ptr [[I]], align 1
 476 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 477 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 478 // CHECK1-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP7]], 20
 479 // CHECK1-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 20
 480 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]]
 481 // CHECK1-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
 482 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]]
 483 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[X2]], align 4
 484 // CHECK1-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
 485 // CHECK1-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 486 // CHECK1-NEXT:    [[TMP9:%.*]] = load i8, ptr [[I]], align 1
 487 // CHECK1-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i64
 488 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP8]], i64 [[IDXPROM]]
 489 // CHECK1-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 490 // CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 491 // CHECK1-NEXT:    [[TMP12:%.*]] = load i8, ptr [[I]], align 1
 492 // CHECK1-NEXT:    [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i64
 493 // CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[IDXPROM7]]
 494 // CHECK1-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX8]], align 4
 495 // CHECK1-NEXT:    [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]]
 496 // CHECK1-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 497 // CHECK1-NEXT:    [[TMP15:%.*]] = load i8, ptr [[I]], align 1
 498 // CHECK1-NEXT:    [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i64
 499 // CHECK1-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[IDXPROM10]]
 500 // CHECK1-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX11]], align 4
 501 // CHECK1-NEXT:    [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]]
 502 // CHECK1-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 503 // CHECK1-NEXT:    [[TMP18:%.*]] = load i8, ptr [[I]], align 1
 504 // CHECK1-NEXT:    [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i64
 505 // CHECK1-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[IDXPROM13]]
 506 // CHECK1-NEXT:    store float [[MUL12]], ptr [[ARRAYIDX14]], align 4
 507 // CHECK1-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
 508 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 509 // CHECK1:       omp.body.continue:
 510 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 511 // CHECK1:       omp.inner.for.inc:
 512 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 513 // CHECK1-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP19]], 1
 514 // CHECK1-NEXT:    store i32 [[ADD15]], ptr [[DOTOMP_IV]], align 4
 515 // CHECK1-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP0]])
 516 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 517 // CHECK1:       omp.inner.for.end:
 518 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 519 // CHECK1:       omp.dispatch.inc:
 520 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
 521 // CHECK1:       omp.dispatch.end:
 522 // CHECK1-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])
 523 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])
 524 // CHECK1-NEXT:    ret void
 525 //
 526 //
 527 // CHECK1-LABEL: define {{[^@]+}}@_Z8foo_simdii
 528 // CHECK1-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR3:[0-9]+]] {
 529 // CHECK1-NEXT:  entry:
 530 // CHECK1-NEXT:    [[LOW_ADDR:%.*]] = alloca i32, align 4
 531 // CHECK1-NEXT:    [[UP_ADDR:%.*]] = alloca i32, align 4
 532 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 533 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
 534 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
 535 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
 536 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 537 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 538 // CHECK1-NEXT:    [[I5:%.*]] = alloca i32, align 4
 539 // CHECK1-NEXT:    [[DOTOMP_IV16:%.*]] = alloca i32, align 4
 540 // CHECK1-NEXT:    [[_TMP17:%.*]] = alloca i32, align 4
 541 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4
 542 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4
 543 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4
 544 // CHECK1-NEXT:    [[I26:%.*]] = alloca i32, align 4
 545 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 546 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 547 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 548 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 549 // CHECK1-NEXT:    [[I28:%.*]] = alloca i32, align 4
 550 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 551 // CHECK1-NEXT:    store i32 [[LOW]], ptr [[LOW_ADDR]], align 4
 552 // CHECK1-NEXT:    store i32 [[UP]], ptr [[UP_ADDR]], align 4
 553 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
 554 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
 555 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[UP_ADDR]], align 4
 556 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
 557 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 558 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 559 // CHECK1-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
 560 // CHECK1-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
 561 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
 562 // CHECK1-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
 563 // CHECK1-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
 564 // CHECK1-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
 565 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 566 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[I]], align 4
 567 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 568 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 569 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
 570 // CHECK1-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
 571 // CHECK1:       simd.if.then:
 572 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IV]], align 4
 573 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 574 // CHECK1:       omp.inner.for.cond:
 575 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
 576 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
 577 // CHECK1-NEXT:    [[ADD6:%.*]] = add i32 [[TMP9]], 1
 578 // CHECK1-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]]
 579 // CHECK1-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 580 // CHECK1:       omp.inner.for.body:
 581 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP3]]
 582 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
 583 // CHECK1-NEXT:    [[MUL:%.*]] = mul i32 [[TMP11]], 1
 584 // CHECK1-NEXT:    [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]]
 585 // CHECK1-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]]
 586 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]]
 587 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
 588 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
 589 // CHECK1-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
 590 // CHECK1-NEXT:    call void @__captured_stmt(ptr [[I5]]), !llvm.access.group [[ACC_GRP3]]
 591 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 592 // CHECK1:       omp.body.continue:
 593 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 594 // CHECK1:       omp.inner.for.inc:
 595 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
 596 // CHECK1-NEXT:    [[ADD9:%.*]] = add i32 [[TMP13]], 1
 597 // CHECK1-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
 598 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
 599 // CHECK1:       omp.inner.for.end:
 600 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 601 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 602 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 603 // CHECK1-NEXT:    [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]]
 604 // CHECK1-NEXT:    [[SUB11:%.*]] = sub i32 [[SUB10]], 1
 605 // CHECK1-NEXT:    [[ADD12:%.*]] = add i32 [[SUB11]], 1
 606 // CHECK1-NEXT:    [[DIV13:%.*]] = udiv i32 [[ADD12]], 1
 607 // CHECK1-NEXT:    [[MUL14:%.*]] = mul i32 [[DIV13]], 1
 608 // CHECK1-NEXT:    [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]]
 609 // CHECK1-NEXT:    store i32 [[ADD15]], ptr [[I5]], align 4
 610 // CHECK1-NEXT:    br label [[SIMD_IF_END]]
 611 // CHECK1:       simd.if.end:
 612 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
 613 // CHECK1-NEXT:    store i32 [[TMP17]], ptr [[DOTCAPTURE_EXPR_18]], align 4
 614 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[UP_ADDR]], align 4
 615 // CHECK1-NEXT:    store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR_19]], align 4
 616 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
 617 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
 618 // CHECK1-NEXT:    [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]]
 619 // CHECK1-NEXT:    [[SUB22:%.*]] = sub i32 [[SUB21]], 1
 620 // CHECK1-NEXT:    [[ADD23:%.*]] = add i32 [[SUB22]], 1
 621 // CHECK1-NEXT:    [[DIV24:%.*]] = udiv i32 [[ADD23]], 1
 622 // CHECK1-NEXT:    [[SUB25:%.*]] = sub i32 [[DIV24]], 1
 623 // CHECK1-NEXT:    store i32 [[SUB25]], ptr [[DOTCAPTURE_EXPR_20]], align 4
 624 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
 625 // CHECK1-NEXT:    store i32 [[TMP21]], ptr [[I26]], align 4
 626 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
 627 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
 628 // CHECK1-NEXT:    [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]]
 629 // CHECK1-NEXT:    br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
 630 // CHECK1:       omp.precond.then:
 631 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 632 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
 633 // CHECK1-NEXT:    store i32 [[TMP24]], ptr [[DOTOMP_UB]], align 4
 634 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 635 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 636 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
 637 // CHECK1-NEXT:    call void @__kmpc_dispatch_init_4u(ptr @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1)
 638 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 639 // CHECK1:       omp.dispatch.cond:
 640 // CHECK1-NEXT:    [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 641 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0
 642 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 643 // CHECK1:       omp.dispatch.body:
 644 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 645 // CHECK1-NEXT:    store i32 [[TMP27]], ptr [[DOTOMP_IV16]], align 4
 646 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND29:%.*]]
 647 // CHECK1:       omp.inner.for.cond29:
 648 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
 649 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
 650 // CHECK1-NEXT:    [[ADD30:%.*]] = add i32 [[TMP29]], 1
 651 // CHECK1-NEXT:    [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]]
 652 // CHECK1-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]]
 653 // CHECK1:       omp.inner.for.body32:
 654 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group [[ACC_GRP7]]
 655 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
 656 // CHECK1-NEXT:    [[MUL33:%.*]] = mul i32 [[TMP31]], 1
 657 // CHECK1-NEXT:    [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]]
 658 // CHECK1-NEXT:    store i32 [[ADD34]], ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]]
 659 // CHECK1-NEXT:    [[TMP32:%.*]] = load i32, ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]]
 660 // CHECK1-NEXT:    [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64
 661 // CHECK1-NEXT:    [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM35]]
 662 // CHECK1-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX36]], align 4, !llvm.access.group [[ACC_GRP7]]
 663 // CHECK1-NEXT:    call void @__captured_stmt.1(ptr [[I28]]), !llvm.access.group [[ACC_GRP7]]
 664 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE37:%.*]]
 665 // CHECK1:       omp.body.continue37:
 666 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC38:%.*]]
 667 // CHECK1:       omp.inner.for.inc38:
 668 // CHECK1-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
 669 // CHECK1-NEXT:    [[ADD39:%.*]] = add i32 [[TMP33]], 1
 670 // CHECK1-NEXT:    store i32 [[ADD39]], ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
 671 // CHECK1-NEXT:    call void @__kmpc_dispatch_fini_4u(ptr @[[GLOB1]], i32 [[TMP0]]), !llvm.access.group [[ACC_GRP7]]
 672 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP8:![0-9]+]]
 673 // CHECK1:       omp.inner.for.end40:
 674 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 675 // CHECK1:       omp.dispatch.inc:
 676 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
 677 // CHECK1:       omp.dispatch.end:
 678 // CHECK1-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])
 679 // CHECK1-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 680 // CHECK1-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
 681 // CHECK1-NEXT:    br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 682 // CHECK1:       .omp.final.then:
 683 // CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
 684 // CHECK1-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
 685 // CHECK1-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
 686 // CHECK1-NEXT:    [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]]
 687 // CHECK1-NEXT:    [[SUB42:%.*]] = sub i32 [[SUB41]], 1
 688 // CHECK1-NEXT:    [[ADD43:%.*]] = add i32 [[SUB42]], 1
 689 // CHECK1-NEXT:    [[DIV44:%.*]] = udiv i32 [[ADD43]], 1
 690 // CHECK1-NEXT:    [[MUL45:%.*]] = mul i32 [[DIV44]], 1
 691 // CHECK1-NEXT:    [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]]
 692 // CHECK1-NEXT:    store i32 [[ADD46]], ptr [[I28]], align 4
 693 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 694 // CHECK1:       .omp.final.done:
 695 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
 696 // CHECK1:       omp.precond.end:
 697 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])
 698 // CHECK1-NEXT:    ret void
 699 //
 700 //
 701 // CHECK1-LABEL: define {{[^@]+}}@__captured_stmt
 702 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4:[0-9]+]] {
 703 // CHECK1-NEXT:  entry:
 704 // CHECK1-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
 705 // CHECK1-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
 706 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
 707 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 708 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
 709 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
 710 // CHECK1-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4
 711 // CHECK1-NEXT:    ret void
 712 //
 713 //
 714 // CHECK1-LABEL: define {{[^@]+}}@__captured_stmt.1
 715 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4]] {
 716 // CHECK1-NEXT:  entry:
 717 // CHECK1-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
 718 // CHECK1-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
 719 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
 720 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 721 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
 722 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
 723 // CHECK1-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4
 724 // CHECK1-NEXT:    ret void
 725 //
 726 //
 727 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
 728 // CHECK1-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
 729 // CHECK1-IRBUILDER-NEXT:  entry:
 730 // CHECK1-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 731 // CHECK1-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 732 // CHECK1-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 733 // CHECK1-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 734 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 735 // CHECK1-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 736 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 737 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 738 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 739 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 740 // CHECK1-IRBUILDER-NEXT:    [[I:%.*]] = alloca i32, align 4
 741 // CHECK1-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 742 // CHECK1-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 743 // CHECK1-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 744 // CHECK1-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 745 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 746 // CHECK1-IRBUILDER-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
 747 // CHECK1-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 748 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 749 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
 750 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 4571423, i32 1, i32 1)
 751 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 752 // CHECK1-IRBUILDER:       omp.dispatch.cond:
 753 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
 754 // CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 755 // CHECK1-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
 756 // CHECK1-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 757 // CHECK1-IRBUILDER:       omp.dispatch.body:
 758 // CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 759 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 4
 760 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 761 // CHECK1-IRBUILDER:       omp.inner.for.cond:
 762 // CHECK1-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 763 // CHECK1-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 764 // CHECK1-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
 765 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 766 // CHECK1-IRBUILDER:       omp.inner.for.body:
 767 // CHECK1-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 768 // CHECK1-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
 769 // CHECK1-IRBUILDER-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
 770 // CHECK1-IRBUILDER-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
 771 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 772 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
 773 // CHECK1-IRBUILDER-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 774 // CHECK1-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4
 775 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
 776 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 [[IDXPROM]]
 777 // CHECK1-IRBUILDER-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 778 // CHECK1-IRBUILDER-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 779 // CHECK1-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4
 780 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64
 781 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i64 [[IDXPROM3]]
 782 // CHECK1-IRBUILDER-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
 783 // CHECK1-IRBUILDER-NEXT:    [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]]
 784 // CHECK1-IRBUILDER-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 785 // CHECK1-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4
 786 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM6:%.*]] = sext i32 [[TMP12]] to i64
 787 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[IDXPROM6]]
 788 // CHECK1-IRBUILDER-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
 789 // CHECK1-IRBUILDER-NEXT:    [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP13]]
 790 // CHECK1-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 791 // CHECK1-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4
 792 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM9:%.*]] = sext i32 [[TMP15]] to i64
 793 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM9]]
 794 // CHECK1-IRBUILDER-NEXT:    store float [[MUL8]], ptr [[ARRAYIDX10]], align 4
 795 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
 796 // CHECK1-IRBUILDER:       omp.inner.for.body.ordered.after:
 797 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
 798 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 799 // CHECK1-IRBUILDER:       omp.body.continue:
 800 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 801 // CHECK1-IRBUILDER:       omp.inner.for.inc:
 802 // CHECK1-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 803 // CHECK1-IRBUILDER-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
 804 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
 805 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
 806 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM11]])
 807 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]
 808 // CHECK1-IRBUILDER:       omp.inner.for.end:
 809 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 810 // CHECK1-IRBUILDER:       omp.dispatch.inc:
 811 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
 812 // CHECK1-IRBUILDER:       omp.dispatch.end:
 813 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
 814 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM12]])
 815 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM13:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 816 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM13]])
 817 // CHECK1-IRBUILDER-NEXT:    ret void
 818 //
 819 //
 820 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_
 821 // CHECK1-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 822 // CHECK1-IRBUILDER-NEXT:  entry:
 823 // CHECK1-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 824 // CHECK1-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 825 // CHECK1-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 826 // CHECK1-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 827 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
 828 // CHECK1-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i64, align 8
 829 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
 830 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
 831 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
 832 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 833 // CHECK1-IRBUILDER-NEXT:    [[I:%.*]] = alloca i64, align 8
 834 // CHECK1-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 835 // CHECK1-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 836 // CHECK1-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 837 // CHECK1-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 838 // CHECK1-IRBUILDER-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
 839 // CHECK1-IRBUILDER-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8
 840 // CHECK1-IRBUILDER-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
 841 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 842 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6:[0-9]+]])
 843 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1073741891, i64 0, i64 16908287, i64 1, i64 1)
 844 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 845 // CHECK1-IRBUILDER:       omp.dispatch.cond:
 846 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6]])
 847 // CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 848 // CHECK1-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
 849 // CHECK1-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 850 // CHECK1-IRBUILDER:       omp.dispatch.body:
 851 // CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
 852 // CHECK1-IRBUILDER-NEXT:    store i64 [[TMP1]], ptr [[DOTOMP_IV]], align 8
 853 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 854 // CHECK1-IRBUILDER:       omp.inner.for.cond:
 855 // CHECK1-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 856 // CHECK1-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 857 // CHECK1-IRBUILDER-NEXT:    [[ADD:%.*]] = add i64 [[TMP3]], 1
 858 // CHECK1-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP2]], [[ADD]]
 859 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 860 // CHECK1-IRBUILDER:       omp.inner.for.body:
 861 // CHECK1-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 862 // CHECK1-IRBUILDER-NEXT:    [[MUL:%.*]] = mul i64 [[TMP4]], 127
 863 // CHECK1-IRBUILDER-NEXT:    [[ADD2:%.*]] = add i64 131071, [[MUL]]
 864 // CHECK1-IRBUILDER-NEXT:    store i64 [[ADD2]], ptr [[I]], align 8
 865 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 866 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]])
 867 // CHECK1-IRBUILDER-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 868 // CHECK1-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i64, ptr [[I]], align 8
 869 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP5]], i64 [[TMP6]]
 870 // CHECK1-IRBUILDER-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 871 // CHECK1-IRBUILDER-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 872 // CHECK1-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i64, ptr [[I]], align 8
 873 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP8]], i64 [[TMP9]]
 874 // CHECK1-IRBUILDER-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
 875 // CHECK1-IRBUILDER-NEXT:    [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]]
 876 // CHECK1-IRBUILDER-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 877 // CHECK1-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i64, ptr [[I]], align 8
 878 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]]
 879 // CHECK1-IRBUILDER-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
 880 // CHECK1-IRBUILDER-NEXT:    [[MUL7:%.*]] = fmul float [[MUL5]], [[TMP13]]
 881 // CHECK1-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 882 // CHECK1-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i64, ptr [[I]], align 8
 883 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]]
 884 // CHECK1-IRBUILDER-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX8]], align 4
 885 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
 886 // CHECK1-IRBUILDER:       omp.inner.for.body.ordered.after:
 887 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]])
 888 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 889 // CHECK1-IRBUILDER:       omp.body.continue:
 890 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 891 // CHECK1-IRBUILDER:       omp.inner.for.inc:
 892 // CHECK1-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 893 // CHECK1-IRBUILDER-NEXT:    [[ADD9:%.*]] = add i64 [[TMP16]], 1
 894 // CHECK1-IRBUILDER-NEXT:    store i64 [[ADD9]], ptr [[DOTOMP_IV]], align 8
 895 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6]])
 896 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]])
 897 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]
 898 // CHECK1-IRBUILDER:       omp.inner.for.end:
 899 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 900 // CHECK1-IRBUILDER:       omp.dispatch.inc:
 901 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
 902 // CHECK1-IRBUILDER:       omp.dispatch.end:
 903 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6]])
 904 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM11]])
 905 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 906 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM12]])
 907 // CHECK1-IRBUILDER-NEXT:    ret void
 908 //
 909 //
 910 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_
 911 // CHECK1-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 912 // CHECK1-IRBUILDER-NEXT:  entry:
 913 // CHECK1-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 914 // CHECK1-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 915 // CHECK1-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 916 // CHECK1-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 917 // CHECK1-IRBUILDER-NEXT:    [[X:%.*]] = alloca i32, align 4
 918 // CHECK1-IRBUILDER-NEXT:    [[Y:%.*]] = alloca i32, align 4
 919 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
 920 // CHECK1-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i8, align 1
 921 // CHECK1-IRBUILDER-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 922 // CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
 923 // CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
 924 // CHECK1-IRBUILDER-NEXT:    [[I:%.*]] = alloca i8, align 1
 925 // CHECK1-IRBUILDER-NEXT:    [[X6:%.*]] = alloca i32, align 4
 926 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
 927 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
 928 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
 929 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 930 // CHECK1-IRBUILDER-NEXT:    [[I8:%.*]] = alloca i8, align 1
 931 // CHECK1-IRBUILDER-NEXT:    [[X9:%.*]] = alloca i32, align 4
 932 // CHECK1-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 933 // CHECK1-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 934 // CHECK1-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 935 // CHECK1-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 936 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[X]], align 4
 937 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[Y]], align 4
 938 // CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = load i32, ptr [[Y]], align 4
 939 // CHECK1-IRBUILDER-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP0]] to i8
 940 // CHECK1-IRBUILDER-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1
 941 // CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 942 // CHECK1-IRBUILDER-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP1]] to i32
 943 // CHECK1-IRBUILDER-NEXT:    [[SUB:%.*]] = sub i32 57, [[CONV3]]
 944 // CHECK1-IRBUILDER-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], 1
 945 // CHECK1-IRBUILDER-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
 946 // CHECK1-IRBUILDER-NEXT:    [[CONV4:%.*]] = zext i32 [[DIV]] to i64
 947 // CHECK1-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11
 948 // CHECK1-IRBUILDER-NEXT:    [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1
 949 // CHECK1-IRBUILDER-NEXT:    store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8
 950 // CHECK1-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 951 // CHECK1-IRBUILDER-NEXT:    store i8 [[TMP2]], ptr [[I]], align 1
 952 // CHECK1-IRBUILDER-NEXT:    store i32 11, ptr [[X6]], align 4
 953 // CHECK1-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 954 // CHECK1-IRBUILDER-NEXT:    [[CONV7:%.*]] = sext i8 [[TMP3]] to i32
 955 // CHECK1-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57
 956 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
 957 // CHECK1-IRBUILDER:       omp.precond.then:
 958 // CHECK1-IRBUILDER-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
 959 // CHECK1-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
 960 // CHECK1-IRBUILDER-NEXT:    store i64 [[TMP4]], ptr [[DOTOMP_UB]], align 8
 961 // CHECK1-IRBUILDER-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
 962 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 963 // CHECK1-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
 964 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8:[0-9]+]])
 965 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1073741894, i64 0, i64 [[TMP5]], i64 1, i64 1)
 966 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 967 // CHECK1-IRBUILDER:       omp.dispatch.cond:
 968 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8]])
 969 // CHECK1-IRBUILDER-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 970 // CHECK1-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
 971 // CHECK1-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 972 // CHECK1-IRBUILDER:       omp.dispatch.body:
 973 // CHECK1-IRBUILDER-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
 974 // CHECK1-IRBUILDER-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
 975 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 976 // CHECK1-IRBUILDER:       omp.inner.for.cond:
 977 // CHECK1-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 978 // CHECK1-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 979 // CHECK1-IRBUILDER-NEXT:    [[CMP11:%.*]] = icmp sle i64 [[TMP8]], [[TMP9]]
 980 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 981 // CHECK1-IRBUILDER:       omp.inner.for.body:
 982 // CHECK1-IRBUILDER-NEXT:    [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 983 // CHECK1-IRBUILDER-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP10]] to i64
 984 // CHECK1-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 985 // CHECK1-IRBUILDER-NEXT:    [[DIV13:%.*]] = sdiv i64 [[TMP11]], 11
 986 // CHECK1-IRBUILDER-NEXT:    [[MUL14:%.*]] = mul nsw i64 [[DIV13]], 1
 987 // CHECK1-IRBUILDER-NEXT:    [[ADD15:%.*]] = add nsw i64 [[CONV12]], [[MUL14]]
 988 // CHECK1-IRBUILDER-NEXT:    [[CONV16:%.*]] = trunc i64 [[ADD15]] to i8
 989 // CHECK1-IRBUILDER-NEXT:    store i8 [[CONV16]], ptr [[I8]], align 1
 990 // CHECK1-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 991 // CHECK1-IRBUILDER-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 992 // CHECK1-IRBUILDER-NEXT:    [[DIV17:%.*]] = sdiv i64 [[TMP13]], 11
 993 // CHECK1-IRBUILDER-NEXT:    [[MUL18:%.*]] = mul nsw i64 [[DIV17]], 11
 994 // CHECK1-IRBUILDER-NEXT:    [[SUB19:%.*]] = sub nsw i64 [[TMP12]], [[MUL18]]
 995 // CHECK1-IRBUILDER-NEXT:    [[MUL20:%.*]] = mul nsw i64 [[SUB19]], 1
 996 // CHECK1-IRBUILDER-NEXT:    [[SUB21:%.*]] = sub nsw i64 11, [[MUL20]]
 997 // CHECK1-IRBUILDER-NEXT:    [[CONV22:%.*]] = trunc i64 [[SUB21]] to i32
 998 // CHECK1-IRBUILDER-NEXT:    store i32 [[CONV22]], ptr [[X9]], align 4
 999 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM23:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1000 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]])
1001 // CHECK1-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1002 // CHECK1-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i8, ptr [[I8]], align 1
1003 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP15]] to i64
1004 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]]
1005 // CHECK1-IRBUILDER-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1006 // CHECK1-IRBUILDER-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1007 // CHECK1-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i8, ptr [[I8]], align 1
1008 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM24:%.*]] = sext i8 [[TMP18]] to i64
1009 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM24]]
1010 // CHECK1-IRBUILDER-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX25]], align 4
1011 // CHECK1-IRBUILDER-NEXT:    [[MUL26:%.*]] = fmul float [[TMP16]], [[TMP19]]
1012 // CHECK1-IRBUILDER-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1013 // CHECK1-IRBUILDER-NEXT:    [[TMP21:%.*]] = load i8, ptr [[I8]], align 1
1014 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM27:%.*]] = sext i8 [[TMP21]] to i64
1015 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM27]]
1016 // CHECK1-IRBUILDER-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX28]], align 4
1017 // CHECK1-IRBUILDER-NEXT:    [[MUL29:%.*]] = fmul float [[MUL26]], [[TMP22]]
1018 // CHECK1-IRBUILDER-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1019 // CHECK1-IRBUILDER-NEXT:    [[TMP24:%.*]] = load i8, ptr [[I8]], align 1
1020 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM30:%.*]] = sext i8 [[TMP24]] to i64
1021 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX31:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM30]]
1022 // CHECK1-IRBUILDER-NEXT:    store float [[MUL29]], ptr [[ARRAYIDX31]], align 4
1023 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
1024 // CHECK1-IRBUILDER:       omp.inner.for.body.ordered.after:
1025 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]])
1026 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1027 // CHECK1-IRBUILDER:       omp.body.continue:
1028 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1029 // CHECK1-IRBUILDER:       omp.inner.for.inc:
1030 // CHECK1-IRBUILDER-NEXT:    [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1031 // CHECK1-IRBUILDER-NEXT:    [[ADD32:%.*]] = add nsw i64 [[TMP25]], 1
1032 // CHECK1-IRBUILDER-NEXT:    store i64 [[ADD32]], ptr [[DOTOMP_IV]], align 8
1033 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM33:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8]])
1034 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM33]])
1035 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]
1036 // CHECK1-IRBUILDER:       omp.inner.for.end:
1037 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1038 // CHECK1-IRBUILDER:       omp.dispatch.inc:
1039 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
1040 // CHECK1-IRBUILDER:       omp.dispatch.end:
1041 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM34:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8]])
1042 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM34]])
1043 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_PRECOND_END]]
1044 // CHECK1-IRBUILDER:       omp.precond.end:
1045 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM35:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1046 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM35]])
1047 // CHECK1-IRBUILDER-NEXT:    ret void
1048 //
1049 //
1050 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_
1051 // CHECK1-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
1052 // CHECK1-IRBUILDER-NEXT:  entry:
1053 // CHECK1-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1054 // CHECK1-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1055 // CHECK1-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1056 // CHECK1-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1057 // CHECK1-IRBUILDER-NEXT:    [[X:%.*]] = alloca i32, align 4
1058 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1059 // CHECK1-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i8, align 1
1060 // CHECK1-IRBUILDER-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1061 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1062 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1063 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1064 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1065 // CHECK1-IRBUILDER-NEXT:    [[I:%.*]] = alloca i8, align 1
1066 // CHECK1-IRBUILDER-NEXT:    [[X2:%.*]] = alloca i32, align 4
1067 // CHECK1-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1068 // CHECK1-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1069 // CHECK1-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1070 // CHECK1-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1071 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[X]], align 4
1072 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1073 // CHECK1-IRBUILDER-NEXT:    store i32 199, ptr [[DOTOMP_UB]], align 4
1074 // CHECK1-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1075 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1076 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10:[0-9]+]])
1077 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1073741893, i32 0, i32 199, i32 1, i32 1)
1078 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1079 // CHECK1-IRBUILDER:       omp.dispatch.cond:
1080 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10]])
1081 // CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1082 // CHECK1-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
1083 // CHECK1-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1084 // CHECK1-IRBUILDER:       omp.dispatch.body:
1085 // CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1086 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 4
1087 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1088 // CHECK1-IRBUILDER:       omp.inner.for.cond:
1089 // CHECK1-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1090 // CHECK1-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1091 // CHECK1-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
1092 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1093 // CHECK1-IRBUILDER:       omp.inner.for.body:
1094 // CHECK1-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1095 // CHECK1-IRBUILDER-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP4]], 20
1096 // CHECK1-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1097 // CHECK1-IRBUILDER-NEXT:    [[ADD:%.*]] = add nsw i32 48, [[MUL]]
1098 // CHECK1-IRBUILDER-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i8
1099 // CHECK1-IRBUILDER-NEXT:    store i8 [[CONV]], ptr [[I]], align 1
1100 // CHECK1-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1101 // CHECK1-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1102 // CHECK1-IRBUILDER-NEXT:    [[DIV4:%.*]] = sdiv i32 [[TMP6]], 20
1103 // CHECK1-IRBUILDER-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 20
1104 // CHECK1-IRBUILDER-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP5]], [[MUL5]]
1105 // CHECK1-IRBUILDER-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1
1106 // CHECK1-IRBUILDER-NEXT:    [[ADD7:%.*]] = add nsw i32 -10, [[MUL6]]
1107 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD7]], ptr [[X2]], align 4
1108 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM8:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1109 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]])
1110 // CHECK1-IRBUILDER-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1111 // CHECK1-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i8, ptr [[I]], align 1
1112 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP8]] to i64
1113 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP7]], i64 [[IDXPROM]]
1114 // CHECK1-IRBUILDER-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1115 // CHECK1-IRBUILDER-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1116 // CHECK1-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i8, ptr [[I]], align 1
1117 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM9:%.*]] = zext i8 [[TMP11]] to i64
1118 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP10]], i64 [[IDXPROM9]]
1119 // CHECK1-IRBUILDER-NEXT:    [[TMP12:%.*]] = load float, ptr [[ARRAYIDX10]], align 4
1120 // CHECK1-IRBUILDER-NEXT:    [[MUL11:%.*]] = fmul float [[TMP9]], [[TMP12]]
1121 // CHECK1-IRBUILDER-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1122 // CHECK1-IRBUILDER-NEXT:    [[TMP14:%.*]] = load i8, ptr [[I]], align 1
1123 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM12:%.*]] = zext i8 [[TMP14]] to i64
1124 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i64 [[IDXPROM12]]
1125 // CHECK1-IRBUILDER-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX13]], align 4
1126 // CHECK1-IRBUILDER-NEXT:    [[MUL14:%.*]] = fmul float [[MUL11]], [[TMP15]]
1127 // CHECK1-IRBUILDER-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1128 // CHECK1-IRBUILDER-NEXT:    [[TMP17:%.*]] = load i8, ptr [[I]], align 1
1129 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM15:%.*]] = zext i8 [[TMP17]] to i64
1130 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM15]]
1131 // CHECK1-IRBUILDER-NEXT:    store float [[MUL14]], ptr [[ARRAYIDX16]], align 4
1132 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
1133 // CHECK1-IRBUILDER:       omp.inner.for.body.ordered.after:
1134 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]])
1135 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1136 // CHECK1-IRBUILDER:       omp.body.continue:
1137 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1138 // CHECK1-IRBUILDER:       omp.inner.for.inc:
1139 // CHECK1-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1140 // CHECK1-IRBUILDER-NEXT:    [[ADD17:%.*]] = add nsw i32 [[TMP18]], 1
1141 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4
1142 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM18:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10]])
1143 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM18]])
1144 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]
1145 // CHECK1-IRBUILDER:       omp.inner.for.end:
1146 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1147 // CHECK1-IRBUILDER:       omp.dispatch.inc:
1148 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
1149 // CHECK1-IRBUILDER:       omp.dispatch.end:
1150 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM19:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10]])
1151 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM19]])
1152 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM20:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1153 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM20]])
1154 // CHECK1-IRBUILDER-NEXT:    ret void
1155 //
1156 //
1157 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z8foo_simdii
1158 // CHECK1-IRBUILDER-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR3:[0-9]+]] {
1159 // CHECK1-IRBUILDER-NEXT:  entry:
1160 // CHECK1-IRBUILDER-NEXT:    [[LOW_ADDR:%.*]] = alloca i32, align 4
1161 // CHECK1-IRBUILDER-NEXT:    [[UP_ADDR:%.*]] = alloca i32, align 4
1162 // CHECK1-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1163 // CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1164 // CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1165 // CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1166 // CHECK1-IRBUILDER-NEXT:    [[I:%.*]] = alloca i32, align 4
1167 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1168 // CHECK1-IRBUILDER-NEXT:    [[I5:%.*]] = alloca i32, align 4
1169 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV16:%.*]] = alloca i32, align 4
1170 // CHECK1-IRBUILDER-NEXT:    [[_TMP17:%.*]] = alloca i32, align 4
1171 // CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4
1172 // CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4
1173 // CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4
1174 // CHECK1-IRBUILDER-NEXT:    [[I26:%.*]] = alloca i32, align 4
1175 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1176 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1177 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1178 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1179 // CHECK1-IRBUILDER-NEXT:    [[I28:%.*]] = alloca i32, align 4
1180 // CHECK1-IRBUILDER-NEXT:    store i32 [[LOW]], ptr [[LOW_ADDR]], align 4
1181 // CHECK1-IRBUILDER-NEXT:    store i32 [[UP]], ptr [[UP_ADDR]], align 4
1182 // CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
1183 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
1184 // CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[UP_ADDR]], align 4
1185 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1186 // CHECK1-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1187 // CHECK1-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1188 // CHECK1-IRBUILDER-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
1189 // CHECK1-IRBUILDER-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
1190 // CHECK1-IRBUILDER-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
1191 // CHECK1-IRBUILDER-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
1192 // CHECK1-IRBUILDER-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
1193 // CHECK1-IRBUILDER-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1194 // CHECK1-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1195 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP4]], ptr [[I]], align 4
1196 // CHECK1-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1197 // CHECK1-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1198 // CHECK1-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]]
1199 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
1200 // CHECK1-IRBUILDER:       simd.if.then:
1201 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IV]], align 4
1202 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1203 // CHECK1-IRBUILDER:       omp.inner.for.cond:
1204 // CHECK1-IRBUILDER-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
1205 // CHECK1-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
1206 // CHECK1-IRBUILDER-NEXT:    [[ADD6:%.*]] = add i32 [[TMP8]], 1
1207 // CHECK1-IRBUILDER-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]]
1208 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1209 // CHECK1-IRBUILDER:       omp.inner.for.body:
1210 // CHECK1-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP3]]
1211 // CHECK1-IRBUILDER-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1212 // CHECK1-IRBUILDER-NEXT:    [[MUL:%.*]] = mul i32 [[TMP10]], 1
1213 // CHECK1-IRBUILDER-NEXT:    [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]]
1214 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]]
1215 // CHECK1-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]]
1216 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
1217 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
1218 // CHECK1-IRBUILDER-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
1219 // CHECK1-IRBUILDER-NEXT:    call void @__captured_stmt(ptr [[I5]]), !llvm.access.group [[ACC_GRP3]]
1220 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
1221 // CHECK1-IRBUILDER:       omp.inner.for.body.ordered.after:
1222 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1223 // CHECK1-IRBUILDER:       omp.body.continue:
1224 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1225 // CHECK1-IRBUILDER:       omp.inner.for.inc:
1226 // CHECK1-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1227 // CHECK1-IRBUILDER-NEXT:    [[ADD9:%.*]] = add i32 [[TMP12]], 1
1228 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1229 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1230 // CHECK1-IRBUILDER:       omp.inner.for.end:
1231 // CHECK1-IRBUILDER-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1232 // CHECK1-IRBUILDER-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1233 // CHECK1-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1234 // CHECK1-IRBUILDER-NEXT:    [[SUB10:%.*]] = sub i32 [[TMP14]], [[TMP15]]
1235 // CHECK1-IRBUILDER-NEXT:    [[SUB11:%.*]] = sub i32 [[SUB10]], 1
1236 // CHECK1-IRBUILDER-NEXT:    [[ADD12:%.*]] = add i32 [[SUB11]], 1
1237 // CHECK1-IRBUILDER-NEXT:    [[DIV13:%.*]] = udiv i32 [[ADD12]], 1
1238 // CHECK1-IRBUILDER-NEXT:    [[MUL14:%.*]] = mul i32 [[DIV13]], 1
1239 // CHECK1-IRBUILDER-NEXT:    [[ADD15:%.*]] = add i32 [[TMP13]], [[MUL14]]
1240 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD15]], ptr [[I5]], align 4
1241 // CHECK1-IRBUILDER-NEXT:    br label [[SIMD_IF_END]]
1242 // CHECK1-IRBUILDER:       simd.if.end:
1243 // CHECK1-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
1244 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_18]], align 4
1245 // CHECK1-IRBUILDER-NEXT:    [[TMP17:%.*]] = load i32, ptr [[UP_ADDR]], align 4
1246 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP17]], ptr [[DOTCAPTURE_EXPR_19]], align 4
1247 // CHECK1-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
1248 // CHECK1-IRBUILDER-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1249 // CHECK1-IRBUILDER-NEXT:    [[SUB21:%.*]] = sub i32 [[TMP18]], [[TMP19]]
1250 // CHECK1-IRBUILDER-NEXT:    [[SUB22:%.*]] = sub i32 [[SUB21]], 1
1251 // CHECK1-IRBUILDER-NEXT:    [[ADD23:%.*]] = add i32 [[SUB22]], 1
1252 // CHECK1-IRBUILDER-NEXT:    [[DIV24:%.*]] = udiv i32 [[ADD23]], 1
1253 // CHECK1-IRBUILDER-NEXT:    [[SUB25:%.*]] = sub i32 [[DIV24]], 1
1254 // CHECK1-IRBUILDER-NEXT:    store i32 [[SUB25]], ptr [[DOTCAPTURE_EXPR_20]], align 4
1255 // CHECK1-IRBUILDER-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1256 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP20]], ptr [[I26]], align 4
1257 // CHECK1-IRBUILDER-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1258 // CHECK1-IRBUILDER-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
1259 // CHECK1-IRBUILDER-NEXT:    [[CMP27:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]]
1260 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1261 // CHECK1-IRBUILDER:       omp.precond.then:
1262 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1263 // CHECK1-IRBUILDER-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
1264 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP23]], ptr [[DOTOMP_UB]], align 4
1265 // CHECK1-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1266 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1267 // CHECK1-IRBUILDER-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
1268 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12:[0-9]+]])
1269 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 [[TMP24]], i32 1, i32 1)
1270 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1271 // CHECK1-IRBUILDER:       omp.dispatch.cond:
1272 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM29:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12]])
1273 // CHECK1-IRBUILDER-NEXT:    [[TMP25:%.*]] = call i32 @__kmpc_dispatch_next_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM29]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1274 // CHECK1-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP25]], 0
1275 // CHECK1-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1276 // CHECK1-IRBUILDER:       omp.dispatch.body:
1277 // CHECK1-IRBUILDER-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1278 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP26]], ptr [[DOTOMP_IV16]], align 4
1279 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
1280 // CHECK1-IRBUILDER:       omp.inner.for.cond30:
1281 // CHECK1-IRBUILDER-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
1282 // CHECK1-IRBUILDER-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
1283 // CHECK1-IRBUILDER-NEXT:    [[ADD31:%.*]] = add i32 [[TMP28]], 1
1284 // CHECK1-IRBUILDER-NEXT:    [[CMP32:%.*]] = icmp ult i32 [[TMP27]], [[ADD31]]
1285 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP32]], label [[OMP_INNER_FOR_BODY33:%.*]], label [[OMP_INNER_FOR_END42:%.*]]
1286 // CHECK1-IRBUILDER:       omp.inner.for.body33:
1287 // CHECK1-IRBUILDER-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group [[ACC_GRP7]]
1288 // CHECK1-IRBUILDER-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
1289 // CHECK1-IRBUILDER-NEXT:    [[MUL34:%.*]] = mul i32 [[TMP30]], 1
1290 // CHECK1-IRBUILDER-NEXT:    [[ADD35:%.*]] = add i32 [[TMP29]], [[MUL34]]
1291 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD35]], ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]]
1292 // CHECK1-IRBUILDER-NEXT:    [[TMP31:%.*]] = load i32, ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]]
1293 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64
1294 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM36]]
1295 // CHECK1-IRBUILDER-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX37]], align 4, !llvm.access.group [[ACC_GRP7]]
1296 // CHECK1-IRBUILDER-NEXT:    call void @__captured_stmt.1(ptr [[I28]]), !llvm.access.group [[ACC_GRP7]]
1297 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY33_ORDERED_AFTER:%.*]]
1298 // CHECK1-IRBUILDER:       omp.inner.for.body33.ordered.after:
1299 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE38:%.*]]
1300 // CHECK1-IRBUILDER:       omp.body.continue38:
1301 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC39:%.*]]
1302 // CHECK1-IRBUILDER:       omp.inner.for.inc39:
1303 // CHECK1-IRBUILDER-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
1304 // CHECK1-IRBUILDER-NEXT:    [[ADD40:%.*]] = add i32 [[TMP32]], 1
1305 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD40]], ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
1306 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM41:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12]])
1307 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM41]]), !llvm.access.group [[ACC_GRP7]]
1308 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP8:![0-9]+]]
1309 // CHECK1-IRBUILDER:       omp.inner.for.end42:
1310 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1311 // CHECK1-IRBUILDER:       omp.dispatch.inc:
1312 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
1313 // CHECK1-IRBUILDER:       omp.dispatch.end:
1314 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM43:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12]])
1315 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM43]])
1316 // CHECK1-IRBUILDER-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1317 // CHECK1-IRBUILDER-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
1318 // CHECK1-IRBUILDER-NEXT:    br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1319 // CHECK1-IRBUILDER:       .omp.final.then:
1320 // CHECK1-IRBUILDER-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1321 // CHECK1-IRBUILDER-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
1322 // CHECK1-IRBUILDER-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1323 // CHECK1-IRBUILDER-NEXT:    [[SUB44:%.*]] = sub i32 [[TMP36]], [[TMP37]]
1324 // CHECK1-IRBUILDER-NEXT:    [[SUB45:%.*]] = sub i32 [[SUB44]], 1
1325 // CHECK1-IRBUILDER-NEXT:    [[ADD46:%.*]] = add i32 [[SUB45]], 1
1326 // CHECK1-IRBUILDER-NEXT:    [[DIV47:%.*]] = udiv i32 [[ADD46]], 1
1327 // CHECK1-IRBUILDER-NEXT:    [[MUL48:%.*]] = mul i32 [[DIV47]], 1
1328 // CHECK1-IRBUILDER-NEXT:    [[ADD49:%.*]] = add i32 [[TMP35]], [[MUL48]]
1329 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD49]], ptr [[I28]], align 4
1330 // CHECK1-IRBUILDER-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1331 // CHECK1-IRBUILDER:       .omp.final.done:
1332 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_PRECOND_END]]
1333 // CHECK1-IRBUILDER:       omp.precond.end:
1334 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM50:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1335 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM50]])
1336 // CHECK1-IRBUILDER-NEXT:    ret void
1337 //
1338 //
1339 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt
1340 // CHECK1-IRBUILDER-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4:[0-9]+]] {
1341 // CHECK1-IRBUILDER-NEXT:  entry:
1342 // CHECK1-IRBUILDER-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
1343 // CHECK1-IRBUILDER-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
1344 // CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
1345 // CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1346 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
1347 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
1348 // CHECK1-IRBUILDER-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4
1349 // CHECK1-IRBUILDER-NEXT:    ret void
1350 //
1351 //
1352 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt.1
1353 // CHECK1-IRBUILDER-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4]] {
1354 // CHECK1-IRBUILDER-NEXT:  entry:
1355 // CHECK1-IRBUILDER-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
1356 // CHECK1-IRBUILDER-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
1357 // CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
1358 // CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1359 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
1360 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
1361 // CHECK1-IRBUILDER-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4
1362 // CHECK1-IRBUILDER-NEXT:    ret void
1363 //
1364 //
1365 // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
1366 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
1367 // CHECK3-NEXT:  entry:
1368 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1369 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1370 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1371 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1372 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1373 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1374 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1375 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1376 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1377 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1378 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1379 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
1380 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1381 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1382 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1383 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1384 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1385 // CHECK3-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
1386 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1387 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1388 // CHECK3-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1)
1389 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1390 // CHECK3:       omp.dispatch.cond:
1391 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1392 // CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
1393 // CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1394 // CHECK3:       omp.dispatch.body:
1395 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1396 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_IV]], align 4
1397 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1398 // CHECK3:       omp.inner.for.cond:
1399 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1400 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1401 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]]
1402 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1403 // CHECK3:       omp.inner.for.body:
1404 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1405 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP5]], 7
1406 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
1407 // CHECK3-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
1408 // CHECK3-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
1409 // CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1410 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4
1411 // CHECK3-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64
1412 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i64 [[IDXPROM]]
1413 // CHECK3-NEXT:    [[TMP8:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1414 // CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1415 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[I]], align 4
1416 // CHECK3-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i64
1417 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i64 [[IDXPROM1]]
1418 // CHECK3-NEXT:    [[TMP11:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
1419 // CHECK3-NEXT:    [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]]
1420 // CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1421 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
1422 // CHECK3-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64
1423 // CHECK3-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM4]]
1424 // CHECK3-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX5]], align 4
1425 // CHECK3-NEXT:    [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]]
1426 // CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1427 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
1428 // CHECK3-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64
1429 // CHECK3-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM7]]
1430 // CHECK3-NEXT:    store float [[MUL6]], ptr [[ARRAYIDX8]], align 4
1431 // CHECK3-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
1432 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1433 // CHECK3:       omp.body.continue:
1434 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1435 // CHECK3:       omp.inner.for.inc:
1436 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1437 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP17]], 1
1438 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
1439 // CHECK3-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP0]])
1440 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
1441 // CHECK3:       omp.inner.for.end:
1442 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1443 // CHECK3:       omp.dispatch.inc:
1444 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
1445 // CHECK3:       omp.dispatch.end:
1446 // CHECK3-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])
1447 // CHECK3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP0]])
1448 // CHECK3-NEXT:    ret void
1449 //
1450 //
1451 // CHECK3-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_
1452 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
1453 // CHECK3-NEXT:  entry:
1454 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1455 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1456 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1457 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1458 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1459 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i64, align 8
1460 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
1461 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
1462 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1463 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1464 // CHECK3-NEXT:    [[I:%.*]] = alloca i64, align 8
1465 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1466 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1467 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1468 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1469 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1470 // CHECK3-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
1471 // CHECK3-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8
1472 // CHECK3-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
1473 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1474 // CHECK3-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB1]], i32 [[TMP0]], i32 67, i64 0, i64 16908287, i64 1, i64 1)
1475 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1476 // CHECK3:       omp.dispatch.cond:
1477 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1478 // CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
1479 // CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1480 // CHECK3:       omp.dispatch.body:
1481 // CHECK3-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1482 // CHECK3-NEXT:    store i64 [[TMP2]], ptr [[DOTOMP_IV]], align 8
1483 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1484 // CHECK3:       omp.inner.for.cond:
1485 // CHECK3-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1486 // CHECK3-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1487 // CHECK3-NEXT:    [[ADD:%.*]] = add i64 [[TMP4]], 1
1488 // CHECK3-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]]
1489 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1490 // CHECK3:       omp.inner.for.body:
1491 // CHECK3-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1492 // CHECK3-NEXT:    [[MUL:%.*]] = mul i64 [[TMP5]], 127
1493 // CHECK3-NEXT:    [[ADD1:%.*]] = add i64 131071, [[MUL]]
1494 // CHECK3-NEXT:    store i64 [[ADD1]], ptr [[I]], align 8
1495 // CHECK3-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
1496 // CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1497 // CHECK3-NEXT:    [[TMP7:%.*]] = load i64, ptr [[I]], align 8
1498 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP6]], i64 [[TMP7]]
1499 // CHECK3-NEXT:    [[TMP8:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1500 // CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1501 // CHECK3-NEXT:    [[TMP10:%.*]] = load i64, ptr [[I]], align 8
1502 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP9]], i64 [[TMP10]]
1503 // CHECK3-NEXT:    [[TMP11:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
1504 // CHECK3-NEXT:    [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]]
1505 // CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1506 // CHECK3-NEXT:    [[TMP13:%.*]] = load i64, ptr [[I]], align 8
1507 // CHECK3-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP12]], i64 [[TMP13]]
1508 // CHECK3-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
1509 // CHECK3-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]]
1510 // CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1511 // CHECK3-NEXT:    [[TMP16:%.*]] = load i64, ptr [[I]], align 8
1512 // CHECK3-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP15]], i64 [[TMP16]]
1513 // CHECK3-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4
1514 // CHECK3-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
1515 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1516 // CHECK3:       omp.body.continue:
1517 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1518 // CHECK3:       omp.inner.for.inc:
1519 // CHECK3-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1520 // CHECK3-NEXT:    [[ADD7:%.*]] = add i64 [[TMP17]], 1
1521 // CHECK3-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8
1522 // CHECK3-NEXT:    call void @__kmpc_dispatch_fini_8u(ptr @[[GLOB1]], i32 [[TMP0]])
1523 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
1524 // CHECK3:       omp.inner.for.end:
1525 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1526 // CHECK3:       omp.dispatch.inc:
1527 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
1528 // CHECK3:       omp.dispatch.end:
1529 // CHECK3-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])
1530 // CHECK3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])
1531 // CHECK3-NEXT:    ret void
1532 //
1533 //
1534 // CHECK3-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_
1535 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
1536 // CHECK3-NEXT:  entry:
1537 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1538 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1539 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1540 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1541 // CHECK3-NEXT:    [[X:%.*]] = alloca i32, align 4
1542 // CHECK3-NEXT:    [[Y:%.*]] = alloca i32, align 4
1543 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1544 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i8, align 1
1545 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1546 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1547 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
1548 // CHECK3-NEXT:    [[I:%.*]] = alloca i8, align 1
1549 // CHECK3-NEXT:    [[X6:%.*]] = alloca i32, align 4
1550 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
1551 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
1552 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1553 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1554 // CHECK3-NEXT:    [[I8:%.*]] = alloca i8, align 1
1555 // CHECK3-NEXT:    [[X9:%.*]] = alloca i32, align 4
1556 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1557 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1558 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1559 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1560 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1561 // CHECK3-NEXT:    store i32 0, ptr [[X]], align 4
1562 // CHECK3-NEXT:    store i32 0, ptr [[Y]], align 4
1563 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[Y]], align 4
1564 // CHECK3-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP1]] to i8
1565 // CHECK3-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1
1566 // CHECK3-NEXT:    [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
1567 // CHECK3-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
1568 // CHECK3-NEXT:    [[SUB:%.*]] = sub i32 57, [[CONV3]]
1569 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], 1
1570 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
1571 // CHECK3-NEXT:    [[CONV4:%.*]] = zext i32 [[DIV]] to i64
1572 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11
1573 // CHECK3-NEXT:    [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1
1574 // CHECK3-NEXT:    store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8
1575 // CHECK3-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
1576 // CHECK3-NEXT:    store i8 [[TMP3]], ptr [[I]], align 1
1577 // CHECK3-NEXT:    store i32 11, ptr [[X6]], align 4
1578 // CHECK3-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
1579 // CHECK3-NEXT:    [[CONV7:%.*]] = sext i8 [[TMP4]] to i32
1580 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57
1581 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1582 // CHECK3:       omp.precond.then:
1583 // CHECK3-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
1584 // CHECK3-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
1585 // CHECK3-NEXT:    store i64 [[TMP5]], ptr [[DOTOMP_UB]], align 8
1586 // CHECK3-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
1587 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1588 // CHECK3-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
1589 // CHECK3-NEXT:    call void @__kmpc_dispatch_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 70, i64 0, i64 [[TMP6]], i64 1, i64 1)
1590 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1591 // CHECK3:       omp.dispatch.cond:
1592 // CHECK3-NEXT:    [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1593 // CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
1594 // CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1595 // CHECK3:       omp.dispatch.body:
1596 // CHECK3-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1597 // CHECK3-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
1598 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1599 // CHECK3:       omp.inner.for.cond:
1600 // CHECK3-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1601 // CHECK3-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1602 // CHECK3-NEXT:    [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]]
1603 // CHECK3-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1604 // CHECK3:       omp.inner.for.body:
1605 // CHECK3-NEXT:    [[TMP11:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
1606 // CHECK3-NEXT:    [[CONV11:%.*]] = sext i8 [[TMP11]] to i64
1607 // CHECK3-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1608 // CHECK3-NEXT:    [[DIV12:%.*]] = sdiv i64 [[TMP12]], 11
1609 // CHECK3-NEXT:    [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1
1610 // CHECK3-NEXT:    [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]]
1611 // CHECK3-NEXT:    [[CONV15:%.*]] = trunc i64 [[ADD14]] to i8
1612 // CHECK3-NEXT:    store i8 [[CONV15]], ptr [[I8]], align 1
1613 // CHECK3-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1614 // CHECK3-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1615 // CHECK3-NEXT:    [[DIV16:%.*]] = sdiv i64 [[TMP14]], 11
1616 // CHECK3-NEXT:    [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11
1617 // CHECK3-NEXT:    [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]]
1618 // CHECK3-NEXT:    [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 1
1619 // CHECK3-NEXT:    [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]]
1620 // CHECK3-NEXT:    [[CONV21:%.*]] = trunc i64 [[SUB20]] to i32
1621 // CHECK3-NEXT:    store i32 [[CONV21]], ptr [[X9]], align 4
1622 // CHECK3-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
1623 // CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1624 // CHECK3-NEXT:    [[TMP16:%.*]] = load i8, ptr [[I8]], align 1
1625 // CHECK3-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i64
1626 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM]]
1627 // CHECK3-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1628 // CHECK3-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1629 // CHECK3-NEXT:    [[TMP19:%.*]] = load i8, ptr [[I8]], align 1
1630 // CHECK3-NEXT:    [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i64
1631 // CHECK3-NEXT:    [[ARRAYIDX23:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM22]]
1632 // CHECK3-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX23]], align 4
1633 // CHECK3-NEXT:    [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]]
1634 // CHECK3-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1635 // CHECK3-NEXT:    [[TMP22:%.*]] = load i8, ptr [[I8]], align 1
1636 // CHECK3-NEXT:    [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i64
1637 // CHECK3-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM25]]
1638 // CHECK3-NEXT:    [[TMP23:%.*]] = load float, ptr [[ARRAYIDX26]], align 4
1639 // CHECK3-NEXT:    [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]]
1640 // CHECK3-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1641 // CHECK3-NEXT:    [[TMP25:%.*]] = load i8, ptr [[I8]], align 1
1642 // CHECK3-NEXT:    [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i64
1643 // CHECK3-NEXT:    [[ARRAYIDX29:%.*]] = getelementptr inbounds float, ptr [[TMP24]], i64 [[IDXPROM28]]
1644 // CHECK3-NEXT:    store float [[MUL27]], ptr [[ARRAYIDX29]], align 4
1645 // CHECK3-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
1646 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1647 // CHECK3:       omp.body.continue:
1648 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1649 // CHECK3:       omp.inner.for.inc:
1650 // CHECK3-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1651 // CHECK3-NEXT:    [[ADD30:%.*]] = add nsw i64 [[TMP26]], 1
1652 // CHECK3-NEXT:    store i64 [[ADD30]], ptr [[DOTOMP_IV]], align 8
1653 // CHECK3-NEXT:    call void @__kmpc_dispatch_fini_8(ptr @[[GLOB1]], i32 [[TMP0]])
1654 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
1655 // CHECK3:       omp.inner.for.end:
1656 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1657 // CHECK3:       omp.dispatch.inc:
1658 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
1659 // CHECK3:       omp.dispatch.end:
1660 // CHECK3-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])
1661 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
1662 // CHECK3:       omp.precond.end:
1663 // CHECK3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])
1664 // CHECK3-NEXT:    ret void
1665 //
1666 //
1667 // CHECK3-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_
1668 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
1669 // CHECK3-NEXT:  entry:
1670 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1671 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1672 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1673 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1674 // CHECK3-NEXT:    [[X:%.*]] = alloca i32, align 4
1675 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1676 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i8, align 1
1677 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1678 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1679 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1680 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1681 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1682 // CHECK3-NEXT:    [[I:%.*]] = alloca i8, align 1
1683 // CHECK3-NEXT:    [[X2:%.*]] = alloca i32, align 4
1684 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1685 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1686 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1687 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1688 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1689 // CHECK3-NEXT:    store i32 0, ptr [[X]], align 4
1690 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1691 // CHECK3-NEXT:    store i32 199, ptr [[DOTOMP_UB]], align 4
1692 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1693 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1694 // CHECK3-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 69, i32 0, i32 199, i32 1, i32 1)
1695 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1696 // CHECK3:       omp.dispatch.cond:
1697 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1698 // CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
1699 // CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1700 // CHECK3:       omp.dispatch.body:
1701 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1702 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_IV]], align 4
1703 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1704 // CHECK3:       omp.inner.for.cond:
1705 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1706 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1707 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]]
1708 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1709 // CHECK3:       omp.inner.for.body:
1710 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1711 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP5]], 20
1712 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1713 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 48, [[MUL]]
1714 // CHECK3-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i8
1715 // CHECK3-NEXT:    store i8 [[CONV]], ptr [[I]], align 1
1716 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1717 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1718 // CHECK3-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP7]], 20
1719 // CHECK3-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 20
1720 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]]
1721 // CHECK3-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
1722 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]]
1723 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[X2]], align 4
1724 // CHECK3-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
1725 // CHECK3-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1726 // CHECK3-NEXT:    [[TMP9:%.*]] = load i8, ptr [[I]], align 1
1727 // CHECK3-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i64
1728 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP8]], i64 [[IDXPROM]]
1729 // CHECK3-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1730 // CHECK3-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1731 // CHECK3-NEXT:    [[TMP12:%.*]] = load i8, ptr [[I]], align 1
1732 // CHECK3-NEXT:    [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i64
1733 // CHECK3-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[IDXPROM7]]
1734 // CHECK3-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX8]], align 4
1735 // CHECK3-NEXT:    [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]]
1736 // CHECK3-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1737 // CHECK3-NEXT:    [[TMP15:%.*]] = load i8, ptr [[I]], align 1
1738 // CHECK3-NEXT:    [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i64
1739 // CHECK3-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[IDXPROM10]]
1740 // CHECK3-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX11]], align 4
1741 // CHECK3-NEXT:    [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]]
1742 // CHECK3-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1743 // CHECK3-NEXT:    [[TMP18:%.*]] = load i8, ptr [[I]], align 1
1744 // CHECK3-NEXT:    [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i64
1745 // CHECK3-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[IDXPROM13]]
1746 // CHECK3-NEXT:    store float [[MUL12]], ptr [[ARRAYIDX14]], align 4
1747 // CHECK3-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
1748 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1749 // CHECK3:       omp.body.continue:
1750 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1751 // CHECK3:       omp.inner.for.inc:
1752 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1753 // CHECK3-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP19]], 1
1754 // CHECK3-NEXT:    store i32 [[ADD15]], ptr [[DOTOMP_IV]], align 4
1755 // CHECK3-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP0]])
1756 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
1757 // CHECK3:       omp.inner.for.end:
1758 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1759 // CHECK3:       omp.dispatch.inc:
1760 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
1761 // CHECK3:       omp.dispatch.end:
1762 // CHECK3-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])
1763 // CHECK3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])
1764 // CHECK3-NEXT:    ret void
1765 //
1766 //
1767 // CHECK3-LABEL: define {{[^@]+}}@_Z8foo_simdii
1768 // CHECK3-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR3:[0-9]+]] {
1769 // CHECK3-NEXT:  entry:
1770 // CHECK3-NEXT:    [[LOW_ADDR:%.*]] = alloca i32, align 4
1771 // CHECK3-NEXT:    [[UP_ADDR:%.*]] = alloca i32, align 4
1772 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1773 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1774 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1775 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1776 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1777 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1778 // CHECK3-NEXT:    [[I5:%.*]] = alloca i32, align 4
1779 // CHECK3-NEXT:    [[DOTOMP_IV16:%.*]] = alloca i32, align 4
1780 // CHECK3-NEXT:    [[_TMP17:%.*]] = alloca i32, align 4
1781 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4
1782 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4
1783 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4
1784 // CHECK3-NEXT:    [[I26:%.*]] = alloca i32, align 4
1785 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1786 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1787 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1788 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1789 // CHECK3-NEXT:    [[I28:%.*]] = alloca i32, align 4
1790 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1791 // CHECK3-NEXT:    store i32 [[LOW]], ptr [[LOW_ADDR]], align 4
1792 // CHECK3-NEXT:    store i32 [[UP]], ptr [[UP_ADDR]], align 4
1793 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
1794 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
1795 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[UP_ADDR]], align 4
1796 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1797 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1798 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1799 // CHECK3-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
1800 // CHECK3-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
1801 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
1802 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
1803 // CHECK3-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
1804 // CHECK3-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1805 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1806 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[I]], align 4
1807 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1808 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1809 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
1810 // CHECK3-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
1811 // CHECK3:       simd.if.then:
1812 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IV]], align 4
1813 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1814 // CHECK3:       omp.inner.for.cond:
1815 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
1816 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
1817 // CHECK3-NEXT:    [[ADD6:%.*]] = add i32 [[TMP9]], 1
1818 // CHECK3-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]]
1819 // CHECK3-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1820 // CHECK3:       omp.inner.for.body:
1821 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP3]]
1822 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1823 // CHECK3-NEXT:    [[MUL:%.*]] = mul i32 [[TMP11]], 1
1824 // CHECK3-NEXT:    [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]]
1825 // CHECK3-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]]
1826 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]]
1827 // CHECK3-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
1828 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
1829 // CHECK3-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
1830 // CHECK3-NEXT:    call void @__captured_stmt(ptr [[I5]]), !llvm.access.group [[ACC_GRP3]]
1831 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1832 // CHECK3:       omp.body.continue:
1833 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1834 // CHECK3:       omp.inner.for.inc:
1835 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1836 // CHECK3-NEXT:    [[ADD9:%.*]] = add i32 [[TMP13]], 1
1837 // CHECK3-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1838 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1839 // CHECK3:       omp.inner.for.end:
1840 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1841 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1842 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1843 // CHECK3-NEXT:    [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]]
1844 // CHECK3-NEXT:    [[SUB11:%.*]] = sub i32 [[SUB10]], 1
1845 // CHECK3-NEXT:    [[ADD12:%.*]] = add i32 [[SUB11]], 1
1846 // CHECK3-NEXT:    [[DIV13:%.*]] = udiv i32 [[ADD12]], 1
1847 // CHECK3-NEXT:    [[MUL14:%.*]] = mul i32 [[DIV13]], 1
1848 // CHECK3-NEXT:    [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]]
1849 // CHECK3-NEXT:    store i32 [[ADD15]], ptr [[I5]], align 4
1850 // CHECK3-NEXT:    br label [[SIMD_IF_END]]
1851 // CHECK3:       simd.if.end:
1852 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
1853 // CHECK3-NEXT:    store i32 [[TMP17]], ptr [[DOTCAPTURE_EXPR_18]], align 4
1854 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[UP_ADDR]], align 4
1855 // CHECK3-NEXT:    store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR_19]], align 4
1856 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
1857 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1858 // CHECK3-NEXT:    [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]]
1859 // CHECK3-NEXT:    [[SUB22:%.*]] = sub i32 [[SUB21]], 1
1860 // CHECK3-NEXT:    [[ADD23:%.*]] = add i32 [[SUB22]], 1
1861 // CHECK3-NEXT:    [[DIV24:%.*]] = udiv i32 [[ADD23]], 1
1862 // CHECK3-NEXT:    [[SUB25:%.*]] = sub i32 [[DIV24]], 1
1863 // CHECK3-NEXT:    store i32 [[SUB25]], ptr [[DOTCAPTURE_EXPR_20]], align 4
1864 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1865 // CHECK3-NEXT:    store i32 [[TMP21]], ptr [[I26]], align 4
1866 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1867 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
1868 // CHECK3-NEXT:    [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]]
1869 // CHECK3-NEXT:    br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1870 // CHECK3:       omp.precond.then:
1871 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1872 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
1873 // CHECK3-NEXT:    store i32 [[TMP24]], ptr [[DOTOMP_UB]], align 4
1874 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1875 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1876 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
1877 // CHECK3-NEXT:    call void @__kmpc_dispatch_init_4u(ptr @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1)
1878 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1879 // CHECK3:       omp.dispatch.cond:
1880 // CHECK3-NEXT:    [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1881 // CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0
1882 // CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1883 // CHECK3:       omp.dispatch.body:
1884 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1885 // CHECK3-NEXT:    store i32 [[TMP27]], ptr [[DOTOMP_IV16]], align 4
1886 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND29:%.*]]
1887 // CHECK3:       omp.inner.for.cond29:
1888 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
1889 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
1890 // CHECK3-NEXT:    [[ADD30:%.*]] = add i32 [[TMP29]], 1
1891 // CHECK3-NEXT:    [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]]
1892 // CHECK3-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]]
1893 // CHECK3:       omp.inner.for.body32:
1894 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group [[ACC_GRP7]]
1895 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
1896 // CHECK3-NEXT:    [[MUL33:%.*]] = mul i32 [[TMP31]], 1
1897 // CHECK3-NEXT:    [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]]
1898 // CHECK3-NEXT:    store i32 [[ADD34]], ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]]
1899 // CHECK3-NEXT:    [[TMP32:%.*]] = load i32, ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]]
1900 // CHECK3-NEXT:    [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64
1901 // CHECK3-NEXT:    [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM35]]
1902 // CHECK3-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX36]], align 4, !llvm.access.group [[ACC_GRP7]]
1903 // CHECK3-NEXT:    call void @__captured_stmt.1(ptr [[I28]]), !llvm.access.group [[ACC_GRP7]]
1904 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE37:%.*]]
1905 // CHECK3:       omp.body.continue37:
1906 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC38:%.*]]
1907 // CHECK3:       omp.inner.for.inc38:
1908 // CHECK3-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
1909 // CHECK3-NEXT:    [[ADD39:%.*]] = add i32 [[TMP33]], 1
1910 // CHECK3-NEXT:    store i32 [[ADD39]], ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
1911 // CHECK3-NEXT:    call void @__kmpc_dispatch_fini_4u(ptr @[[GLOB1]], i32 [[TMP0]]), !llvm.access.group [[ACC_GRP7]]
1912 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP8:![0-9]+]]
1913 // CHECK3:       omp.inner.for.end40:
1914 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1915 // CHECK3:       omp.dispatch.inc:
1916 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
1917 // CHECK3:       omp.dispatch.end:
1918 // CHECK3-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])
1919 // CHECK3-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1920 // CHECK3-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
1921 // CHECK3-NEXT:    br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1922 // CHECK3:       .omp.final.then:
1923 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1924 // CHECK3-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
1925 // CHECK3-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1926 // CHECK3-NEXT:    [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]]
1927 // CHECK3-NEXT:    [[SUB42:%.*]] = sub i32 [[SUB41]], 1
1928 // CHECK3-NEXT:    [[ADD43:%.*]] = add i32 [[SUB42]], 1
1929 // CHECK3-NEXT:    [[DIV44:%.*]] = udiv i32 [[ADD43]], 1
1930 // CHECK3-NEXT:    [[MUL45:%.*]] = mul i32 [[DIV44]], 1
1931 // CHECK3-NEXT:    [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]]
1932 // CHECK3-NEXT:    store i32 [[ADD46]], ptr [[I28]], align 4
1933 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1934 // CHECK3:       .omp.final.done:
1935 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
1936 // CHECK3:       omp.precond.end:
1937 // CHECK3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])
1938 // CHECK3-NEXT:    ret void
1939 //
1940 //
1941 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt
1942 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4:[0-9]+]] {
1943 // CHECK3-NEXT:  entry:
1944 // CHECK3-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
1945 // CHECK3-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
1946 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
1947 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1948 // CHECK3-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
1949 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
1950 // CHECK3-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4
1951 // CHECK3-NEXT:    ret void
1952 //
1953 //
1954 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt.1
1955 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4]] {
1956 // CHECK3-NEXT:  entry:
1957 // CHECK3-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
1958 // CHECK3-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
1959 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
1960 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1961 // CHECK3-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
1962 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
1963 // CHECK3-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4
1964 // CHECK3-NEXT:    ret void
1965 //
1966 //
1967 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
1968 // CHECK3-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
1969 // CHECK3-IRBUILDER-NEXT:  entry:
1970 // CHECK3-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1971 // CHECK3-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1972 // CHECK3-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1973 // CHECK3-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1974 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1975 // CHECK3-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1976 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1977 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1978 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1979 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1980 // CHECK3-IRBUILDER-NEXT:    [[I:%.*]] = alloca i32, align 4
1981 // CHECK3-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1982 // CHECK3-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1983 // CHECK3-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1984 // CHECK3-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1985 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1986 // CHECK3-IRBUILDER-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
1987 // CHECK3-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1988 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1989 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
1990 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 4571423, i32 1, i32 1)
1991 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1992 // CHECK3-IRBUILDER:       omp.dispatch.cond:
1993 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
1994 // CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1995 // CHECK3-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
1996 // CHECK3-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1997 // CHECK3-IRBUILDER:       omp.dispatch.body:
1998 // CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1999 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 4
2000 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2001 // CHECK3-IRBUILDER:       omp.inner.for.cond:
2002 // CHECK3-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2003 // CHECK3-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2004 // CHECK3-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
2005 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2006 // CHECK3-IRBUILDER:       omp.inner.for.body:
2007 // CHECK3-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2008 // CHECK3-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
2009 // CHECK3-IRBUILDER-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
2010 // CHECK3-IRBUILDER-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
2011 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2012 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
2013 // CHECK3-IRBUILDER-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2014 // CHECK3-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4
2015 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
2016 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 [[IDXPROM]]
2017 // CHECK3-IRBUILDER-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2018 // CHECK3-IRBUILDER-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2019 // CHECK3-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4
2020 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64
2021 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i64 [[IDXPROM3]]
2022 // CHECK3-IRBUILDER-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
2023 // CHECK3-IRBUILDER-NEXT:    [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]]
2024 // CHECK3-IRBUILDER-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2025 // CHECK3-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4
2026 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM6:%.*]] = sext i32 [[TMP12]] to i64
2027 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[IDXPROM6]]
2028 // CHECK3-IRBUILDER-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
2029 // CHECK3-IRBUILDER-NEXT:    [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP13]]
2030 // CHECK3-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2031 // CHECK3-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4
2032 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM9:%.*]] = sext i32 [[TMP15]] to i64
2033 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM9]]
2034 // CHECK3-IRBUILDER-NEXT:    store float [[MUL8]], ptr [[ARRAYIDX10]], align 4
2035 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
2036 // CHECK3-IRBUILDER:       omp.inner.for.body.ordered.after:
2037 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
2038 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2039 // CHECK3-IRBUILDER:       omp.body.continue:
2040 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2041 // CHECK3-IRBUILDER:       omp.inner.for.inc:
2042 // CHECK3-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2043 // CHECK3-IRBUILDER-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
2044 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
2045 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
2046 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM11]])
2047 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]
2048 // CHECK3-IRBUILDER:       omp.inner.for.end:
2049 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2050 // CHECK3-IRBUILDER:       omp.dispatch.inc:
2051 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
2052 // CHECK3-IRBUILDER:       omp.dispatch.end:
2053 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
2054 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM12]])
2055 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM13:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2056 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM13]])
2057 // CHECK3-IRBUILDER-NEXT:    ret void
2058 //
2059 //
2060 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_
2061 // CHECK3-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
2062 // CHECK3-IRBUILDER-NEXT:  entry:
2063 // CHECK3-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2064 // CHECK3-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2065 // CHECK3-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2066 // CHECK3-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2067 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
2068 // CHECK3-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i64, align 8
2069 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
2070 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
2071 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
2072 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2073 // CHECK3-IRBUILDER-NEXT:    [[I:%.*]] = alloca i64, align 8
2074 // CHECK3-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2075 // CHECK3-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2076 // CHECK3-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2077 // CHECK3-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2078 // CHECK3-IRBUILDER-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
2079 // CHECK3-IRBUILDER-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8
2080 // CHECK3-IRBUILDER-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
2081 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2082 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6:[0-9]+]])
2083 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 67, i64 0, i64 16908287, i64 1, i64 1)
2084 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2085 // CHECK3-IRBUILDER:       omp.dispatch.cond:
2086 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6]])
2087 // CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
2088 // CHECK3-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
2089 // CHECK3-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2090 // CHECK3-IRBUILDER:       omp.dispatch.body:
2091 // CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
2092 // CHECK3-IRBUILDER-NEXT:    store i64 [[TMP1]], ptr [[DOTOMP_IV]], align 8
2093 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2094 // CHECK3-IRBUILDER:       omp.inner.for.cond:
2095 // CHECK3-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2096 // CHECK3-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
2097 // CHECK3-IRBUILDER-NEXT:    [[ADD:%.*]] = add i64 [[TMP3]], 1
2098 // CHECK3-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP2]], [[ADD]]
2099 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2100 // CHECK3-IRBUILDER:       omp.inner.for.body:
2101 // CHECK3-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2102 // CHECK3-IRBUILDER-NEXT:    [[MUL:%.*]] = mul i64 [[TMP4]], 127
2103 // CHECK3-IRBUILDER-NEXT:    [[ADD2:%.*]] = add i64 131071, [[MUL]]
2104 // CHECK3-IRBUILDER-NEXT:    store i64 [[ADD2]], ptr [[I]], align 8
2105 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2106 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]])
2107 // CHECK3-IRBUILDER-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2108 // CHECK3-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i64, ptr [[I]], align 8
2109 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP5]], i64 [[TMP6]]
2110 // CHECK3-IRBUILDER-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2111 // CHECK3-IRBUILDER-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2112 // CHECK3-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i64, ptr [[I]], align 8
2113 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP8]], i64 [[TMP9]]
2114 // CHECK3-IRBUILDER-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
2115 // CHECK3-IRBUILDER-NEXT:    [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]]
2116 // CHECK3-IRBUILDER-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2117 // CHECK3-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i64, ptr [[I]], align 8
2118 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]]
2119 // CHECK3-IRBUILDER-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
2120 // CHECK3-IRBUILDER-NEXT:    [[MUL7:%.*]] = fmul float [[MUL5]], [[TMP13]]
2121 // CHECK3-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2122 // CHECK3-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i64, ptr [[I]], align 8
2123 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]]
2124 // CHECK3-IRBUILDER-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX8]], align 4
2125 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
2126 // CHECK3-IRBUILDER:       omp.inner.for.body.ordered.after:
2127 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]])
2128 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2129 // CHECK3-IRBUILDER:       omp.body.continue:
2130 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2131 // CHECK3-IRBUILDER:       omp.inner.for.inc:
2132 // CHECK3-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2133 // CHECK3-IRBUILDER-NEXT:    [[ADD9:%.*]] = add i64 [[TMP16]], 1
2134 // CHECK3-IRBUILDER-NEXT:    store i64 [[ADD9]], ptr [[DOTOMP_IV]], align 8
2135 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6]])
2136 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]])
2137 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]
2138 // CHECK3-IRBUILDER:       omp.inner.for.end:
2139 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2140 // CHECK3-IRBUILDER:       omp.dispatch.inc:
2141 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
2142 // CHECK3-IRBUILDER:       omp.dispatch.end:
2143 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6]])
2144 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM11]])
2145 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2146 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM12]])
2147 // CHECK3-IRBUILDER-NEXT:    ret void
2148 //
2149 //
2150 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_
2151 // CHECK3-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
2152 // CHECK3-IRBUILDER-NEXT:  entry:
2153 // CHECK3-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2154 // CHECK3-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2155 // CHECK3-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2156 // CHECK3-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2157 // CHECK3-IRBUILDER-NEXT:    [[X:%.*]] = alloca i32, align 4
2158 // CHECK3-IRBUILDER-NEXT:    [[Y:%.*]] = alloca i32, align 4
2159 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
2160 // CHECK3-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i8, align 1
2161 // CHECK3-IRBUILDER-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2162 // CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2163 // CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
2164 // CHECK3-IRBUILDER-NEXT:    [[I:%.*]] = alloca i8, align 1
2165 // CHECK3-IRBUILDER-NEXT:    [[X6:%.*]] = alloca i32, align 4
2166 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
2167 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
2168 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
2169 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2170 // CHECK3-IRBUILDER-NEXT:    [[I8:%.*]] = alloca i8, align 1
2171 // CHECK3-IRBUILDER-NEXT:    [[X9:%.*]] = alloca i32, align 4
2172 // CHECK3-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2173 // CHECK3-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2174 // CHECK3-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2175 // CHECK3-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2176 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[X]], align 4
2177 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[Y]], align 4
2178 // CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = load i32, ptr [[Y]], align 4
2179 // CHECK3-IRBUILDER-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP0]] to i8
2180 // CHECK3-IRBUILDER-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1
2181 // CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2182 // CHECK3-IRBUILDER-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP1]] to i32
2183 // CHECK3-IRBUILDER-NEXT:    [[SUB:%.*]] = sub i32 57, [[CONV3]]
2184 // CHECK3-IRBUILDER-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], 1
2185 // CHECK3-IRBUILDER-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
2186 // CHECK3-IRBUILDER-NEXT:    [[CONV4:%.*]] = zext i32 [[DIV]] to i64
2187 // CHECK3-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11
2188 // CHECK3-IRBUILDER-NEXT:    [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1
2189 // CHECK3-IRBUILDER-NEXT:    store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8
2190 // CHECK3-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2191 // CHECK3-IRBUILDER-NEXT:    store i8 [[TMP2]], ptr [[I]], align 1
2192 // CHECK3-IRBUILDER-NEXT:    store i32 11, ptr [[X6]], align 4
2193 // CHECK3-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2194 // CHECK3-IRBUILDER-NEXT:    [[CONV7:%.*]] = sext i8 [[TMP3]] to i32
2195 // CHECK3-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57
2196 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
2197 // CHECK3-IRBUILDER:       omp.precond.then:
2198 // CHECK3-IRBUILDER-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
2199 // CHECK3-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
2200 // CHECK3-IRBUILDER-NEXT:    store i64 [[TMP4]], ptr [[DOTOMP_UB]], align 8
2201 // CHECK3-IRBUILDER-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
2202 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2203 // CHECK3-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
2204 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8:[0-9]+]])
2205 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 70, i64 0, i64 [[TMP5]], i64 1, i64 1)
2206 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2207 // CHECK3-IRBUILDER:       omp.dispatch.cond:
2208 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8]])
2209 // CHECK3-IRBUILDER-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
2210 // CHECK3-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
2211 // CHECK3-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2212 // CHECK3-IRBUILDER:       omp.dispatch.body:
2213 // CHECK3-IRBUILDER-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
2214 // CHECK3-IRBUILDER-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
2215 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2216 // CHECK3-IRBUILDER:       omp.inner.for.cond:
2217 // CHECK3-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2218 // CHECK3-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
2219 // CHECK3-IRBUILDER-NEXT:    [[CMP11:%.*]] = icmp sle i64 [[TMP8]], [[TMP9]]
2220 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2221 // CHECK3-IRBUILDER:       omp.inner.for.body:
2222 // CHECK3-IRBUILDER-NEXT:    [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2223 // CHECK3-IRBUILDER-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP10]] to i64
2224 // CHECK3-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2225 // CHECK3-IRBUILDER-NEXT:    [[DIV13:%.*]] = sdiv i64 [[TMP11]], 11
2226 // CHECK3-IRBUILDER-NEXT:    [[MUL14:%.*]] = mul nsw i64 [[DIV13]], 1
2227 // CHECK3-IRBUILDER-NEXT:    [[ADD15:%.*]] = add nsw i64 [[CONV12]], [[MUL14]]
2228 // CHECK3-IRBUILDER-NEXT:    [[CONV16:%.*]] = trunc i64 [[ADD15]] to i8
2229 // CHECK3-IRBUILDER-NEXT:    store i8 [[CONV16]], ptr [[I8]], align 1
2230 // CHECK3-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2231 // CHECK3-IRBUILDER-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2232 // CHECK3-IRBUILDER-NEXT:    [[DIV17:%.*]] = sdiv i64 [[TMP13]], 11
2233 // CHECK3-IRBUILDER-NEXT:    [[MUL18:%.*]] = mul nsw i64 [[DIV17]], 11
2234 // CHECK3-IRBUILDER-NEXT:    [[SUB19:%.*]] = sub nsw i64 [[TMP12]], [[MUL18]]
2235 // CHECK3-IRBUILDER-NEXT:    [[MUL20:%.*]] = mul nsw i64 [[SUB19]], 1
2236 // CHECK3-IRBUILDER-NEXT:    [[SUB21:%.*]] = sub nsw i64 11, [[MUL20]]
2237 // CHECK3-IRBUILDER-NEXT:    [[CONV22:%.*]] = trunc i64 [[SUB21]] to i32
2238 // CHECK3-IRBUILDER-NEXT:    store i32 [[CONV22]], ptr [[X9]], align 4
2239 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM23:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2240 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]])
2241 // CHECK3-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2242 // CHECK3-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i8, ptr [[I8]], align 1
2243 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP15]] to i64
2244 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]]
2245 // CHECK3-IRBUILDER-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2246 // CHECK3-IRBUILDER-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2247 // CHECK3-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i8, ptr [[I8]], align 1
2248 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM24:%.*]] = sext i8 [[TMP18]] to i64
2249 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM24]]
2250 // CHECK3-IRBUILDER-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX25]], align 4
2251 // CHECK3-IRBUILDER-NEXT:    [[MUL26:%.*]] = fmul float [[TMP16]], [[TMP19]]
2252 // CHECK3-IRBUILDER-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2253 // CHECK3-IRBUILDER-NEXT:    [[TMP21:%.*]] = load i8, ptr [[I8]], align 1
2254 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM27:%.*]] = sext i8 [[TMP21]] to i64
2255 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM27]]
2256 // CHECK3-IRBUILDER-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX28]], align 4
2257 // CHECK3-IRBUILDER-NEXT:    [[MUL29:%.*]] = fmul float [[MUL26]], [[TMP22]]
2258 // CHECK3-IRBUILDER-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2259 // CHECK3-IRBUILDER-NEXT:    [[TMP24:%.*]] = load i8, ptr [[I8]], align 1
2260 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM30:%.*]] = sext i8 [[TMP24]] to i64
2261 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX31:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM30]]
2262 // CHECK3-IRBUILDER-NEXT:    store float [[MUL29]], ptr [[ARRAYIDX31]], align 4
2263 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
2264 // CHECK3-IRBUILDER:       omp.inner.for.body.ordered.after:
2265 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]])
2266 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2267 // CHECK3-IRBUILDER:       omp.body.continue:
2268 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2269 // CHECK3-IRBUILDER:       omp.inner.for.inc:
2270 // CHECK3-IRBUILDER-NEXT:    [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2271 // CHECK3-IRBUILDER-NEXT:    [[ADD32:%.*]] = add nsw i64 [[TMP25]], 1
2272 // CHECK3-IRBUILDER-NEXT:    store i64 [[ADD32]], ptr [[DOTOMP_IV]], align 8
2273 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM33:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8]])
2274 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM33]])
2275 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]
2276 // CHECK3-IRBUILDER:       omp.inner.for.end:
2277 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2278 // CHECK3-IRBUILDER:       omp.dispatch.inc:
2279 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
2280 // CHECK3-IRBUILDER:       omp.dispatch.end:
2281 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM34:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8]])
2282 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM34]])
2283 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_PRECOND_END]]
2284 // CHECK3-IRBUILDER:       omp.precond.end:
2285 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM35:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2286 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM35]])
2287 // CHECK3-IRBUILDER-NEXT:    ret void
2288 //
2289 //
2290 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_
2291 // CHECK3-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
2292 // CHECK3-IRBUILDER-NEXT:  entry:
2293 // CHECK3-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2294 // CHECK3-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2295 // CHECK3-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2296 // CHECK3-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2297 // CHECK3-IRBUILDER-NEXT:    [[X:%.*]] = alloca i32, align 4
2298 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2299 // CHECK3-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i8, align 1
2300 // CHECK3-IRBUILDER-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2301 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2302 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2303 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2304 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2305 // CHECK3-IRBUILDER-NEXT:    [[I:%.*]] = alloca i8, align 1
2306 // CHECK3-IRBUILDER-NEXT:    [[X2:%.*]] = alloca i32, align 4
2307 // CHECK3-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2308 // CHECK3-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2309 // CHECK3-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2310 // CHECK3-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2311 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[X]], align 4
2312 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2313 // CHECK3-IRBUILDER-NEXT:    store i32 199, ptr [[DOTOMP_UB]], align 4
2314 // CHECK3-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2315 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2316 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10:[0-9]+]])
2317 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 69, i32 0, i32 199, i32 1, i32 1)
2318 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2319 // CHECK3-IRBUILDER:       omp.dispatch.cond:
2320 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10]])
2321 // CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
2322 // CHECK3-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
2323 // CHECK3-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2324 // CHECK3-IRBUILDER:       omp.dispatch.body:
2325 // CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2326 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 4
2327 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2328 // CHECK3-IRBUILDER:       omp.inner.for.cond:
2329 // CHECK3-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2330 // CHECK3-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2331 // CHECK3-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
2332 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2333 // CHECK3-IRBUILDER:       omp.inner.for.body:
2334 // CHECK3-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2335 // CHECK3-IRBUILDER-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP4]], 20
2336 // CHECK3-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
2337 // CHECK3-IRBUILDER-NEXT:    [[ADD:%.*]] = add nsw i32 48, [[MUL]]
2338 // CHECK3-IRBUILDER-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i8
2339 // CHECK3-IRBUILDER-NEXT:    store i8 [[CONV]], ptr [[I]], align 1
2340 // CHECK3-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2341 // CHECK3-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2342 // CHECK3-IRBUILDER-NEXT:    [[DIV4:%.*]] = sdiv i32 [[TMP6]], 20
2343 // CHECK3-IRBUILDER-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 20
2344 // CHECK3-IRBUILDER-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP5]], [[MUL5]]
2345 // CHECK3-IRBUILDER-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1
2346 // CHECK3-IRBUILDER-NEXT:    [[ADD7:%.*]] = add nsw i32 -10, [[MUL6]]
2347 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD7]], ptr [[X2]], align 4
2348 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM8:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2349 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]])
2350 // CHECK3-IRBUILDER-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2351 // CHECK3-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i8, ptr [[I]], align 1
2352 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP8]] to i64
2353 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP7]], i64 [[IDXPROM]]
2354 // CHECK3-IRBUILDER-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2355 // CHECK3-IRBUILDER-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2356 // CHECK3-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i8, ptr [[I]], align 1
2357 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM9:%.*]] = zext i8 [[TMP11]] to i64
2358 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP10]], i64 [[IDXPROM9]]
2359 // CHECK3-IRBUILDER-NEXT:    [[TMP12:%.*]] = load float, ptr [[ARRAYIDX10]], align 4
2360 // CHECK3-IRBUILDER-NEXT:    [[MUL11:%.*]] = fmul float [[TMP9]], [[TMP12]]
2361 // CHECK3-IRBUILDER-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2362 // CHECK3-IRBUILDER-NEXT:    [[TMP14:%.*]] = load i8, ptr [[I]], align 1
2363 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM12:%.*]] = zext i8 [[TMP14]] to i64
2364 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i64 [[IDXPROM12]]
2365 // CHECK3-IRBUILDER-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX13]], align 4
2366 // CHECK3-IRBUILDER-NEXT:    [[MUL14:%.*]] = fmul float [[MUL11]], [[TMP15]]
2367 // CHECK3-IRBUILDER-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2368 // CHECK3-IRBUILDER-NEXT:    [[TMP17:%.*]] = load i8, ptr [[I]], align 1
2369 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM15:%.*]] = zext i8 [[TMP17]] to i64
2370 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM15]]
2371 // CHECK3-IRBUILDER-NEXT:    store float [[MUL14]], ptr [[ARRAYIDX16]], align 4
2372 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
2373 // CHECK3-IRBUILDER:       omp.inner.for.body.ordered.after:
2374 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]])
2375 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2376 // CHECK3-IRBUILDER:       omp.body.continue:
2377 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2378 // CHECK3-IRBUILDER:       omp.inner.for.inc:
2379 // CHECK3-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2380 // CHECK3-IRBUILDER-NEXT:    [[ADD17:%.*]] = add nsw i32 [[TMP18]], 1
2381 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4
2382 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM18:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10]])
2383 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM18]])
2384 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]
2385 // CHECK3-IRBUILDER:       omp.inner.for.end:
2386 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2387 // CHECK3-IRBUILDER:       omp.dispatch.inc:
2388 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
2389 // CHECK3-IRBUILDER:       omp.dispatch.end:
2390 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM19:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10]])
2391 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM19]])
2392 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM20:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2393 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM20]])
2394 // CHECK3-IRBUILDER-NEXT:    ret void
2395 //
2396 //
2397 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z8foo_simdii
2398 // CHECK3-IRBUILDER-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR3:[0-9]+]] {
2399 // CHECK3-IRBUILDER-NEXT:  entry:
2400 // CHECK3-IRBUILDER-NEXT:    [[LOW_ADDR:%.*]] = alloca i32, align 4
2401 // CHECK3-IRBUILDER-NEXT:    [[UP_ADDR:%.*]] = alloca i32, align 4
2402 // CHECK3-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2403 // CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2404 // CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
2405 // CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
2406 // CHECK3-IRBUILDER-NEXT:    [[I:%.*]] = alloca i32, align 4
2407 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2408 // CHECK3-IRBUILDER-NEXT:    [[I5:%.*]] = alloca i32, align 4
2409 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV16:%.*]] = alloca i32, align 4
2410 // CHECK3-IRBUILDER-NEXT:    [[_TMP17:%.*]] = alloca i32, align 4
2411 // CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4
2412 // CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4
2413 // CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4
2414 // CHECK3-IRBUILDER-NEXT:    [[I26:%.*]] = alloca i32, align 4
2415 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2416 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2417 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2418 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2419 // CHECK3-IRBUILDER-NEXT:    [[I28:%.*]] = alloca i32, align 4
2420 // CHECK3-IRBUILDER-NEXT:    store i32 [[LOW]], ptr [[LOW_ADDR]], align 4
2421 // CHECK3-IRBUILDER-NEXT:    store i32 [[UP]], ptr [[UP_ADDR]], align 4
2422 // CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
2423 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
2424 // CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[UP_ADDR]], align 4
2425 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4
2426 // CHECK3-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2427 // CHECK3-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2428 // CHECK3-IRBUILDER-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
2429 // CHECK3-IRBUILDER-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
2430 // CHECK3-IRBUILDER-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
2431 // CHECK3-IRBUILDER-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
2432 // CHECK3-IRBUILDER-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
2433 // CHECK3-IRBUILDER-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
2434 // CHECK3-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2435 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP4]], ptr [[I]], align 4
2436 // CHECK3-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2437 // CHECK3-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2438 // CHECK3-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]]
2439 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
2440 // CHECK3-IRBUILDER:       simd.if.then:
2441 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IV]], align 4
2442 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2443 // CHECK3-IRBUILDER:       omp.inner.for.cond:
2444 // CHECK3-IRBUILDER-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
2445 // CHECK3-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
2446 // CHECK3-IRBUILDER-NEXT:    [[ADD6:%.*]] = add i32 [[TMP8]], 1
2447 // CHECK3-IRBUILDER-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]]
2448 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2449 // CHECK3-IRBUILDER:       omp.inner.for.body:
2450 // CHECK3-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP3]]
2451 // CHECK3-IRBUILDER-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
2452 // CHECK3-IRBUILDER-NEXT:    [[MUL:%.*]] = mul i32 [[TMP10]], 1
2453 // CHECK3-IRBUILDER-NEXT:    [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]]
2454 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]]
2455 // CHECK3-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]]
2456 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
2457 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
2458 // CHECK3-IRBUILDER-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
2459 // CHECK3-IRBUILDER-NEXT:    call void @__captured_stmt(ptr [[I5]]), !llvm.access.group [[ACC_GRP3]]
2460 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
2461 // CHECK3-IRBUILDER:       omp.inner.for.body.ordered.after:
2462 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2463 // CHECK3-IRBUILDER:       omp.body.continue:
2464 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2465 // CHECK3-IRBUILDER:       omp.inner.for.inc:
2466 // CHECK3-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
2467 // CHECK3-IRBUILDER-NEXT:    [[ADD9:%.*]] = add i32 [[TMP12]], 1
2468 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
2469 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
2470 // CHECK3-IRBUILDER:       omp.inner.for.end:
2471 // CHECK3-IRBUILDER-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2472 // CHECK3-IRBUILDER-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2473 // CHECK3-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2474 // CHECK3-IRBUILDER-NEXT:    [[SUB10:%.*]] = sub i32 [[TMP14]], [[TMP15]]
2475 // CHECK3-IRBUILDER-NEXT:    [[SUB11:%.*]] = sub i32 [[SUB10]], 1
2476 // CHECK3-IRBUILDER-NEXT:    [[ADD12:%.*]] = add i32 [[SUB11]], 1
2477 // CHECK3-IRBUILDER-NEXT:    [[DIV13:%.*]] = udiv i32 [[ADD12]], 1
2478 // CHECK3-IRBUILDER-NEXT:    [[MUL14:%.*]] = mul i32 [[DIV13]], 1
2479 // CHECK3-IRBUILDER-NEXT:    [[ADD15:%.*]] = add i32 [[TMP13]], [[MUL14]]
2480 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD15]], ptr [[I5]], align 4
2481 // CHECK3-IRBUILDER-NEXT:    br label [[SIMD_IF_END]]
2482 // CHECK3-IRBUILDER:       simd.if.end:
2483 // CHECK3-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
2484 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_18]], align 4
2485 // CHECK3-IRBUILDER-NEXT:    [[TMP17:%.*]] = load i32, ptr [[UP_ADDR]], align 4
2486 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP17]], ptr [[DOTCAPTURE_EXPR_19]], align 4
2487 // CHECK3-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
2488 // CHECK3-IRBUILDER-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
2489 // CHECK3-IRBUILDER-NEXT:    [[SUB21:%.*]] = sub i32 [[TMP18]], [[TMP19]]
2490 // CHECK3-IRBUILDER-NEXT:    [[SUB22:%.*]] = sub i32 [[SUB21]], 1
2491 // CHECK3-IRBUILDER-NEXT:    [[ADD23:%.*]] = add i32 [[SUB22]], 1
2492 // CHECK3-IRBUILDER-NEXT:    [[DIV24:%.*]] = udiv i32 [[ADD23]], 1
2493 // CHECK3-IRBUILDER-NEXT:    [[SUB25:%.*]] = sub i32 [[DIV24]], 1
2494 // CHECK3-IRBUILDER-NEXT:    store i32 [[SUB25]], ptr [[DOTCAPTURE_EXPR_20]], align 4
2495 // CHECK3-IRBUILDER-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
2496 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP20]], ptr [[I26]], align 4
2497 // CHECK3-IRBUILDER-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
2498 // CHECK3-IRBUILDER-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
2499 // CHECK3-IRBUILDER-NEXT:    [[CMP27:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]]
2500 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
2501 // CHECK3-IRBUILDER:       omp.precond.then:
2502 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2503 // CHECK3-IRBUILDER-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
2504 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP23]], ptr [[DOTOMP_UB]], align 4
2505 // CHECK3-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2506 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2507 // CHECK3-IRBUILDER-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
2508 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12:[0-9]+]])
2509 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 [[TMP24]], i32 1, i32 1)
2510 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2511 // CHECK3-IRBUILDER:       omp.dispatch.cond:
2512 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM29:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12]])
2513 // CHECK3-IRBUILDER-NEXT:    [[TMP25:%.*]] = call i32 @__kmpc_dispatch_next_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM29]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
2514 // CHECK3-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP25]], 0
2515 // CHECK3-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2516 // CHECK3-IRBUILDER:       omp.dispatch.body:
2517 // CHECK3-IRBUILDER-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2518 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP26]], ptr [[DOTOMP_IV16]], align 4
2519 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
2520 // CHECK3-IRBUILDER:       omp.inner.for.cond30:
2521 // CHECK3-IRBUILDER-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
2522 // CHECK3-IRBUILDER-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
2523 // CHECK3-IRBUILDER-NEXT:    [[ADD31:%.*]] = add i32 [[TMP28]], 1
2524 // CHECK3-IRBUILDER-NEXT:    [[CMP32:%.*]] = icmp ult i32 [[TMP27]], [[ADD31]]
2525 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP32]], label [[OMP_INNER_FOR_BODY33:%.*]], label [[OMP_INNER_FOR_END42:%.*]]
2526 // CHECK3-IRBUILDER:       omp.inner.for.body33:
2527 // CHECK3-IRBUILDER-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group [[ACC_GRP7]]
2528 // CHECK3-IRBUILDER-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
2529 // CHECK3-IRBUILDER-NEXT:    [[MUL34:%.*]] = mul i32 [[TMP30]], 1
2530 // CHECK3-IRBUILDER-NEXT:    [[ADD35:%.*]] = add i32 [[TMP29]], [[MUL34]]
2531 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD35]], ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]]
2532 // CHECK3-IRBUILDER-NEXT:    [[TMP31:%.*]] = load i32, ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]]
2533 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64
2534 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM36]]
2535 // CHECK3-IRBUILDER-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX37]], align 4, !llvm.access.group [[ACC_GRP7]]
2536 // CHECK3-IRBUILDER-NEXT:    call void @__captured_stmt.1(ptr [[I28]]), !llvm.access.group [[ACC_GRP7]]
2537 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY33_ORDERED_AFTER:%.*]]
2538 // CHECK3-IRBUILDER:       omp.inner.for.body33.ordered.after:
2539 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE38:%.*]]
2540 // CHECK3-IRBUILDER:       omp.body.continue38:
2541 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC39:%.*]]
2542 // CHECK3-IRBUILDER:       omp.inner.for.inc39:
2543 // CHECK3-IRBUILDER-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
2544 // CHECK3-IRBUILDER-NEXT:    [[ADD40:%.*]] = add i32 [[TMP32]], 1
2545 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD40]], ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
2546 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM41:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12]])
2547 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM41]]), !llvm.access.group [[ACC_GRP7]]
2548 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP8:![0-9]+]]
2549 // CHECK3-IRBUILDER:       omp.inner.for.end42:
2550 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2551 // CHECK3-IRBUILDER:       omp.dispatch.inc:
2552 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
2553 // CHECK3-IRBUILDER:       omp.dispatch.end:
2554 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM43:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12]])
2555 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM43]])
2556 // CHECK3-IRBUILDER-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2557 // CHECK3-IRBUILDER-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
2558 // CHECK3-IRBUILDER-NEXT:    br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2559 // CHECK3-IRBUILDER:       .omp.final.then:
2560 // CHECK3-IRBUILDER-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
2561 // CHECK3-IRBUILDER-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
2562 // CHECK3-IRBUILDER-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
2563 // CHECK3-IRBUILDER-NEXT:    [[SUB44:%.*]] = sub i32 [[TMP36]], [[TMP37]]
2564 // CHECK3-IRBUILDER-NEXT:    [[SUB45:%.*]] = sub i32 [[SUB44]], 1
2565 // CHECK3-IRBUILDER-NEXT:    [[ADD46:%.*]] = add i32 [[SUB45]], 1
2566 // CHECK3-IRBUILDER-NEXT:    [[DIV47:%.*]] = udiv i32 [[ADD46]], 1
2567 // CHECK3-IRBUILDER-NEXT:    [[MUL48:%.*]] = mul i32 [[DIV47]], 1
2568 // CHECK3-IRBUILDER-NEXT:    [[ADD49:%.*]] = add i32 [[TMP35]], [[MUL48]]
2569 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD49]], ptr [[I28]], align 4
2570 // CHECK3-IRBUILDER-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2571 // CHECK3-IRBUILDER:       .omp.final.done:
2572 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_PRECOND_END]]
2573 // CHECK3-IRBUILDER:       omp.precond.end:
2574 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM50:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2575 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM50]])
2576 // CHECK3-IRBUILDER-NEXT:    ret void
2577 //
2578 //
2579 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt
2580 // CHECK3-IRBUILDER-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4:[0-9]+]] {
2581 // CHECK3-IRBUILDER-NEXT:  entry:
2582 // CHECK3-IRBUILDER-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
2583 // CHECK3-IRBUILDER-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
2584 // CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
2585 // CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2586 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
2587 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
2588 // CHECK3-IRBUILDER-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4
2589 // CHECK3-IRBUILDER-NEXT:    ret void
2590 //
2591 //
2592 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt.1
2593 // CHECK3-IRBUILDER-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4]] {
2594 // CHECK3-IRBUILDER-NEXT:  entry:
2595 // CHECK3-IRBUILDER-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
2596 // CHECK3-IRBUILDER-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
2597 // CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
2598 // CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2599 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
2600 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
2601 // CHECK3-IRBUILDER-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4
2602 // CHECK3-IRBUILDER-NEXT:    ret void
2603 //
2604 //
2605 // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
2606 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
2607 // CHECK5-NEXT:  entry:
2608 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2609 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2610 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2611 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2612 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
2613 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2614 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2615 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2616 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2617 // CHECK5-NEXT:    store i32 32000000, ptr [[I]], align 4
2618 // CHECK5-NEXT:    br label [[FOR_COND:%.*]]
2619 // CHECK5:       for.cond:
2620 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[I]], align 4
2621 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33
2622 // CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
2623 // CHECK5:       for.body:
2624 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2625 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 4
2626 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64
2627 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i64 [[IDXPROM]]
2628 // CHECK5-NEXT:    [[TMP3:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2629 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2630 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4
2631 // CHECK5-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64
2632 // CHECK5-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 [[IDXPROM1]]
2633 // CHECK5-NEXT:    [[TMP6:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
2634 // CHECK5-NEXT:    [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]]
2635 // CHECK5-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2636 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[I]], align 4
2637 // CHECK5-NEXT:    [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64
2638 // CHECK5-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i64 [[IDXPROM3]]
2639 // CHECK5-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
2640 // CHECK5-NEXT:    [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]]
2641 // CHECK5-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2642 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
2643 // CHECK5-NEXT:    [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64
2644 // CHECK5-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i64 [[IDXPROM6]]
2645 // CHECK5-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX7]], align 4
2646 // CHECK5-NEXT:    br label [[FOR_INC:%.*]]
2647 // CHECK5:       for.inc:
2648 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4
2649 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP12]], -7
2650 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
2651 // CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
2652 // CHECK5:       for.end:
2653 // CHECK5-NEXT:    ret void
2654 //
2655 //
2656 // CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_
2657 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
2658 // CHECK5-NEXT:  entry:
2659 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2660 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2661 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2662 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2663 // CHECK5-NEXT:    [[I:%.*]] = alloca i64, align 8
2664 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2665 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2666 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2667 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2668 // CHECK5-NEXT:    store i64 131071, ptr [[I]], align 8
2669 // CHECK5-NEXT:    br label [[FOR_COND:%.*]]
2670 // CHECK5:       for.cond:
2671 // CHECK5-NEXT:    [[TMP0:%.*]] = load i64, ptr [[I]], align 8
2672 // CHECK5-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647
2673 // CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
2674 // CHECK5:       for.body:
2675 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2676 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, ptr [[I]], align 8
2677 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP1]], i64 [[TMP2]]
2678 // CHECK5-NEXT:    [[TMP3:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2679 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2680 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, ptr [[I]], align 8
2681 // CHECK5-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw float, ptr [[TMP4]], i64 [[TMP5]]
2682 // CHECK5-NEXT:    [[TMP6:%.*]] = load float, ptr [[ARRAYIDX1]], align 4
2683 // CHECK5-NEXT:    [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]]
2684 // CHECK5-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2685 // CHECK5-NEXT:    [[TMP8:%.*]] = load i64, ptr [[I]], align 8
2686 // CHECK5-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP7]], i64 [[TMP8]]
2687 // CHECK5-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
2688 // CHECK5-NEXT:    [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]]
2689 // CHECK5-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2690 // CHECK5-NEXT:    [[TMP11:%.*]] = load i64, ptr [[I]], align 8
2691 // CHECK5-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP10]], i64 [[TMP11]]
2692 // CHECK5-NEXT:    store float [[MUL3]], ptr [[ARRAYIDX4]], align 4
2693 // CHECK5-NEXT:    br label [[FOR_INC:%.*]]
2694 // CHECK5:       for.inc:
2695 // CHECK5-NEXT:    [[TMP12:%.*]] = load i64, ptr [[I]], align 8
2696 // CHECK5-NEXT:    [[ADD:%.*]] = add i64 [[TMP12]], 127
2697 // CHECK5-NEXT:    store i64 [[ADD]], ptr [[I]], align 8
2698 // CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
2699 // CHECK5:       for.end:
2700 // CHECK5-NEXT:    ret void
2701 //
2702 //
2703 // CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_
2704 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
2705 // CHECK5-NEXT:  entry:
2706 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2707 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2708 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2709 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2710 // CHECK5-NEXT:    [[X:%.*]] = alloca i32, align 4
2711 // CHECK5-NEXT:    [[Y:%.*]] = alloca i32, align 4
2712 // CHECK5-NEXT:    [[I:%.*]] = alloca i8, align 1
2713 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2714 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2715 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2716 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2717 // CHECK5-NEXT:    store i32 0, ptr [[X]], align 4
2718 // CHECK5-NEXT:    store i32 0, ptr [[Y]], align 4
2719 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[Y]], align 4
2720 // CHECK5-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP0]] to i8
2721 // CHECK5-NEXT:    store i8 [[CONV]], ptr [[I]], align 1
2722 // CHECK5-NEXT:    br label [[FOR_COND:%.*]]
2723 // CHECK5:       for.cond:
2724 // CHECK5-NEXT:    [[TMP1:%.*]] = load i8, ptr [[I]], align 1
2725 // CHECK5-NEXT:    [[CONV1:%.*]] = sext i8 [[TMP1]] to i32
2726 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57
2727 // CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]]
2728 // CHECK5:       for.body:
2729 // CHECK5-NEXT:    store i32 11, ptr [[X]], align 4
2730 // CHECK5-NEXT:    br label [[FOR_COND2:%.*]]
2731 // CHECK5:       for.cond2:
2732 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[X]], align 4
2733 // CHECK5-NEXT:    [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0
2734 // CHECK5-NEXT:    br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]]
2735 // CHECK5:       for.body4:
2736 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2737 // CHECK5-NEXT:    [[TMP4:%.*]] = load i8, ptr [[I]], align 1
2738 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64
2739 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i64 [[IDXPROM]]
2740 // CHECK5-NEXT:    [[TMP5:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2741 // CHECK5-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2742 // CHECK5-NEXT:    [[TMP7:%.*]] = load i8, ptr [[I]], align 1
2743 // CHECK5-NEXT:    [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64
2744 // CHECK5-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i64 [[IDXPROM5]]
2745 // CHECK5-NEXT:    [[TMP8:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
2746 // CHECK5-NEXT:    [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]]
2747 // CHECK5-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2748 // CHECK5-NEXT:    [[TMP10:%.*]] = load i8, ptr [[I]], align 1
2749 // CHECK5-NEXT:    [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64
2750 // CHECK5-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i64 [[IDXPROM7]]
2751 // CHECK5-NEXT:    [[TMP11:%.*]] = load float, ptr [[ARRAYIDX8]], align 4
2752 // CHECK5-NEXT:    [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]]
2753 // CHECK5-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2754 // CHECK5-NEXT:    [[TMP13:%.*]] = load i8, ptr [[I]], align 1
2755 // CHECK5-NEXT:    [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64
2756 // CHECK5-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM10]]
2757 // CHECK5-NEXT:    store float [[MUL9]], ptr [[ARRAYIDX11]], align 4
2758 // CHECK5-NEXT:    br label [[FOR_INC:%.*]]
2759 // CHECK5:       for.inc:
2760 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, ptr [[X]], align 4
2761 // CHECK5-NEXT:    [[DEC:%.*]] = add i32 [[TMP14]], -1
2762 // CHECK5-NEXT:    store i32 [[DEC]], ptr [[X]], align 4
2763 // CHECK5-NEXT:    br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]]
2764 // CHECK5:       for.end:
2765 // CHECK5-NEXT:    br label [[FOR_INC12:%.*]]
2766 // CHECK5:       for.inc12:
2767 // CHECK5-NEXT:    [[TMP15:%.*]] = load i8, ptr [[I]], align 1
2768 // CHECK5-NEXT:    [[INC:%.*]] = add i8 [[TMP15]], 1
2769 // CHECK5-NEXT:    store i8 [[INC]], ptr [[I]], align 1
2770 // CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
2771 // CHECK5:       for.end13:
2772 // CHECK5-NEXT:    ret void
2773 //
2774 //
2775 // CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_
2776 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
2777 // CHECK5-NEXT:  entry:
2778 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2779 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2780 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2781 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2782 // CHECK5-NEXT:    [[X:%.*]] = alloca i32, align 4
2783 // CHECK5-NEXT:    [[I:%.*]] = alloca i8, align 1
2784 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2785 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2786 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2787 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2788 // CHECK5-NEXT:    store i32 0, ptr [[X]], align 4
2789 // CHECK5-NEXT:    store i8 48, ptr [[I]], align 1
2790 // CHECK5-NEXT:    br label [[FOR_COND:%.*]]
2791 // CHECK5:       for.cond:
2792 // CHECK5-NEXT:    [[TMP0:%.*]] = load i8, ptr [[I]], align 1
2793 // CHECK5-NEXT:    [[CONV:%.*]] = zext i8 [[TMP0]] to i32
2794 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV]], 57
2795 // CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]]
2796 // CHECK5:       for.body:
2797 // CHECK5-NEXT:    store i32 -10, ptr [[X]], align 4
2798 // CHECK5-NEXT:    br label [[FOR_COND1:%.*]]
2799 // CHECK5:       for.cond1:
2800 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[X]], align 4
2801 // CHECK5-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10
2802 // CHECK5-NEXT:    br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]]
2803 // CHECK5:       for.body3:
2804 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2805 // CHECK5-NEXT:    [[TMP3:%.*]] = load i8, ptr [[I]], align 1
2806 // CHECK5-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64
2807 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP2]], i64 [[IDXPROM]]
2808 // CHECK5-NEXT:    [[TMP4:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2809 // CHECK5-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2810 // CHECK5-NEXT:    [[TMP6:%.*]] = load i8, ptr [[I]], align 1
2811 // CHECK5-NEXT:    [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64
2812 // CHECK5-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds nuw float, ptr [[TMP5]], i64 [[IDXPROM4]]
2813 // CHECK5-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX5]], align 4
2814 // CHECK5-NEXT:    [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]]
2815 // CHECK5-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2816 // CHECK5-NEXT:    [[TMP9:%.*]] = load i8, ptr [[I]], align 1
2817 // CHECK5-NEXT:    [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64
2818 // CHECK5-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP8]], i64 [[IDXPROM6]]
2819 // CHECK5-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
2820 // CHECK5-NEXT:    [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]]
2821 // CHECK5-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2822 // CHECK5-NEXT:    [[TMP12:%.*]] = load i8, ptr [[I]], align 1
2823 // CHECK5-NEXT:    [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64
2824 // CHECK5-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[IDXPROM9]]
2825 // CHECK5-NEXT:    store float [[MUL8]], ptr [[ARRAYIDX10]], align 4
2826 // CHECK5-NEXT:    br label [[FOR_INC:%.*]]
2827 // CHECK5:       for.inc:
2828 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[X]], align 4
2829 // CHECK5-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP13]], 1
2830 // CHECK5-NEXT:    store i32 [[INC]], ptr [[X]], align 4
2831 // CHECK5-NEXT:    br label [[FOR_COND1]], !llvm.loop [[LOOP7:![0-9]+]]
2832 // CHECK5:       for.end:
2833 // CHECK5-NEXT:    br label [[FOR_INC11:%.*]]
2834 // CHECK5:       for.inc11:
2835 // CHECK5-NEXT:    [[TMP14:%.*]] = load i8, ptr [[I]], align 1
2836 // CHECK5-NEXT:    [[INC12:%.*]] = add i8 [[TMP14]], 1
2837 // CHECK5-NEXT:    store i8 [[INC12]], ptr [[I]], align 1
2838 // CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
2839 // CHECK5:       for.end13:
2840 // CHECK5-NEXT:    ret void
2841 //
2842 //
2843 // CHECK5-LABEL: define {{[^@]+}}@_Z8foo_simdii
2844 // CHECK5-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] {
2845 // CHECK5-NEXT:  entry:
2846 // CHECK5-NEXT:    [[LOW_ADDR:%.*]] = alloca i32, align 4
2847 // CHECK5-NEXT:    [[UP_ADDR:%.*]] = alloca i32, align 4
2848 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2849 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2850 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
2851 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
2852 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
2853 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2854 // CHECK5-NEXT:    [[I5:%.*]] = alloca i32, align 4
2855 // CHECK5-NEXT:    [[_TMP18:%.*]] = alloca i32, align 4
2856 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4
2857 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4
2858 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4
2859 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2860 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2861 // CHECK5-NEXT:    [[I27:%.*]] = alloca i32, align 4
2862 // CHECK5-NEXT:    [[DOTOMP_IV30:%.*]] = alloca i32, align 4
2863 // CHECK5-NEXT:    [[I31:%.*]] = alloca i32, align 4
2864 // CHECK5-NEXT:    store i32 [[LOW]], ptr [[LOW_ADDR]], align 4
2865 // CHECK5-NEXT:    store i32 [[UP]], ptr [[UP_ADDR]], align 4
2866 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
2867 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
2868 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[UP_ADDR]], align 4
2869 // CHECK5-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4
2870 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2871 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2872 // CHECK5-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
2873 // CHECK5-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
2874 // CHECK5-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
2875 // CHECK5-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
2876 // CHECK5-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
2877 // CHECK5-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
2878 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2879 // CHECK5-NEXT:    store i32 [[TMP4]], ptr [[I]], align 4
2880 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2881 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2882 // CHECK5-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]]
2883 // CHECK5-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
2884 // CHECK5:       simd.if.then:
2885 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IV]], align 4
2886 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2887 // CHECK5:       omp.inner.for.cond:
2888 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]
2889 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP9]]
2890 // CHECK5-NEXT:    [[ADD6:%.*]] = add i32 [[TMP8]], 1
2891 // CHECK5-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]]
2892 // CHECK5-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2893 // CHECK5:       omp.inner.for.body:
2894 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP9]]
2895 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
2896 // CHECK5-NEXT:    [[MUL:%.*]] = mul i32 [[TMP10]], 1
2897 // CHECK5-NEXT:    [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]]
2898 // CHECK5-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP9]]
2899 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP9]]
2900 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
2901 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
2902 // CHECK5-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]]
2903 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP9]]
2904 // CHECK5-NEXT:    [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64
2905 // CHECK5-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM9]]
2906 // CHECK5-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP9]]
2907 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2908 // CHECK5:       omp.body.continue:
2909 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2910 // CHECK5:       omp.inner.for.inc:
2911 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
2912 // CHECK5-NEXT:    [[ADD11:%.*]] = add i32 [[TMP13]], 1
2913 // CHECK5-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
2914 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
2915 // CHECK5:       omp.inner.for.end:
2916 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2917 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2918 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2919 // CHECK5-NEXT:    [[SUB12:%.*]] = sub i32 [[TMP15]], [[TMP16]]
2920 // CHECK5-NEXT:    [[SUB13:%.*]] = sub i32 [[SUB12]], 1
2921 // CHECK5-NEXT:    [[ADD14:%.*]] = add i32 [[SUB13]], 1
2922 // CHECK5-NEXT:    [[DIV15:%.*]] = udiv i32 [[ADD14]], 1
2923 // CHECK5-NEXT:    [[MUL16:%.*]] = mul i32 [[DIV15]], 1
2924 // CHECK5-NEXT:    [[ADD17:%.*]] = add i32 [[TMP14]], [[MUL16]]
2925 // CHECK5-NEXT:    store i32 [[ADD17]], ptr [[I5]], align 4
2926 // CHECK5-NEXT:    br label [[SIMD_IF_END]]
2927 // CHECK5:       simd.if.end:
2928 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
2929 // CHECK5-NEXT:    store i32 [[TMP17]], ptr [[DOTCAPTURE_EXPR_19]], align 4
2930 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, ptr [[UP_ADDR]], align 4
2931 // CHECK5-NEXT:    store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR_20]], align 4
2932 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
2933 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
2934 // CHECK5-NEXT:    [[SUB22:%.*]] = sub i32 [[TMP19]], [[TMP20]]
2935 // CHECK5-NEXT:    [[SUB23:%.*]] = sub i32 [[SUB22]], 1
2936 // CHECK5-NEXT:    [[ADD24:%.*]] = add i32 [[SUB23]], 1
2937 // CHECK5-NEXT:    [[DIV25:%.*]] = udiv i32 [[ADD24]], 1
2938 // CHECK5-NEXT:    [[SUB26:%.*]] = sub i32 [[DIV25]], 1
2939 // CHECK5-NEXT:    store i32 [[SUB26]], ptr [[DOTCAPTURE_EXPR_21]], align 4
2940 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2941 // CHECK5-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_21]], align 4
2942 // CHECK5-NEXT:    store i32 [[TMP21]], ptr [[DOTOMP_UB]], align 4
2943 // CHECK5-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
2944 // CHECK5-NEXT:    store i32 [[TMP22]], ptr [[I27]], align 4
2945 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
2946 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
2947 // CHECK5-NEXT:    [[CMP28:%.*]] = icmp slt i32 [[TMP23]], [[TMP24]]
2948 // CHECK5-NEXT:    br i1 [[CMP28]], label [[SIMD_IF_THEN29:%.*]], label [[SIMD_IF_END52:%.*]]
2949 // CHECK5:       simd.if.then29:
2950 // CHECK5-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2951 // CHECK5-NEXT:    store i32 [[TMP25]], ptr [[DOTOMP_IV30]], align 4
2952 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND32:%.*]]
2953 // CHECK5:       omp.inner.for.cond32:
2954 // CHECK5-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV30]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]
2955 // CHECK5-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]]
2956 // CHECK5-NEXT:    [[ADD33:%.*]] = add i32 [[TMP27]], 1
2957 // CHECK5-NEXT:    [[CMP34:%.*]] = icmp ult i32 [[TMP26]], [[ADD33]]
2958 // CHECK5-NEXT:    br i1 [[CMP34]], label [[OMP_INNER_FOR_BODY35:%.*]], label [[OMP_INNER_FOR_END45:%.*]]
2959 // CHECK5:       omp.inner.for.body35:
2960 // CHECK5-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4, !llvm.access.group [[ACC_GRP13]]
2961 // CHECK5-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV30]], align 4, !llvm.access.group [[ACC_GRP13]]
2962 // CHECK5-NEXT:    [[MUL36:%.*]] = mul i32 [[TMP29]], 1
2963 // CHECK5-NEXT:    [[ADD37:%.*]] = add i32 [[TMP28]], [[MUL36]]
2964 // CHECK5-NEXT:    store i32 [[ADD37]], ptr [[I31]], align 4, !llvm.access.group [[ACC_GRP13]]
2965 // CHECK5-NEXT:    [[TMP30:%.*]] = load i32, ptr [[I31]], align 4, !llvm.access.group [[ACC_GRP13]]
2966 // CHECK5-NEXT:    [[IDXPROM38:%.*]] = sext i32 [[TMP30]] to i64
2967 // CHECK5-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM38]]
2968 // CHECK5-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX39]], align 4, !llvm.access.group [[ACC_GRP13]]
2969 // CHECK5-NEXT:    [[TMP31:%.*]] = load i32, ptr [[I31]], align 4, !llvm.access.group [[ACC_GRP13]]
2970 // CHECK5-NEXT:    [[IDXPROM40:%.*]] = sext i32 [[TMP31]] to i64
2971 // CHECK5-NEXT:    [[ARRAYIDX41:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM40]]
2972 // CHECK5-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX41]], align 4, !llvm.access.group [[ACC_GRP13]]
2973 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE42:%.*]]
2974 // CHECK5:       omp.body.continue42:
2975 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC43:%.*]]
2976 // CHECK5:       omp.inner.for.inc43:
2977 // CHECK5-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV30]], align 4, !llvm.access.group [[ACC_GRP13]]
2978 // CHECK5-NEXT:    [[ADD44:%.*]] = add i32 [[TMP32]], 1
2979 // CHECK5-NEXT:    store i32 [[ADD44]], ptr [[DOTOMP_IV30]], align 4, !llvm.access.group [[ACC_GRP13]]
2980 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND32]], !llvm.loop [[LOOP14:![0-9]+]]
2981 // CHECK5:       omp.inner.for.end45:
2982 // CHECK5-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
2983 // CHECK5-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
2984 // CHECK5-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
2985 // CHECK5-NEXT:    [[SUB46:%.*]] = sub i32 [[TMP34]], [[TMP35]]
2986 // CHECK5-NEXT:    [[SUB47:%.*]] = sub i32 [[SUB46]], 1
2987 // CHECK5-NEXT:    [[ADD48:%.*]] = add i32 [[SUB47]], 1
2988 // CHECK5-NEXT:    [[DIV49:%.*]] = udiv i32 [[ADD48]], 1
2989 // CHECK5-NEXT:    [[MUL50:%.*]] = mul i32 [[DIV49]], 1
2990 // CHECK5-NEXT:    [[ADD51:%.*]] = add i32 [[TMP33]], [[MUL50]]
2991 // CHECK5-NEXT:    store i32 [[ADD51]], ptr [[I31]], align 4
2992 // CHECK5-NEXT:    br label [[SIMD_IF_END52]]
2993 // CHECK5:       simd.if.end52:
2994 // CHECK5-NEXT:    ret void
2995 //