clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
   3 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
   4 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
   5 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
   6 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
   7 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
   8
   9 // RUN: %clang_cc1  -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
  10 // RUN: %clang_cc1  -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  11 // RUN: %clang_cc1  -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5
  12 // RUN: %clang_cc1  -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7
  13 // RUN: %clang_cc1  -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  14 // RUN: %clang_cc1  -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7
  15
  16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  17 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  18 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  19 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  20 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  22
  23 // RUN: %clang_cc1  -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  24 // RUN: %clang_cc1  -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  25 // RUN: %clang_cc1  -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  26 // RUN: %clang_cc1  -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  27 // RUN: %clang_cc1  -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  28 // RUN: %clang_cc1  -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  29
  30 // expected-no-diagnostics
  31 #ifndef HEADER
  32 #define HEADER
  33
  34 template <class T>
  35 struct S {
  36   T f;
  37   S(T a) : f(a) {}
  38   S() : f() {}
  39   operator T() { return T(); }
  40   ~S() {}
  41 };
  42
  43 template <typename T>
  44 T tmain() {
  45   S<T> test;
  46   T t_var = T();
  47   T vec[] = {1, 2};
  48   S<T> s_arr[] = {1, 2};
  49   S<T> &var = test;
  50   #pragma omp target teams distribute parallel for lastprivate(t_var, vec, s_arr, s_arr, var, var)
  51   for (int i = 0; i < 2; ++i) {
  52     vec[i] = t_var;
  53     s_arr[i] = var;
  54   }
  55   return T();
  56 }
  57
  58 int main() {
  59   static int svar;
  60   volatile double g;
  61   volatile double &g1 = g;
  62
  63   #ifdef LAMBDA
  64   [&]() {
  65     static float sfvar;
  66
  67     #pragma omp target teams distribute parallel for lastprivate(g, g1, svar, sfvar)
  68     for (int i = 0; i < 2; ++i) {
  69       // skip gbl and bound tid
  70       // loop variables
  71
  72
  73
  74       g1 = 1;
  75       svar = 3;
  76       sfvar = 4.0;
  77
  78
  79
  80       // skip tid and prev variables
  81       // loop variables
  82
  83
  84
  85
  86
  87
  88
  89       [&]() {
  90         g = 2;
  91         g1 = 2;
  92         svar = 4;
  93         sfvar = 8.0;
  94
  95       }();
  96     }
  97   }();
  98   return 0;
  99   #else
 100   S<float> test;
 101   int t_var = 0;
 102   int vec[] = {1, 2};
 103   S<float> s_arr[] = {1, 2};
 104   S<float> &var = test;
 105
 106   #pragma omp target teams distribute parallel for lastprivate(t_var, vec, s_arr, s_arr, var, var, svar)
 107   for (int i = 0; i < 2; ++i) {
 108     vec[i] = t_var;
 109     s_arr[i] = var;
 110   }
 111   int i;
 112
 113   return tmain<int>();
 114   #endif
 115 }
 116
 117
 118 // skip loop variables
 119
 120 // copy from parameters to local address variables
 121
 122 // prepare lastprivate targets
 123
 124 // the distribute loop
 125
 126 // lastprivates
 127
 128
 129
 130 // gbl and bound tid vars, prev lb and ub vars
 131
 132 // skip loop variables
 133
 134 // copy from parameters to local address variables
 135
 136 // prepare lastprivate targets
 137
 138 // the distribute loop
 139 // skip body: code generation routine is same as distribute parallel for lastprivate
 140
 141 // lastprivates
 142
 143
 144 // template tmain
 145
 146
 147 // skip alloca of global_tid and bound_tid
 148 // skip loop variables
 149
 150 // copy from parameters to local address variables
 151
 152 // prepare lastprivate targets
 153
 154
 155 // lastprivates
 156
 157
 158 // skip alloca of global_tid and bound_tid, and prev lb and ub vars
 159
 160 // skip loop variables
 161
 162 // copy from parameters to local address variables
 163
 164 // prepare lastprivate targets
 165
 166 // skip body: code generation routine is same as distribute parallel for lastprivate
 167
 168 // lastprivates
 169
 170
 171 #endif
 172 // CHECK1-LABEL: define {{[^@]+}}@main
 173 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
 174 // CHECK1-NEXT:  entry:
 175 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 176 // CHECK1-NEXT:    [[G:%.*]] = alloca double, align 8
 177 // CHECK1-NEXT:    [[G1:%.*]] = alloca ptr, align 8
 178 // CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
 179 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 180 // CHECK1-NEXT:    store ptr [[G]], ptr [[G1]], align 8
 181 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
 182 // CHECK1-NEXT:    store ptr [[G]], ptr [[TMP0]], align 8
 183 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1
 184 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8
 185 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP1]], align 8
 186 // CHECK1-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])
 187 // CHECK1-NEXT:    ret i32 0
 188 //
 189 //
 190 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67
 191 // CHECK1-SAME: (i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2:[0-9]+]] {
 192 // CHECK1-NEXT:  entry:
 193 // CHECK1-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8
 194 // CHECK1-NEXT:    [[SVAR_ADDR:%.*]] = alloca i64, align 8
 195 // CHECK1-NEXT:    [[SFVAR_ADDR:%.*]] = alloca i64, align 8
 196 // CHECK1-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8
 197 // CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 198 // CHECK1-NEXT:    [[G1_CASTED:%.*]] = alloca i64, align 8
 199 // CHECK1-NEXT:    [[SVAR_CASTED:%.*]] = alloca i64, align 8
 200 // CHECK1-NEXT:    [[SFVAR_CASTED:%.*]] = alloca i64, align 8
 201 // CHECK1-NEXT:    [[G_CASTED:%.*]] = alloca i64, align 8
 202 // CHECK1-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 8
 203 // CHECK1-NEXT:    store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
 204 // CHECK1-NEXT:    store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8
 205 // CHECK1-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 8
 206 // CHECK1-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 8
 207 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
 208 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile double, ptr [[TMP0]], align 8
 209 // CHECK1-NEXT:    store double [[TMP1]], ptr [[G1_CASTED]], align 8
 210 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[G1_CASTED]], align 8
 211 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4
 212 // CHECK1-NEXT:    store i32 [[TMP3]], ptr [[SVAR_CASTED]], align 4
 213 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8
 214 // CHECK1-NEXT:    [[TMP5:%.*]] = load float, ptr [[SFVAR_ADDR]], align 4
 215 // CHECK1-NEXT:    store float [[TMP5]], ptr [[SFVAR_CASTED]], align 4
 216 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[SFVAR_CASTED]], align 8
 217 // CHECK1-NEXT:    [[TMP7:%.*]] = load double, ptr [[G_ADDR]], align 8
 218 // CHECK1-NEXT:    store double [[TMP7]], ptr [[G_CASTED]], align 8
 219 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, ptr [[G_CASTED]], align 8
 220 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]])
 221 // CHECK1-NEXT:    ret void
 222 //
 223 //
 224 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined
 225 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2]] {
 226 // CHECK1-NEXT:  entry:
 227 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 228 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 229 // CHECK1-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8
 230 // CHECK1-NEXT:    [[SVAR_ADDR:%.*]] = alloca i64, align 8
 231 // CHECK1-NEXT:    [[SFVAR_ADDR:%.*]] = alloca i64, align 8
 232 // CHECK1-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8
 233 // CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 234 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 235 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 236 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 237 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 238 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 239 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 240 // CHECK1-NEXT:    [[G2:%.*]] = alloca double, align 8
 241 // CHECK1-NEXT:    [[G13:%.*]] = alloca double, align 8
 242 // CHECK1-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 8
 243 // CHECK1-NEXT:    [[SVAR5:%.*]] = alloca i32, align 4
 244 // CHECK1-NEXT:    [[SFVAR6:%.*]] = alloca float, align 4
 245 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 246 // CHECK1-NEXT:    [[G1_CASTED:%.*]] = alloca i64, align 8
 247 // CHECK1-NEXT:    [[SVAR_CASTED:%.*]] = alloca i64, align 8
 248 // CHECK1-NEXT:    [[SFVAR_CASTED:%.*]] = alloca i64, align 8
 249 // CHECK1-NEXT:    [[G_CASTED:%.*]] = alloca i64, align 8
 250 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 251 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 252 // CHECK1-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 8
 253 // CHECK1-NEXT:    store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
 254 // CHECK1-NEXT:    store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8
 255 // CHECK1-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 8
 256 // CHECK1-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 8
 257 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 258 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
 259 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 260 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 261 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
 262 // CHECK1-NEXT:    store ptr [[G13]], ptr [[_TMP4]], align 8
 263 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 264 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 265 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 266 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 267 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
 268 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 269 // CHECK1:       cond.true:
 270 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 271 // CHECK1:       cond.false:
 272 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 273 // CHECK1-NEXT:    br label [[COND_END]]
 274 // CHECK1:       cond.end:
 275 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
 276 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 277 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 278 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
 279 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 280 // CHECK1:       omp.inner.for.cond:
 281 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 282 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 283 // CHECK1-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
 284 // CHECK1-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 285 // CHECK1:       omp.inner.for.body:
 286 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 287 // CHECK1-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
 288 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 289 // CHECK1-NEXT:    [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
 290 // CHECK1-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8
 291 // CHECK1-NEXT:    [[TMP13:%.*]] = load volatile double, ptr [[TMP12]], align 8
 292 // CHECK1-NEXT:    store double [[TMP13]], ptr [[G1_CASTED]], align 8
 293 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[G1_CASTED]], align 8
 294 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[SVAR5]], align 4
 295 // CHECK1-NEXT:    store i32 [[TMP15]], ptr [[SVAR_CASTED]], align 4
 296 // CHECK1-NEXT:    [[TMP16:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8
 297 // CHECK1-NEXT:    [[TMP17:%.*]] = load float, ptr [[SFVAR6]], align 4
 298 // CHECK1-NEXT:    store float [[TMP17]], ptr [[SFVAR_CASTED]], align 4
 299 // CHECK1-NEXT:    [[TMP18:%.*]] = load i64, ptr [[SFVAR_CASTED]], align 8
 300 // CHECK1-NEXT:    [[TMP19:%.*]] = load double, ptr [[G2]], align 8
 301 // CHECK1-NEXT:    store double [[TMP19]], ptr [[G_CASTED]], align 8
 302 // CHECK1-NEXT:    [[TMP20:%.*]] = load i64, ptr [[G_CASTED]], align 8
 303 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]])
 304 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 305 // CHECK1:       omp.inner.for.inc:
 306 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 307 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 308 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
 309 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
 310 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 311 // CHECK1:       omp.inner.for.end:
 312 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 313 // CHECK1:       omp.loop.exit:
 314 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
 315 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 316 // CHECK1-NEXT:    [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
 317 // CHECK1-NEXT:    br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
 318 // CHECK1:       .omp.lastprivate.then:
 319 // CHECK1-NEXT:    [[TMP25:%.*]] = load double, ptr [[G2]], align 8
 320 // CHECK1-NEXT:    store volatile double [[TMP25]], ptr [[G_ADDR]], align 8
 321 // CHECK1-NEXT:    [[TMP26:%.*]] = load ptr, ptr [[_TMP4]], align 8
 322 // CHECK1-NEXT:    [[TMP27:%.*]] = load double, ptr [[TMP26]], align 8
 323 // CHECK1-NEXT:    store volatile double [[TMP27]], ptr [[TMP0]], align 8
 324 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[SVAR5]], align 4
 325 // CHECK1-NEXT:    store i32 [[TMP28]], ptr [[SVAR_ADDR]], align 4
 326 // CHECK1-NEXT:    [[TMP29:%.*]] = load float, ptr [[SFVAR6]], align 4
 327 // CHECK1-NEXT:    store float [[TMP29]], ptr [[SFVAR_ADDR]], align 4
 328 // CHECK1-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
 329 // CHECK1:       .omp.lastprivate.done:
 330 // CHECK1-NEXT:    ret void
 331 //
 332 //
 333 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined
 334 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2]] {
 335 // CHECK1-NEXT:  entry:
 336 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 337 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 338 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
 339 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
 340 // CHECK1-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8
 341 // CHECK1-NEXT:    [[SVAR_ADDR:%.*]] = alloca i64, align 8
 342 // CHECK1-NEXT:    [[SFVAR_ADDR:%.*]] = alloca i64, align 8
 343 // CHECK1-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8
 344 // CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 345 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 346 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 347 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 348 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 349 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 350 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 351 // CHECK1-NEXT:    [[G3:%.*]] = alloca double, align 8
 352 // CHECK1-NEXT:    [[G14:%.*]] = alloca double, align 8
 353 // CHECK1-NEXT:    [[_TMP5:%.*]] = alloca ptr, align 8
 354 // CHECK1-NEXT:    [[SVAR6:%.*]] = alloca i32, align 4
 355 // CHECK1-NEXT:    [[SFVAR7:%.*]] = alloca float, align 4
 356 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 357 // CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
 358 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 359 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 360 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 361 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 362 // CHECK1-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 8
 363 // CHECK1-NEXT:    store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
 364 // CHECK1-NEXT:    store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8
 365 // CHECK1-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 8
 366 // CHECK1-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 8
 367 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 368 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 369 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 370 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
 371 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 372 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
 373 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
 374 // CHECK1-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
 375 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 376 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 377 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8
 378 // CHECK1-NEXT:    store ptr [[G14]], ptr [[_TMP5]], align 8
 379 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 380 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
 381 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 382 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 383 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
 384 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 385 // CHECK1:       cond.true:
 386 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 387 // CHECK1:       cond.false:
 388 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 389 // CHECK1-NEXT:    br label [[COND_END]]
 390 // CHECK1:       cond.end:
 391 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
 392 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 393 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 394 // CHECK1-NEXT:    store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
 395 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 396 // CHECK1:       omp.inner.for.cond:
 397 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 398 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 399 // CHECK1-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
 400 // CHECK1-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 401 // CHECK1:       omp.inner.for.body:
 402 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 403 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
 404 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 405 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
 406 // CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[_TMP5]], align 8
 407 // CHECK1-NEXT:    store volatile double 1.000000e+00, ptr [[TMP11]], align 8
 408 // CHECK1-NEXT:    store i32 3, ptr [[SVAR6]], align 4
 409 // CHECK1-NEXT:    store float 4.000000e+00, ptr [[SFVAR7]], align 4
 410 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
 411 // CHECK1-NEXT:    store ptr [[G3]], ptr [[TMP12]], align 8
 412 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
 413 // CHECK1-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[_TMP5]], align 8
 414 // CHECK1-NEXT:    store ptr [[TMP14]], ptr [[TMP13]], align 8
 415 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
 416 // CHECK1-NEXT:    store ptr [[SVAR6]], ptr [[TMP15]], align 8
 417 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3
 418 // CHECK1-NEXT:    store ptr [[SFVAR7]], ptr [[TMP16]], align 8
 419 // CHECK1-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]])
 420 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 421 // CHECK1:       omp.body.continue:
 422 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 423 // CHECK1:       omp.inner.for.inc:
 424 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 425 // CHECK1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP17]], 1
 426 // CHECK1-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
 427 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 428 // CHECK1:       omp.inner.for.end:
 429 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 430 // CHECK1:       omp.loop.exit:
 431 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]])
 432 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 433 // CHECK1-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
 434 // CHECK1-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
 435 // CHECK1:       .omp.lastprivate.then:
 436 // CHECK1-NEXT:    [[TMP20:%.*]] = load double, ptr [[G3]], align 8
 437 // CHECK1-NEXT:    store volatile double [[TMP20]], ptr [[G_ADDR]], align 8
 438 // CHECK1-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[_TMP5]], align 8
 439 // CHECK1-NEXT:    [[TMP22:%.*]] = load double, ptr [[TMP21]], align 8
 440 // CHECK1-NEXT:    store volatile double [[TMP22]], ptr [[TMP2]], align 8
 441 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[SVAR6]], align 4
 442 // CHECK1-NEXT:    store i32 [[TMP23]], ptr [[SVAR_ADDR]], align 4
 443 // CHECK1-NEXT:    [[TMP24:%.*]] = load float, ptr [[SFVAR7]], align 4
 444 // CHECK1-NEXT:    store float [[TMP24]], ptr [[SFVAR_ADDR]], align 4
 445 // CHECK1-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
 446 // CHECK1:       .omp.lastprivate.done:
 447 // CHECK1-NEXT:    ret void
 448 //
 449 //
 450 // CHECK3-LABEL: define {{[^@]+}}@main
 451 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
 452 // CHECK3-NEXT:  entry:
 453 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 454 // CHECK3-NEXT:    [[G:%.*]] = alloca double, align 8
 455 // CHECK3-NEXT:    [[G1:%.*]] = alloca ptr, align 4
 456 // CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4
 457 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 458 // CHECK3-NEXT:    store ptr [[G]], ptr [[G1]], align 4
 459 // CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
 460 // CHECK3-NEXT:    store ptr [[G]], ptr [[TMP0]], align 4
 461 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1
 462 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4
 463 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP1]], align 4
 464 // CHECK3-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]])
 465 // CHECK3-NEXT:    ret i32 0
 466 //
 467 //
 468 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67
 469 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2:[0-9]+]] {
 470 // CHECK3-NEXT:  entry:
 471 // CHECK3-NEXT:    [[G1_ADDR:%.*]] = alloca ptr, align 4
 472 // CHECK3-NEXT:    [[SVAR_ADDR:%.*]] = alloca i32, align 4
 473 // CHECK3-NEXT:    [[SFVAR_ADDR:%.*]] = alloca i32, align 4
 474 // CHECK3-NEXT:    [[G_ADDR:%.*]] = alloca ptr, align 4
 475 // CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
 476 // CHECK3-NEXT:    [[SVAR_CASTED:%.*]] = alloca i32, align 4
 477 // CHECK3-NEXT:    [[SFVAR_CASTED:%.*]] = alloca i32, align 4
 478 // CHECK3-NEXT:    store ptr [[G1]], ptr [[G1_ADDR]], align 4
 479 // CHECK3-NEXT:    store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
 480 // CHECK3-NEXT:    store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4
 481 // CHECK3-NEXT:    store ptr [[G]], ptr [[G_ADDR]], align 4
 482 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[G1_ADDR]], align 4
 483 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[G_ADDR]], align 4
 484 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 4
 485 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4
 486 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4
 487 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[SVAR_CASTED]], align 4
 488 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4
 489 // CHECK3-NEXT:    [[TMP5:%.*]] = load float, ptr [[SFVAR_ADDR]], align 4
 490 // CHECK3-NEXT:    store float [[TMP5]], ptr [[SFVAR_CASTED]], align 4
 491 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[SFVAR_CASTED]], align 4
 492 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, ptr [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP1]])
 493 // CHECK3-NEXT:    ret void
 494 //
 495 //
 496 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined
 497 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] {
 498 // CHECK3-NEXT:  entry:
 499 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
 500 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
 501 // CHECK3-NEXT:    [[G1_ADDR:%.*]] = alloca ptr, align 4
 502 // CHECK3-NEXT:    [[SVAR_ADDR:%.*]] = alloca i32, align 4
 503 // CHECK3-NEXT:    [[SFVAR_ADDR:%.*]] = alloca i32, align 4
 504 // CHECK3-NEXT:    [[G_ADDR:%.*]] = alloca ptr, align 4
 505 // CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
 506 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 507 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 508 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 509 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 510 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 511 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 512 // CHECK3-NEXT:    [[G2:%.*]] = alloca double, align 8
 513 // CHECK3-NEXT:    [[G13:%.*]] = alloca double, align 8
 514 // CHECK3-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 4
 515 // CHECK3-NEXT:    [[SVAR5:%.*]] = alloca i32, align 4
 516 // CHECK3-NEXT:    [[SFVAR6:%.*]] = alloca float, align 4
 517 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
 518 // CHECK3-NEXT:    [[SVAR_CASTED:%.*]] = alloca i32, align 4
 519 // CHECK3-NEXT:    [[SFVAR_CASTED:%.*]] = alloca i32, align 4
 520 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
 521 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
 522 // CHECK3-NEXT:    store ptr [[G1]], ptr [[G1_ADDR]], align 4
 523 // CHECK3-NEXT:    store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
 524 // CHECK3-NEXT:    store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4
 525 // CHECK3-NEXT:    store ptr [[G]], ptr [[G_ADDR]], align 4
 526 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[G1_ADDR]], align 4
 527 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[G_ADDR]], align 4
 528 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 4
 529 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 530 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
 531 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 532 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 533 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4
 534 // CHECK3-NEXT:    store ptr [[G13]], ptr [[_TMP4]], align 4
 535 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
 536 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
 537 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 538 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 539 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
 540 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 541 // CHECK3:       cond.true:
 542 // CHECK3-NEXT:    br label [[COND_END:%.*]]
 543 // CHECK3:       cond.false:
 544 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 545 // CHECK3-NEXT:    br label [[COND_END]]
 546 // CHECK3:       cond.end:
 547 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
 548 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 549 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 550 // CHECK3-NEXT:    store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
 551 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 552 // CHECK3:       omp.inner.for.cond:
 553 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 554 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 555 // CHECK3-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
 556 // CHECK3-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 557 // CHECK3:       omp.inner.for.body:
 558 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 559 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 560 // CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 4
 561 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[SVAR5]], align 4
 562 // CHECK3-NEXT:    store i32 [[TMP13]], ptr [[SVAR_CASTED]], align 4
 563 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4
 564 // CHECK3-NEXT:    [[TMP15:%.*]] = load float, ptr [[SFVAR6]], align 4
 565 // CHECK3-NEXT:    store float [[TMP15]], ptr [[SFVAR_CASTED]], align 4
 566 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[SFVAR_CASTED]], align 4
 567 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined, i32 [[TMP10]], i32 [[TMP11]], ptr [[TMP12]], i32 [[TMP14]], i32 [[TMP16]], ptr [[G2]])
 568 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 569 // CHECK3:       omp.inner.for.inc:
 570 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 571 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 572 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
 573 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
 574 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
 575 // CHECK3:       omp.inner.for.end:
 576 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 577 // CHECK3:       omp.loop.exit:
 578 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]])
 579 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 580 // CHECK3-NEXT:    [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
 581 // CHECK3-NEXT:    br i1 [[TMP20]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
 582 // CHECK3:       .omp.lastprivate.then:
 583 // CHECK3-NEXT:    [[TMP21:%.*]] = load double, ptr [[G2]], align 8
 584 // CHECK3-NEXT:    store volatile double [[TMP21]], ptr [[TMP1]], align 8
 585 // CHECK3-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[_TMP4]], align 4
 586 // CHECK3-NEXT:    [[TMP23:%.*]] = load double, ptr [[TMP22]], align 4
 587 // CHECK3-NEXT:    store volatile double [[TMP23]], ptr [[TMP2]], align 4
 588 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, ptr [[SVAR5]], align 4
 589 // CHECK3-NEXT:    store i32 [[TMP24]], ptr [[SVAR_ADDR]], align 4
 590 // CHECK3-NEXT:    [[TMP25:%.*]] = load float, ptr [[SFVAR6]], align 4
 591 // CHECK3-NEXT:    store float [[TMP25]], ptr [[SFVAR_ADDR]], align 4
 592 // CHECK3-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
 593 // CHECK3:       .omp.lastprivate.done:
 594 // CHECK3-NEXT:    ret void
 595 //
 596 //
 597 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined
 598 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] {
 599 // CHECK3-NEXT:  entry:
 600 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
 601 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
 602 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
 603 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
 604 // CHECK3-NEXT:    [[G1_ADDR:%.*]] = alloca ptr, align 4
 605 // CHECK3-NEXT:    [[SVAR_ADDR:%.*]] = alloca i32, align 4
 606 // CHECK3-NEXT:    [[SFVAR_ADDR:%.*]] = alloca i32, align 4
 607 // CHECK3-NEXT:    [[G_ADDR:%.*]] = alloca ptr, align 4
 608 // CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
 609 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 610 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 611 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 612 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 613 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 614 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 615 // CHECK3-NEXT:    [[G2:%.*]] = alloca double, align 8
 616 // CHECK3-NEXT:    [[G13:%.*]] = alloca double, align 8
 617 // CHECK3-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 4
 618 // CHECK3-NEXT:    [[SVAR5:%.*]] = alloca i32, align 4
 619 // CHECK3-NEXT:    [[SFVAR6:%.*]] = alloca float, align 4
 620 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
 621 // CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4
 622 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
 623 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
 624 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
 625 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
 626 // CHECK3-NEXT:    store ptr [[G1]], ptr [[G1_ADDR]], align 4
 627 // CHECK3-NEXT:    store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
 628 // CHECK3-NEXT:    store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4
 629 // CHECK3-NEXT:    store ptr [[G]], ptr [[G_ADDR]], align 4
 630 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[G1_ADDR]], align 4
 631 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[G_ADDR]], align 4
 632 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 4
 633 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 634 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 635 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
 636 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
 637 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_LB]], align 4
 638 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[DOTOMP_UB]], align 4
 639 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 640 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 641 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4
 642 // CHECK3-NEXT:    store ptr [[G13]], ptr [[_TMP4]], align 4
 643 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
 644 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
 645 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 646 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 647 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1
 648 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 649 // CHECK3:       cond.true:
 650 // CHECK3-NEXT:    br label [[COND_END:%.*]]
 651 // CHECK3:       cond.false:
 652 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 653 // CHECK3-NEXT:    br label [[COND_END]]
 654 // CHECK3:       cond.end:
 655 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
 656 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 657 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 658 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
 659 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 660 // CHECK3:       omp.inner.for.cond:
 661 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 662 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 663 // CHECK3-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
 664 // CHECK3-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 665 // CHECK3:       omp.inner.for.body:
 666 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 667 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
 668 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 669 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
 670 // CHECK3-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[_TMP4]], align 4
 671 // CHECK3-NEXT:    store volatile double 1.000000e+00, ptr [[TMP13]], align 4
 672 // CHECK3-NEXT:    store i32 3, ptr [[SVAR5]], align 4
 673 // CHECK3-NEXT:    store float 4.000000e+00, ptr [[SFVAR6]], align 4
 674 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
 675 // CHECK3-NEXT:    store ptr [[G2]], ptr [[TMP14]], align 4
 676 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
 677 // CHECK3-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[_TMP4]], align 4
 678 // CHECK3-NEXT:    store ptr [[TMP16]], ptr [[TMP15]], align 4
 679 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
 680 // CHECK3-NEXT:    store ptr [[SVAR5]], ptr [[TMP17]], align 4
 681 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3
 682 // CHECK3-NEXT:    store ptr [[SFVAR6]], ptr [[TMP18]], align 4
 683 // CHECK3-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 4 dereferenceable(16) [[REF_TMP]])
 684 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 685 // CHECK3:       omp.body.continue:
 686 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 687 // CHECK3:       omp.inner.for.inc:
 688 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 689 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
 690 // CHECK3-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4
 691 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
 692 // CHECK3:       omp.inner.for.end:
 693 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 694 // CHECK3:       omp.loop.exit:
 695 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP6]])
 696 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 697 // CHECK3-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
 698 // CHECK3-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
 699 // CHECK3:       .omp.lastprivate.then:
 700 // CHECK3-NEXT:    [[TMP22:%.*]] = load double, ptr [[G2]], align 8
 701 // CHECK3-NEXT:    store volatile double [[TMP22]], ptr [[TMP1]], align 8
 702 // CHECK3-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[_TMP4]], align 4
 703 // CHECK3-NEXT:    [[TMP24:%.*]] = load double, ptr [[TMP23]], align 4
 704 // CHECK3-NEXT:    store volatile double [[TMP24]], ptr [[TMP4]], align 4
 705 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, ptr [[SVAR5]], align 4
 706 // CHECK3-NEXT:    store i32 [[TMP25]], ptr [[SVAR_ADDR]], align 4
 707 // CHECK3-NEXT:    [[TMP26:%.*]] = load float, ptr [[SFVAR6]], align 4
 708 // CHECK3-NEXT:    store float [[TMP26]], ptr [[SFVAR_ADDR]], align 4
 709 // CHECK3-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
 710 // CHECK3:       .omp.lastprivate.done:
 711 // CHECK3-NEXT:    ret void
 712 //
 713 //
 714 // CHECK5-LABEL: define {{[^@]+}}@main
 715 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
 716 // CHECK5-NEXT:  entry:
 717 // CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 718 // CHECK5-NEXT:    [[G:%.*]] = alloca double, align 8
 719 // CHECK5-NEXT:    [[G1:%.*]] = alloca ptr, align 8
 720 // CHECK5-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 721 // CHECK5-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 722 // CHECK5-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 723 // CHECK5-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
 724 // CHECK5-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
 725 // CHECK5-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 726 // CHECK5-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
 727 // CHECK5-NEXT:    [[SVAR_CASTED:%.*]] = alloca i64, align 8
 728 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
 729 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
 730 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
 731 // CHECK5-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 732 // CHECK5-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 733 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
 734 // CHECK5-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 735 // CHECK5-NEXT:    store ptr [[G]], ptr [[G1]], align 8
 736 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 737 // CHECK5-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 738 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)
 739 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)
 740 // CHECK5-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1
 741 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
 742 // CHECK5-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
 743 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
 744 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 8
 745 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
 746 // CHECK5-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
 747 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
 748 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
 749 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4
 750 // CHECK5-NEXT:    store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4
 751 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8
 752 // CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 753 // CHECK5-NEXT:    store ptr [[VEC]], ptr [[TMP6]], align 8
 754 // CHECK5-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 755 // CHECK5-NEXT:    store ptr [[VEC]], ptr [[TMP7]], align 8
 756 // CHECK5-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 757 // CHECK5-NEXT:    store ptr null, ptr [[TMP8]], align 8
 758 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 759 // CHECK5-NEXT:    store i64 [[TMP2]], ptr [[TMP9]], align 8
 760 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 761 // CHECK5-NEXT:    store i64 [[TMP2]], ptr [[TMP10]], align 8
 762 // CHECK5-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 763 // CHECK5-NEXT:    store ptr null, ptr [[TMP11]], align 8
 764 // CHECK5-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
 765 // CHECK5-NEXT:    store ptr [[S_ARR]], ptr [[TMP12]], align 8
 766 // CHECK5-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
 767 // CHECK5-NEXT:    store ptr [[S_ARR]], ptr [[TMP13]], align 8
 768 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
 769 // CHECK5-NEXT:    store ptr null, ptr [[TMP14]], align 8
 770 // CHECK5-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
 771 // CHECK5-NEXT:    store ptr [[TMP3]], ptr [[TMP15]], align 8
 772 // CHECK5-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
 773 // CHECK5-NEXT:    store ptr [[TMP3]], ptr [[TMP16]], align 8
 774 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
 775 // CHECK5-NEXT:    store ptr null, ptr [[TMP17]], align 8
 776 // CHECK5-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
 777 // CHECK5-NEXT:    store i64 [[TMP5]], ptr [[TMP18]], align 8
 778 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
 779 // CHECK5-NEXT:    store i64 [[TMP5]], ptr [[TMP19]], align 8
 780 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
 781 // CHECK5-NEXT:    store ptr null, ptr [[TMP20]], align 8
 782 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 783 // CHECK5-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 784 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 785 // CHECK5-NEXT:    store i32 3, ptr [[TMP23]], align 4
 786 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 787 // CHECK5-NEXT:    store i32 5, ptr [[TMP24]], align 4
 788 // CHECK5-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 789 // CHECK5-NEXT:    store ptr [[TMP21]], ptr [[TMP25]], align 8
 790 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 791 // CHECK5-NEXT:    store ptr [[TMP22]], ptr [[TMP26]], align 8
 792 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 793 // CHECK5-NEXT:    store ptr @.offload_sizes, ptr [[TMP27]], align 8
 794 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 795 // CHECK5-NEXT:    store ptr @.offload_maptypes, ptr [[TMP28]], align 8
 796 // CHECK5-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 797 // CHECK5-NEXT:    store ptr null, ptr [[TMP29]], align 8
 798 // CHECK5-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 799 // CHECK5-NEXT:    store ptr null, ptr [[TMP30]], align 8
 800 // CHECK5-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 801 // CHECK5-NEXT:    store i64 2, ptr [[TMP31]], align 8
 802 // CHECK5-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 803 // CHECK5-NEXT:    store i64 0, ptr [[TMP32]], align 8
 804 // CHECK5-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 805 // CHECK5-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP33]], align 4
 806 // CHECK5-NEXT:    [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 807 // CHECK5-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP34]], align 4
 808 // CHECK5-NEXT:    [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 809 // CHECK5-NEXT:    store i32 0, ptr [[TMP35]], align 4
 810 // CHECK5-NEXT:    [[TMP36:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, ptr [[KERNEL_ARGS]])
 811 // CHECK5-NEXT:    [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0
 812 // CHECK5-NEXT:    br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 813 // CHECK5:       omp_offload.failed:
 814 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(ptr [[VEC]], i64 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]], i64 [[TMP5]]) #[[ATTR4:[0-9]+]]
 815 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 816 // CHECK5:       omp_offload.cont:
 817 // CHECK5-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
 818 // CHECK5-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
 819 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 820 // CHECK5-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
 821 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 822 // CHECK5:       arraydestroy.body:
 823 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 824 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 825 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
 826 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
 827 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
 828 // CHECK5:       arraydestroy.done2:
 829 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
 830 // CHECK5-NEXT:    [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4
 831 // CHECK5-NEXT:    ret i32 [[TMP39]]
 832 //
 833 //
 834 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 835 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
 836 // CHECK5-NEXT:  entry:
 837 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 838 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 839 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 840 // CHECK5-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 841 // CHECK5-NEXT:    ret void
 842 //
 843 //
 844 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 845 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 846 // CHECK5-NEXT:  entry:
 847 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 848 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 849 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 850 // CHECK5-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 851 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 852 // CHECK5-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 853 // CHECK5-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 854 // CHECK5-NEXT:    ret void
 855 //
 856 //
 857 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106
 858 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {
 859 // CHECK5-NEXT:  entry:
 860 // CHECK5-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
 861 // CHECK5-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
 862 // CHECK5-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
 863 // CHECK5-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
 864 // CHECK5-NEXT:    [[SVAR_ADDR:%.*]] = alloca i64, align 8
 865 // CHECK5-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 866 // CHECK5-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
 867 // CHECK5-NEXT:    [[SVAR_CASTED:%.*]] = alloca i64, align 8
 868 // CHECK5-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
 869 // CHECK5-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
 870 // CHECK5-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
 871 // CHECK5-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
 872 // CHECK5-NEXT:    store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
 873 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
 874 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
 875 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
 876 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8
 877 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
 878 // CHECK5-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
 879 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
 880 // CHECK5-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
 881 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4
 882 // CHECK5-NEXT:    store i32 [[TMP6]], ptr [[SVAR_CASTED]], align 4
 883 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8
 884 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]], i64 [[TMP7]])
 885 // CHECK5-NEXT:    ret void
 886 //
 887 //
 888 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined
 889 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] {
 890 // CHECK5-NEXT:  entry:
 891 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 892 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 893 // CHECK5-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
 894 // CHECK5-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
 895 // CHECK5-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
 896 // CHECK5-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
 897 // CHECK5-NEXT:    [[SVAR_ADDR:%.*]] = alloca i64, align 8
 898 // CHECK5-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 899 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 900 // CHECK5-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 901 // CHECK5-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 902 // CHECK5-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 903 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 904 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 905 // CHECK5-NEXT:    [[T_VAR2:%.*]] = alloca i32, align 4
 906 // CHECK5-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 4
 907 // CHECK5-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4
 908 // CHECK5-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 909 // CHECK5-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 8
 910 // CHECK5-NEXT:    [[SVAR7:%.*]] = alloca i32, align 4
 911 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
 912 // CHECK5-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
 913 // CHECK5-NEXT:    [[SVAR_CASTED:%.*]] = alloca i64, align 8
 914 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 915 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 916 // CHECK5-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
 917 // CHECK5-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
 918 // CHECK5-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
 919 // CHECK5-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
 920 // CHECK5-NEXT:    store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
 921 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
 922 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
 923 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
 924 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8
 925 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 926 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
 927 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 928 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 929 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0
 930 // CHECK5-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
 931 // CHECK5-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 932 // CHECK5:       arrayctor.loop:
 933 // CHECK5-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 934 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
 935 // CHECK5-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
 936 // CHECK5-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 937 // CHECK5-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 938 // CHECK5:       arrayctor.cont:
 939 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
 940 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
 941 // CHECK5-NEXT:    store ptr [[VAR5]], ptr [[_TMP6]], align 8
 942 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 943 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
 944 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 945 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 946 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
 947 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 948 // CHECK5:       cond.true:
 949 // CHECK5-NEXT:    br label [[COND_END:%.*]]
 950 // CHECK5:       cond.false:
 951 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 952 // CHECK5-NEXT:    br label [[COND_END]]
 953 // CHECK5:       cond.end:
 954 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
 955 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 956 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 957 // CHECK5-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
 958 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 959 // CHECK5:       omp.inner.for.cond:
 960 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 961 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 962 // CHECK5-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
 963 // CHECK5-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 964 // CHECK5:       omp.inner.for.cond.cleanup:
 965 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 966 // CHECK5:       omp.inner.for.body:
 967 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 968 // CHECK5-NEXT:    [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
 969 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 970 // CHECK5-NEXT:    [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
 971 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR2]], align 4
 972 // CHECK5-NEXT:    store i32 [[TMP15]], ptr [[T_VAR_CASTED]], align 4
 973 // CHECK5-NEXT:    [[TMP16:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
 974 // CHECK5-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 8
 975 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, ptr [[SVAR7]], align 4
 976 // CHECK5-NEXT:    store i32 [[TMP18]], ptr [[SVAR_CASTED]], align 4
 977 // CHECK5-NEXT:    [[TMP19:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8
 978 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], ptr [[VEC3]], i64 [[TMP16]], ptr [[S_ARR4]], ptr [[TMP17]], i64 [[TMP19]])
 979 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 980 // CHECK5:       omp.inner.for.inc:
 981 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 982 // CHECK5-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 983 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
 984 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
 985 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]]
 986 // CHECK5:       omp.inner.for.end:
 987 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 988 // CHECK5:       omp.loop.exit:
 989 // CHECK5-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 990 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
 991 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP23]])
 992 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 993 // CHECK5-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
 994 // CHECK5-NEXT:    br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
 995 // CHECK5:       .omp.lastprivate.then:
 996 // CHECK5-NEXT:    [[TMP26:%.*]] = load i32, ptr [[T_VAR2]], align 4
 997 // CHECK5-NEXT:    store i32 [[TMP26]], ptr [[T_VAR_ADDR]], align 4
 998 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false)
 999 // CHECK5-NEXT:    [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0
1000 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i64 2
1001 // CHECK5-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP27]]
1002 // CHECK5-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1003 // CHECK5:       omp.arraycpy.body:
1004 // CHECK5-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1005 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1006 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)
1007 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1008 // CHECK5-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1009 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]]
1010 // CHECK5-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]]
1011 // CHECK5:       omp.arraycpy.done10:
1012 // CHECK5-NEXT:    [[TMP28:%.*]] = load ptr, ptr [[_TMP6]], align 8
1013 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP3]], ptr align 4 [[TMP28]], i64 4, i1 false)
1014 // CHECK5-NEXT:    [[TMP29:%.*]] = load i32, ptr [[SVAR7]], align 4
1015 // CHECK5-NEXT:    store i32 [[TMP29]], ptr [[SVAR_ADDR]], align 4
1016 // CHECK5-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
1017 // CHECK5:       .omp.lastprivate.done:
1018 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
1019 // CHECK5-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0
1020 // CHECK5-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2
1021 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1022 // CHECK5:       arraydestroy.body:
1023 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1024 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1025 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1026 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
1027 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
1028 // CHECK5:       arraydestroy.done12:
1029 // CHECK5-NEXT:    ret void
1030 //
1031 //
1032 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined.omp_outlined
1033 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] {
1034 // CHECK5-NEXT:  entry:
1035 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1036 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1037 // CHECK5-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1038 // CHECK5-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1039 // CHECK5-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
1040 // CHECK5-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1041 // CHECK5-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1042 // CHECK5-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
1043 // CHECK5-NEXT:    [[SVAR_ADDR:%.*]] = alloca i64, align 8
1044 // CHECK5-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
1045 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1046 // CHECK5-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1047 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1048 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1049 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1050 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1051 // CHECK5-NEXT:    [[T_VAR3:%.*]] = alloca i32, align 4
1052 // CHECK5-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 4
1053 // CHECK5-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
1054 // CHECK5-NEXT:    [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1055 // CHECK5-NEXT:    [[_TMP7:%.*]] = alloca ptr, align 8
1056 // CHECK5-NEXT:    [[SVAR8:%.*]] = alloca i32, align 4
1057 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
1058 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1059 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1060 // CHECK5-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1061 // CHECK5-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1062 // CHECK5-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1063 // CHECK5-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1064 // CHECK5-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1065 // CHECK5-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1066 // CHECK5-NEXT:    store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
1067 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1068 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1069 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1070 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8
1071 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1072 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1073 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1074 // CHECK5-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP3]] to i32
1075 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1076 // CHECK5-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32
1077 // CHECK5-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
1078 // CHECK5-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
1079 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1080 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1081 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0
1082 // CHECK5-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
1083 // CHECK5-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1084 // CHECK5:       arrayctor.loop:
1085 // CHECK5-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1086 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1087 // CHECK5-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
1088 // CHECK5-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1089 // CHECK5-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1090 // CHECK5:       arrayctor.cont:
1091 // CHECK5-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
1092 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]])
1093 // CHECK5-NEXT:    store ptr [[VAR6]], ptr [[_TMP7]], align 8
1094 // CHECK5-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1095 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
1096 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1097 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1098 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
1099 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1100 // CHECK5:       cond.true:
1101 // CHECK5-NEXT:    br label [[COND_END:%.*]]
1102 // CHECK5:       cond.false:
1103 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1104 // CHECK5-NEXT:    br label [[COND_END]]
1105 // CHECK5:       cond.end:
1106 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
1107 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1108 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1109 // CHECK5-NEXT:    store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4
1110 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1111 // CHECK5:       omp.inner.for.cond:
1112 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1113 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1114 // CHECK5-NEXT:    [[CMP9:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
1115 // CHECK5-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1116 // CHECK5:       omp.inner.for.cond.cleanup:
1117 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1118 // CHECK5:       omp.inner.for.body:
1119 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1120 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
1121 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1122 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
1123 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4
1124 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4
1125 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
1126 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]]
1127 // CHECK5-NEXT:    store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4
1128 // CHECK5-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8
1129 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4
1130 // CHECK5-NEXT:    [[IDXPROM10:%.*]] = sext i32 [[TMP17]] to i64
1131 // CHECK5-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
1132 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP16]], i64 4, i1 false)
1133 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1134 // CHECK5:       omp.body.continue:
1135 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1136 // CHECK5:       omp.inner.for.inc:
1137 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1138 // CHECK5-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
1139 // CHECK5-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4
1140 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]]
1141 // CHECK5:       omp.inner.for.end:
1142 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1143 // CHECK5:       omp.loop.exit:
1144 // CHECK5-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1145 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
1146 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP20]])
1147 // CHECK5-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1148 // CHECK5-NEXT:    [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
1149 // CHECK5-NEXT:    br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1150 // CHECK5:       .omp.lastprivate.then:
1151 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, ptr [[T_VAR3]], align 4
1152 // CHECK5-NEXT:    store i32 [[TMP23]], ptr [[T_VAR_ADDR]], align 4
1153 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false)
1154 // CHECK5-NEXT:    [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0
1155 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i64 2
1156 // CHECK5-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN13]], [[TMP24]]
1157 // CHECK5-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1158 // CHECK5:       omp.arraycpy.body:
1159 // CHECK5-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR5]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1160 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1161 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)
1162 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1163 // CHECK5-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1164 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP24]]
1165 // CHECK5-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]]
1166 // CHECK5:       omp.arraycpy.done14:
1167 // CHECK5-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[_TMP7]], align 8
1168 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP25]], i64 4, i1 false)
1169 // CHECK5-NEXT:    [[TMP26:%.*]] = load i32, ptr [[SVAR8]], align 4
1170 // CHECK5-NEXT:    store i32 [[TMP26]], ptr [[SVAR_ADDR]], align 4
1171 // CHECK5-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
1172 // CHECK5:       .omp.lastprivate.done:
1173 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
1174 // CHECK5-NEXT:    [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0
1175 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i64 2
1176 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1177 // CHECK5:       arraydestroy.body:
1178 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1179 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1180 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1181 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]]
1182 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]]
1183 // CHECK5:       arraydestroy.done16:
1184 // CHECK5-NEXT:    ret void
1185 //
1186 //
1187 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1188 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1189 // CHECK5-NEXT:  entry:
1190 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1191 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1192 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1193 // CHECK5-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
1194 // CHECK5-NEXT:    ret void
1195 //
1196 //
1197 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1198 // CHECK5-SAME: () #[[ATTR1]] comdat {
1199 // CHECK5-NEXT:  entry:
1200 // CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1201 // CHECK5-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1202 // CHECK5-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1203 // CHECK5-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1204 // CHECK5-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1205 // CHECK5-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
1206 // CHECK5-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
1207 // CHECK5-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1208 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
1209 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
1210 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
1211 // CHECK5-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1212 // CHECK5-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1213 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1214 // CHECK5-NEXT:    store i32 0, ptr [[T_VAR]], align 4
1215 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
1216 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)
1217 // CHECK5-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1
1218 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
1219 // CHECK5-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
1220 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
1221 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 8
1222 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
1223 // CHECK5-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
1224 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
1225 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
1226 // CHECK5-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1227 // CHECK5-NEXT:    store ptr [[VEC]], ptr [[TMP4]], align 8
1228 // CHECK5-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1229 // CHECK5-NEXT:    store ptr [[VEC]], ptr [[TMP5]], align 8
1230 // CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1231 // CHECK5-NEXT:    store ptr null, ptr [[TMP6]], align 8
1232 // CHECK5-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1233 // CHECK5-NEXT:    store i64 [[TMP2]], ptr [[TMP7]], align 8
1234 // CHECK5-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1235 // CHECK5-NEXT:    store i64 [[TMP2]], ptr [[TMP8]], align 8
1236 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1237 // CHECK5-NEXT:    store ptr null, ptr [[TMP9]], align 8
1238 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1239 // CHECK5-NEXT:    store ptr [[S_ARR]], ptr [[TMP10]], align 8
1240 // CHECK5-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1241 // CHECK5-NEXT:    store ptr [[S_ARR]], ptr [[TMP11]], align 8
1242 // CHECK5-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1243 // CHECK5-NEXT:    store ptr null, ptr [[TMP12]], align 8
1244 // CHECK5-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1245 // CHECK5-NEXT:    store ptr [[TMP3]], ptr [[TMP13]], align 8
1246 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1247 // CHECK5-NEXT:    store ptr [[TMP3]], ptr [[TMP14]], align 8
1248 // CHECK5-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1249 // CHECK5-NEXT:    store ptr null, ptr [[TMP15]], align 8
1250 // CHECK5-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1251 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1252 // CHECK5-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1253 // CHECK5-NEXT:    store i32 3, ptr [[TMP18]], align 4
1254 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1255 // CHECK5-NEXT:    store i32 4, ptr [[TMP19]], align 4
1256 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1257 // CHECK5-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 8
1258 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1259 // CHECK5-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 8
1260 // CHECK5-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1261 // CHECK5-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP22]], align 8
1262 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1263 // CHECK5-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP23]], align 8
1264 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1265 // CHECK5-NEXT:    store ptr null, ptr [[TMP24]], align 8
1266 // CHECK5-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1267 // CHECK5-NEXT:    store ptr null, ptr [[TMP25]], align 8
1268 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1269 // CHECK5-NEXT:    store i64 2, ptr [[TMP26]], align 8
1270 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1271 // CHECK5-NEXT:    store i64 0, ptr [[TMP27]], align 8
1272 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1273 // CHECK5-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4
1274 // CHECK5-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1275 // CHECK5-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4
1276 // CHECK5-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1277 // CHECK5-NEXT:    store i32 0, ptr [[TMP30]], align 4
1278 // CHECK5-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.region_id, ptr [[KERNEL_ARGS]])
1279 // CHECK5-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
1280 // CHECK5-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1281 // CHECK5:       omp_offload.failed:
1282 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50(ptr [[VEC]], i64 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]]
1283 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1284 // CHECK5:       omp_offload.cont:
1285 // CHECK5-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1286 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1287 // CHECK5-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1288 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1289 // CHECK5:       arraydestroy.body:
1290 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1291 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1292 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1293 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1294 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1295 // CHECK5:       arraydestroy.done2:
1296 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1297 // CHECK5-NEXT:    [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4
1298 // CHECK5-NEXT:    ret i32 [[TMP34]]
1299 //
1300 //
1301 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1302 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1303 // CHECK5-NEXT:  entry:
1304 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1305 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1306 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1307 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1308 // CHECK5-NEXT:    store float 0.000000e+00, ptr [[F]], align 4
1309 // CHECK5-NEXT:    ret void
1310 //
1311 //
1312 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1313 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1314 // CHECK5-NEXT:  entry:
1315 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1316 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1317 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1318 // CHECK5-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1319 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1320 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1321 // CHECK5-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1322 // CHECK5-NEXT:    store float [[TMP0]], ptr [[F]], align 4
1323 // CHECK5-NEXT:    ret void
1324 //
1325 //
1326 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1327 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1328 // CHECK5-NEXT:  entry:
1329 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1330 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1331 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1332 // CHECK5-NEXT:    ret void
1333 //
1334 //
1335 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1336 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1337 // CHECK5-NEXT:  entry:
1338 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1339 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1340 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1341 // CHECK5-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1342 // CHECK5-NEXT:    ret void
1343 //
1344 //
1345 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1346 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1347 // CHECK5-NEXT:  entry:
1348 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1349 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1350 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1351 // CHECK5-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1352 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1353 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1354 // CHECK5-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
1355 // CHECK5-NEXT:    ret void
1356 //
1357 //
1358 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50
1359 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1360 // CHECK5-NEXT:  entry:
1361 // CHECK5-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
1362 // CHECK5-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1363 // CHECK5-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1364 // CHECK5-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
1365 // CHECK5-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
1366 // CHECK5-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1367 // CHECK5-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1368 // CHECK5-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1369 // CHECK5-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1370 // CHECK5-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1371 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1372 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1373 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1374 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8
1375 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
1376 // CHECK5-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
1377 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
1378 // CHECK5-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
1379 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])
1380 // CHECK5-NEXT:    ret void
1381 //
1382 //
1383 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined
1384 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1385 // CHECK5-NEXT:  entry:
1386 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1387 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1388 // CHECK5-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
1389 // CHECK5-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1390 // CHECK5-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1391 // CHECK5-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
1392 // CHECK5-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
1393 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1394 // CHECK5-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1395 // CHECK5-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1396 // CHECK5-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1397 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1398 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1399 // CHECK5-NEXT:    [[T_VAR2:%.*]] = alloca i32, align 4
1400 // CHECK5-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 4
1401 // CHECK5-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
1402 // CHECK5-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1403 // CHECK5-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 8
1404 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
1405 // CHECK5-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1406 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1407 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1408 // CHECK5-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1409 // CHECK5-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1410 // CHECK5-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1411 // CHECK5-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1412 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1413 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1414 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1415 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8
1416 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1417 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
1418 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1419 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1420 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1421 // CHECK5-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1422 // CHECK5-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1423 // CHECK5:       arrayctor.loop:
1424 // CHECK5-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1425 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1426 // CHECK5-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
1427 // CHECK5-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1428 // CHECK5-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1429 // CHECK5:       arrayctor.cont:
1430 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
1431 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
1432 // CHECK5-NEXT:    store ptr [[VAR5]], ptr [[_TMP6]], align 8
1433 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1434 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1435 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1436 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1437 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
1438 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1439 // CHECK5:       cond.true:
1440 // CHECK5-NEXT:    br label [[COND_END:%.*]]
1441 // CHECK5:       cond.false:
1442 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1443 // CHECK5-NEXT:    br label [[COND_END]]
1444 // CHECK5:       cond.end:
1445 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1446 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1447 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1448 // CHECK5-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
1449 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1450 // CHECK5:       omp.inner.for.cond:
1451 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1452 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1453 // CHECK5-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1454 // CHECK5-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1455 // CHECK5:       omp.inner.for.cond.cleanup:
1456 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1457 // CHECK5:       omp.inner.for.body:
1458 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1459 // CHECK5-NEXT:    [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
1460 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1461 // CHECK5-NEXT:    [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
1462 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR2]], align 4
1463 // CHECK5-NEXT:    store i32 [[TMP15]], ptr [[T_VAR_CASTED]], align 4
1464 // CHECK5-NEXT:    [[TMP16:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
1465 // CHECK5-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 8
1466 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], ptr [[VEC3]], i64 [[TMP16]], ptr [[S_ARR4]], ptr [[TMP17]])
1467 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1468 // CHECK5:       omp.inner.for.inc:
1469 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1470 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1471 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
1472 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
1473 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]]
1474 // CHECK5:       omp.inner.for.end:
1475 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1476 // CHECK5:       omp.loop.exit:
1477 // CHECK5-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1478 // CHECK5-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
1479 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]])
1480 // CHECK5-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1481 // CHECK5-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
1482 // CHECK5-NEXT:    br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1483 // CHECK5:       .omp.lastprivate.then:
1484 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, ptr [[T_VAR2]], align 4
1485 // CHECK5-NEXT:    store i32 [[TMP24]], ptr [[T_VAR_ADDR]], align 4
1486 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false)
1487 // CHECK5-NEXT:    [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0
1488 // CHECK5-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2
1489 // CHECK5-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP25]]
1490 // CHECK5-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1491 // CHECK5:       omp.arraycpy.body:
1492 // CHECK5-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1493 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN8]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1494 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)
1495 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1496 // CHECK5-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1497 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP25]]
1498 // CHECK5-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]]
1499 // CHECK5:       omp.arraycpy.done9:
1500 // CHECK5-NEXT:    [[TMP26:%.*]] = load ptr, ptr [[_TMP6]], align 8
1501 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP3]], ptr align 4 [[TMP26]], i64 4, i1 false)
1502 // CHECK5-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
1503 // CHECK5:       .omp.lastprivate.done:
1504 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
1505 // CHECK5-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1506 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2
1507 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1508 // CHECK5:       arraydestroy.body:
1509 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1510 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1511 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1512 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1513 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1514 // CHECK5:       arraydestroy.done11:
1515 // CHECK5-NEXT:    ret void
1516 //
1517 //
1518 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined.omp_outlined
1519 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1520 // CHECK5-NEXT:  entry:
1521 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1522 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1523 // CHECK5-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1524 // CHECK5-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1525 // CHECK5-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
1526 // CHECK5-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1527 // CHECK5-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1528 // CHECK5-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
1529 // CHECK5-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
1530 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1531 // CHECK5-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1532 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1533 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1534 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1535 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1536 // CHECK5-NEXT:    [[T_VAR3:%.*]] = alloca i32, align 4
1537 // CHECK5-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 4
1538 // CHECK5-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
1539 // CHECK5-NEXT:    [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1540 // CHECK5-NEXT:    [[_TMP7:%.*]] = alloca ptr, align 8
1541 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
1542 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1543 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1544 // CHECK5-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1545 // CHECK5-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1546 // CHECK5-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1547 // CHECK5-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1548 // CHECK5-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1549 // CHECK5-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1550 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1551 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1552 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1553 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8
1554 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1555 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1556 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1557 // CHECK5-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP3]] to i32
1558 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1559 // CHECK5-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32
1560 // CHECK5-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
1561 // CHECK5-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
1562 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1563 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1564 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0
1565 // CHECK5-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1566 // CHECK5-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1567 // CHECK5:       arrayctor.loop:
1568 // CHECK5-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1569 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1570 // CHECK5-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
1571 // CHECK5-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1572 // CHECK5-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1573 // CHECK5:       arrayctor.cont:
1574 // CHECK5-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
1575 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]])
1576 // CHECK5-NEXT:    store ptr [[VAR6]], ptr [[_TMP7]], align 8
1577 // CHECK5-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1578 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
1579 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1580 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1581 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
1582 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1583 // CHECK5:       cond.true:
1584 // CHECK5-NEXT:    br label [[COND_END:%.*]]
1585 // CHECK5:       cond.false:
1586 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1587 // CHECK5-NEXT:    br label [[COND_END]]
1588 // CHECK5:       cond.end:
1589 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
1590 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1591 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1592 // CHECK5-NEXT:    store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4
1593 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1594 // CHECK5:       omp.inner.for.cond:
1595 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1596 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1597 // CHECK5-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
1598 // CHECK5-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1599 // CHECK5:       omp.inner.for.cond.cleanup:
1600 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1601 // CHECK5:       omp.inner.for.body:
1602 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1603 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
1604 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1605 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
1606 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4
1607 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4
1608 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
1609 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]]
1610 // CHECK5-NEXT:    store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4
1611 // CHECK5-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8
1612 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4
1613 // CHECK5-NEXT:    [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64
1614 // CHECK5-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]]
1615 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP16]], i64 4, i1 false)
1616 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1617 // CHECK5:       omp.body.continue:
1618 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1619 // CHECK5:       omp.inner.for.inc:
1620 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1621 // CHECK5-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP18]], 1
1622 // CHECK5-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4
1623 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]]
1624 // CHECK5:       omp.inner.for.end:
1625 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1626 // CHECK5:       omp.loop.exit:
1627 // CHECK5-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1628 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
1629 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP20]])
1630 // CHECK5-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1631 // CHECK5-NEXT:    [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
1632 // CHECK5-NEXT:    br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1633 // CHECK5:       .omp.lastprivate.then:
1634 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, ptr [[T_VAR3]], align 4
1635 // CHECK5-NEXT:    store i32 [[TMP23]], ptr [[T_VAR_ADDR]], align 4
1636 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false)
1637 // CHECK5-NEXT:    [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0
1638 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2
1639 // CHECK5-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP24]]
1640 // CHECK5-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1641 // CHECK5:       omp.arraycpy.body:
1642 // CHECK5-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR5]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1643 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1644 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)
1645 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1646 // CHECK5-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1647 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP24]]
1648 // CHECK5-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]]
1649 // CHECK5:       omp.arraycpy.done13:
1650 // CHECK5-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[_TMP7]], align 8
1651 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP25]], i64 4, i1 false)
1652 // CHECK5-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
1653 // CHECK5:       .omp.lastprivate.done:
1654 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
1655 // CHECK5-NEXT:    [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0
1656 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2
1657 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1658 // CHECK5:       arraydestroy.body:
1659 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1660 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1661 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1662 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
1663 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
1664 // CHECK5:       arraydestroy.done15:
1665 // CHECK5-NEXT:    ret void
1666 //
1667 //
1668 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1669 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1670 // CHECK5-NEXT:  entry:
1671 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1672 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1673 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1674 // CHECK5-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
1675 // CHECK5-NEXT:    ret void
1676 //
1677 //
1678 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1679 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1680 // CHECK5-NEXT:  entry:
1681 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1682 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1683 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1684 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1685 // CHECK5-NEXT:    store i32 0, ptr [[F]], align 4
1686 // CHECK5-NEXT:    ret void
1687 //
1688 //
1689 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1690 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1691 // CHECK5-NEXT:  entry:
1692 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1693 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1694 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1695 // CHECK5-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1696 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1697 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1698 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1699 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
1700 // CHECK5-NEXT:    ret void
1701 //
1702 //
1703 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1704 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1705 // CHECK5-NEXT:  entry:
1706 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1707 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1708 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1709 // CHECK5-NEXT:    ret void
1710 //
1711 //
1712 // CHECK7-LABEL: define {{[^@]+}}@main
1713 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
1714 // CHECK7-NEXT:  entry:
1715 // CHECK7-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1716 // CHECK7-NEXT:    [[G:%.*]] = alloca double, align 8
1717 // CHECK7-NEXT:    [[G1:%.*]] = alloca ptr, align 4
1718 // CHECK7-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1719 // CHECK7-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1720 // CHECK7-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1721 // CHECK7-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1722 // CHECK7-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
1723 // CHECK7-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1724 // CHECK7-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1725 // CHECK7-NEXT:    [[SVAR_CASTED:%.*]] = alloca i32, align 4
1726 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
1727 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
1728 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
1729 // CHECK7-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1730 // CHECK7-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1731 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
1732 // CHECK7-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1733 // CHECK7-NEXT:    store ptr [[G]], ptr [[G1]], align 4
1734 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1735 // CHECK7-NEXT:    store i32 0, ptr [[T_VAR]], align 4
1736 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false)
1737 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)
1738 // CHECK7-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1
1739 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
1740 // CHECK7-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
1741 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4
1742 // CHECK7-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 4
1743 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
1744 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
1745 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
1746 // CHECK7-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
1747 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4
1748 // CHECK7-NEXT:    store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4
1749 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4
1750 // CHECK7-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1751 // CHECK7-NEXT:    store ptr [[VEC]], ptr [[TMP6]], align 4
1752 // CHECK7-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1753 // CHECK7-NEXT:    store ptr [[VEC]], ptr [[TMP7]], align 4
1754 // CHECK7-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1755 // CHECK7-NEXT:    store ptr null, ptr [[TMP8]], align 4
1756 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1757 // CHECK7-NEXT:    store i32 [[TMP2]], ptr [[TMP9]], align 4
1758 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1759 // CHECK7-NEXT:    store i32 [[TMP2]], ptr [[TMP10]], align 4
1760 // CHECK7-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1761 // CHECK7-NEXT:    store ptr null, ptr [[TMP11]], align 4
1762 // CHECK7-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1763 // CHECK7-NEXT:    store ptr [[S_ARR]], ptr [[TMP12]], align 4
1764 // CHECK7-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1765 // CHECK7-NEXT:    store ptr [[S_ARR]], ptr [[TMP13]], align 4
1766 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1767 // CHECK7-NEXT:    store ptr null, ptr [[TMP14]], align 4
1768 // CHECK7-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1769 // CHECK7-NEXT:    store ptr [[TMP3]], ptr [[TMP15]], align 4
1770 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1771 // CHECK7-NEXT:    store ptr [[TMP3]], ptr [[TMP16]], align 4
1772 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1773 // CHECK7-NEXT:    store ptr null, ptr [[TMP17]], align 4
1774 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1775 // CHECK7-NEXT:    store i32 [[TMP5]], ptr [[TMP18]], align 4
1776 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1777 // CHECK7-NEXT:    store i32 [[TMP5]], ptr [[TMP19]], align 4
1778 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1779 // CHECK7-NEXT:    store ptr null, ptr [[TMP20]], align 4
1780 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1781 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1782 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1783 // CHECK7-NEXT:    store i32 3, ptr [[TMP23]], align 4
1784 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1785 // CHECK7-NEXT:    store i32 5, ptr [[TMP24]], align 4
1786 // CHECK7-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1787 // CHECK7-NEXT:    store ptr [[TMP21]], ptr [[TMP25]], align 4
1788 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1789 // CHECK7-NEXT:    store ptr [[TMP22]], ptr [[TMP26]], align 4
1790 // CHECK7-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1791 // CHECK7-NEXT:    store ptr @.offload_sizes, ptr [[TMP27]], align 4
1792 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1793 // CHECK7-NEXT:    store ptr @.offload_maptypes, ptr [[TMP28]], align 4
1794 // CHECK7-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1795 // CHECK7-NEXT:    store ptr null, ptr [[TMP29]], align 4
1796 // CHECK7-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1797 // CHECK7-NEXT:    store ptr null, ptr [[TMP30]], align 4
1798 // CHECK7-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1799 // CHECK7-NEXT:    store i64 2, ptr [[TMP31]], align 8
1800 // CHECK7-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1801 // CHECK7-NEXT:    store i64 0, ptr [[TMP32]], align 8
1802 // CHECK7-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1803 // CHECK7-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP33]], align 4
1804 // CHECK7-NEXT:    [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1805 // CHECK7-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP34]], align 4
1806 // CHECK7-NEXT:    [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1807 // CHECK7-NEXT:    store i32 0, ptr [[TMP35]], align 4
1808 // CHECK7-NEXT:    [[TMP36:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, ptr [[KERNEL_ARGS]])
1809 // CHECK7-NEXT:    [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0
1810 // CHECK7-NEXT:    br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1811 // CHECK7:       omp_offload.failed:
1812 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(ptr [[VEC]], i32 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]], i32 [[TMP5]]) #[[ATTR4:[0-9]+]]
1813 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1814 // CHECK7:       omp_offload.cont:
1815 // CHECK7-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1816 // CHECK7-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
1817 // CHECK7-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1818 // CHECK7-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
1819 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1820 // CHECK7:       arraydestroy.body:
1821 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1822 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1823 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1824 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1825 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1826 // CHECK7:       arraydestroy.done2:
1827 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1828 // CHECK7-NEXT:    [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4
1829 // CHECK7-NEXT:    ret i32 [[TMP39]]
1830 //
1831 //
1832 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1833 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1834 // CHECK7-NEXT:  entry:
1835 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1836 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1837 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1838 // CHECK7-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1839 // CHECK7-NEXT:    ret void
1840 //
1841 //
1842 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1843 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1844 // CHECK7-NEXT:  entry:
1845 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1846 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1847 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1848 // CHECK7-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1849 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1850 // CHECK7-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1851 // CHECK7-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1852 // CHECK7-NEXT:    ret void
1853 //
1854 //
1855 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106
1856 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {
1857 // CHECK7-NEXT:  entry:
1858 // CHECK7-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
1859 // CHECK7-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1860 // CHECK7-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1861 // CHECK7-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
1862 // CHECK7-NEXT:    [[SVAR_ADDR:%.*]] = alloca i32, align 4
1863 // CHECK7-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1864 // CHECK7-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1865 // CHECK7-NEXT:    [[SVAR_CASTED:%.*]] = alloca i32, align 4
1866 // CHECK7-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1867 // CHECK7-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1868 // CHECK7-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1869 // CHECK7-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1870 // CHECK7-NEXT:    store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
1871 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1872 // CHECK7-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1873 // CHECK7-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1874 // CHECK7-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 4
1875 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
1876 // CHECK7-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
1877 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
1878 // CHECK7-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
1879 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4
1880 // CHECK7-NEXT:    store i32 [[TMP6]], ptr [[SVAR_CASTED]], align 4
1881 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4
1882 // CHECK7-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]], i32 [[TMP7]])
1883 // CHECK7-NEXT:    ret void
1884 //
1885 //
1886 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined
1887 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] {
1888 // CHECK7-NEXT:  entry:
1889 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1890 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1891 // CHECK7-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
1892 // CHECK7-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1893 // CHECK7-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1894 // CHECK7-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
1895 // CHECK7-NEXT:    [[SVAR_ADDR:%.*]] = alloca i32, align 4
1896 // CHECK7-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1897 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1898 // CHECK7-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1899 // CHECK7-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1900 // CHECK7-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1901 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1902 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1903 // CHECK7-NEXT:    [[T_VAR2:%.*]] = alloca i32, align 4
1904 // CHECK7-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 4
1905 // CHECK7-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4
1906 // CHECK7-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1907 // CHECK7-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 4
1908 // CHECK7-NEXT:    [[SVAR7:%.*]] = alloca i32, align 4
1909 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
1910 // CHECK7-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1911 // CHECK7-NEXT:    [[SVAR_CASTED:%.*]] = alloca i32, align 4
1912 // CHECK7-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1913 // CHECK7-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1914 // CHECK7-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1915 // CHECK7-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1916 // CHECK7-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1917 // CHECK7-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1918 // CHECK7-NEXT:    store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
1919 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1920 // CHECK7-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1921 // CHECK7-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1922 // CHECK7-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 4
1923 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1924 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
1925 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1926 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1927 // CHECK7-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0
1928 // CHECK7-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
1929 // CHECK7-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1930 // CHECK7:       arrayctor.loop:
1931 // CHECK7-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1932 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1933 // CHECK7-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1
1934 // CHECK7-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1935 // CHECK7-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1936 // CHECK7:       arrayctor.cont:
1937 // CHECK7-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
1938 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
1939 // CHECK7-NEXT:    store ptr [[VAR5]], ptr [[_TMP6]], align 4
1940 // CHECK7-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1941 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1942 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1943 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1944 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
1945 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1946 // CHECK7:       cond.true:
1947 // CHECK7-NEXT:    br label [[COND_END:%.*]]
1948 // CHECK7:       cond.false:
1949 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1950 // CHECK7-NEXT:    br label [[COND_END]]
1951 // CHECK7:       cond.end:
1952 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1953 // CHECK7-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1954 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1955 // CHECK7-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
1956 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1957 // CHECK7:       omp.inner.for.cond:
1958 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1959 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1960 // CHECK7-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1961 // CHECK7-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1962 // CHECK7:       omp.inner.for.cond.cleanup:
1963 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1964 // CHECK7:       omp.inner.for.body:
1965 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1966 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1967 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, ptr [[T_VAR2]], align 4
1968 // CHECK7-NEXT:    store i32 [[TMP13]], ptr [[T_VAR_CASTED]], align 4
1969 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
1970 // CHECK7-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4
1971 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, ptr [[SVAR7]], align 4
1972 // CHECK7-NEXT:    store i32 [[TMP16]], ptr [[SVAR_CASTED]], align 4
1973 // CHECK7-NEXT:    [[TMP17:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4
1974 // CHECK7-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined.omp_outlined, i32 [[TMP11]], i32 [[TMP12]], ptr [[VEC3]], i32 [[TMP14]], ptr [[S_ARR4]], ptr [[TMP15]], i32 [[TMP17]])
1975 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1976 // CHECK7:       omp.inner.for.inc:
1977 // CHECK7-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1978 // CHECK7-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1979 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
1980 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
1981 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]]
1982 // CHECK7:       omp.inner.for.end:
1983 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1984 // CHECK7:       omp.loop.exit:
1985 // CHECK7-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1986 // CHECK7-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
1987 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]])
1988 // CHECK7-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1989 // CHECK7-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
1990 // CHECK7-NEXT:    br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1991 // CHECK7:       .omp.lastprivate.then:
1992 // CHECK7-NEXT:    [[TMP24:%.*]] = load i32, ptr [[T_VAR2]], align 4
1993 // CHECK7-NEXT:    store i32 [[TMP24]], ptr [[T_VAR_ADDR]], align 4
1994 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false)
1995 // CHECK7-NEXT:    [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0
1996 // CHECK7-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i32 2
1997 // CHECK7-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP25]]
1998 // CHECK7-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1999 // CHECK7:       omp.arraycpy.body:
2000 // CHECK7-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2001 // CHECK7-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2002 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)
2003 // CHECK7-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2004 // CHECK7-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2005 // CHECK7-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP25]]
2006 // CHECK7-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]]
2007 // CHECK7:       omp.arraycpy.done10:
2008 // CHECK7-NEXT:    [[TMP26:%.*]] = load ptr, ptr [[_TMP6]], align 4
2009 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP3]], ptr align 4 [[TMP26]], i32 4, i1 false)
2010 // CHECK7-NEXT:    [[TMP27:%.*]] = load i32, ptr [[SVAR7]], align 4
2011 // CHECK7-NEXT:    store i32 [[TMP27]], ptr [[SVAR_ADDR]], align 4
2012 // CHECK7-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
2013 // CHECK7:       .omp.lastprivate.done:
2014 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
2015 // CHECK7-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0
2016 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2
2017 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2018 // CHECK7:       arraydestroy.body:
2019 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2020 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2021 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2022 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
2023 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
2024 // CHECK7:       arraydestroy.done12:
2025 // CHECK7-NEXT:    ret void
2026 //
2027 //
2028 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined.omp_outlined
2029 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] {
2030 // CHECK7-NEXT:  entry:
2031 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2032 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2033 // CHECK7-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2034 // CHECK7-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2035 // CHECK7-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
2036 // CHECK7-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2037 // CHECK7-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
2038 // CHECK7-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
2039 // CHECK7-NEXT:    [[SVAR_ADDR:%.*]] = alloca i32, align 4
2040 // CHECK7-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
2041 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2042 // CHECK7-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2043 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2044 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2045 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2046 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2047 // CHECK7-NEXT:    [[T_VAR2:%.*]] = alloca i32, align 4
2048 // CHECK7-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 4
2049 // CHECK7-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4
2050 // CHECK7-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2051 // CHECK7-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 4
2052 // CHECK7-NEXT:    [[SVAR7:%.*]] = alloca i32, align 4
2053 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
2054 // CHECK7-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2055 // CHECK7-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2056 // CHECK7-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2057 // CHECK7-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2058 // CHECK7-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
2059 // CHECK7-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
2060 // CHECK7-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
2061 // CHECK7-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
2062 // CHECK7-NEXT:    store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
2063 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
2064 // CHECK7-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
2065 // CHECK7-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
2066 // CHECK7-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 4
2067 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2068 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2069 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2070 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2071 // CHECK7-NEXT:    store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4
2072 // CHECK7-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
2073 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2074 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2075 // CHECK7-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0
2076 // CHECK7-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
2077 // CHECK7-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
2078 // CHECK7:       arrayctor.loop:
2079 // CHECK7-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2080 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2081 // CHECK7-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1
2082 // CHECK7-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2083 // CHECK7-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2084 // CHECK7:       arrayctor.cont:
2085 // CHECK7-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
2086 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
2087 // CHECK7-NEXT:    store ptr [[VAR5]], ptr [[_TMP6]], align 4
2088 // CHECK7-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2089 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
2090 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2091 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2092 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
2093 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2094 // CHECK7:       cond.true:
2095 // CHECK7-NEXT:    br label [[COND_END:%.*]]
2096 // CHECK7:       cond.false:
2097 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2098 // CHECK7-NEXT:    br label [[COND_END]]
2099 // CHECK7:       cond.end:
2100 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
2101 // CHECK7-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2102 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2103 // CHECK7-NEXT:    store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4
2104 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2105 // CHECK7:       omp.inner.for.cond:
2106 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2107 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2108 // CHECK7-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
2109 // CHECK7-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2110 // CHECK7:       omp.inner.for.cond.cleanup:
2111 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2112 // CHECK7:       omp.inner.for.body:
2113 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2114 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
2115 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2116 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
2117 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4
2118 // CHECK7-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4
2119 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP15]]
2120 // CHECK7-NEXT:    store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4
2121 // CHECK7-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4
2122 // CHECK7-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4
2123 // CHECK7-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP17]]
2124 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP16]], i32 4, i1 false)
2125 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2126 // CHECK7:       omp.body.continue:
2127 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2128 // CHECK7:       omp.inner.for.inc:
2129 // CHECK7-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2130 // CHECK7-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP18]], 1
2131 // CHECK7-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
2132 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]]
2133 // CHECK7:       omp.inner.for.end:
2134 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2135 // CHECK7:       omp.loop.exit:
2136 // CHECK7-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2137 // CHECK7-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
2138 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP20]])
2139 // CHECK7-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2140 // CHECK7-NEXT:    [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
2141 // CHECK7-NEXT:    br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
2142 // CHECK7:       .omp.lastprivate.then:
2143 // CHECK7-NEXT:    [[TMP23:%.*]] = load i32, ptr [[T_VAR2]], align 4
2144 // CHECK7-NEXT:    store i32 [[TMP23]], ptr [[T_VAR_ADDR]], align 4
2145 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false)
2146 // CHECK7-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0
2147 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2
2148 // CHECK7-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP24]]
2149 // CHECK7-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2150 // CHECK7:       omp.arraycpy.body:
2151 // CHECK7-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2152 // CHECK7-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2153 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)
2154 // CHECK7-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2155 // CHECK7-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2156 // CHECK7-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP24]]
2157 // CHECK7-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]]
2158 // CHECK7:       omp.arraycpy.done12:
2159 // CHECK7-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[_TMP6]], align 4
2160 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP25]], i32 4, i1 false)
2161 // CHECK7-NEXT:    [[TMP26:%.*]] = load i32, ptr [[SVAR7]], align 4
2162 // CHECK7-NEXT:    store i32 [[TMP26]], ptr [[SVAR_ADDR]], align 4
2163 // CHECK7-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
2164 // CHECK7:       .omp.lastprivate.done:
2165 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
2166 // CHECK7-NEXT:    [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0
2167 // CHECK7-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2
2168 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2169 // CHECK7:       arraydestroy.body:
2170 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2171 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2172 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2173 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
2174 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
2175 // CHECK7:       arraydestroy.done14:
2176 // CHECK7-NEXT:    ret void
2177 //
2178 //
2179 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2180 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2181 // CHECK7-NEXT:  entry:
2182 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2183 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2184 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2185 // CHECK7-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2186 // CHECK7-NEXT:    ret void
2187 //
2188 //
2189 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2190 // CHECK7-SAME: () #[[ATTR1]] comdat {
2191 // CHECK7-NEXT:  entry:
2192 // CHECK7-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2193 // CHECK7-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2194 // CHECK7-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2195 // CHECK7-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2196 // CHECK7-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2197 // CHECK7-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
2198 // CHECK7-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
2199 // CHECK7-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2200 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
2201 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
2202 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
2203 // CHECK7-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2204 // CHECK7-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2205 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
2206 // CHECK7-NEXT:    store i32 0, ptr [[T_VAR]], align 4
2207 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
2208 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)
2209 // CHECK7-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1
2210 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
2211 // CHECK7-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
2212 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4
2213 // CHECK7-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 4
2214 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
2215 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
2216 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
2217 // CHECK7-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
2218 // CHECK7-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2219 // CHECK7-NEXT:    store ptr [[VEC]], ptr [[TMP4]], align 4
2220 // CHECK7-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2221 // CHECK7-NEXT:    store ptr [[VEC]], ptr [[TMP5]], align 4
2222 // CHECK7-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2223 // CHECK7-NEXT:    store ptr null, ptr [[TMP6]], align 4
2224 // CHECK7-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2225 // CHECK7-NEXT:    store i32 [[TMP2]], ptr [[TMP7]], align 4
2226 // CHECK7-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2227 // CHECK7-NEXT:    store i32 [[TMP2]], ptr [[TMP8]], align 4
2228 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2229 // CHECK7-NEXT:    store ptr null, ptr [[TMP9]], align 4
2230 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2231 // CHECK7-NEXT:    store ptr [[S_ARR]], ptr [[TMP10]], align 4
2232 // CHECK7-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2233 // CHECK7-NEXT:    store ptr [[S_ARR]], ptr [[TMP11]], align 4
2234 // CHECK7-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2235 // CHECK7-NEXT:    store ptr null, ptr [[TMP12]], align 4
2236 // CHECK7-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2237 // CHECK7-NEXT:    store ptr [[TMP3]], ptr [[TMP13]], align 4
2238 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2239 // CHECK7-NEXT:    store ptr [[TMP3]], ptr [[TMP14]], align 4
2240 // CHECK7-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2241 // CHECK7-NEXT:    store ptr null, ptr [[TMP15]], align 4
2242 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2243 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2244 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
2245 // CHECK7-NEXT:    store i32 3, ptr [[TMP18]], align 4
2246 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
2247 // CHECK7-NEXT:    store i32 4, ptr [[TMP19]], align 4
2248 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
2249 // CHECK7-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 4
2250 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
2251 // CHECK7-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 4
2252 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
2253 // CHECK7-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP22]], align 4
2254 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
2255 // CHECK7-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP23]], align 4
2256 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
2257 // CHECK7-NEXT:    store ptr null, ptr [[TMP24]], align 4
2258 // CHECK7-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
2259 // CHECK7-NEXT:    store ptr null, ptr [[TMP25]], align 4
2260 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
2261 // CHECK7-NEXT:    store i64 2, ptr [[TMP26]], align 8
2262 // CHECK7-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
2263 // CHECK7-NEXT:    store i64 0, ptr [[TMP27]], align 8
2264 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
2265 // CHECK7-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4
2266 // CHECK7-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
2267 // CHECK7-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4
2268 // CHECK7-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
2269 // CHECK7-NEXT:    store i32 0, ptr [[TMP30]], align 4
2270 // CHECK7-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.region_id, ptr [[KERNEL_ARGS]])
2271 // CHECK7-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
2272 // CHECK7-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2273 // CHECK7:       omp_offload.failed:
2274 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50(ptr [[VEC]], i32 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]]
2275 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2276 // CHECK7:       omp_offload.cont:
2277 // CHECK7-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2278 // CHECK7-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2279 // CHECK7-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
2280 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2281 // CHECK7:       arraydestroy.body:
2282 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2283 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2284 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2285 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2286 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
2287 // CHECK7:       arraydestroy.done2:
2288 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
2289 // CHECK7-NEXT:    [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4
2290 // CHECK7-NEXT:    ret i32 [[TMP34]]
2291 //
2292 //
2293 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2294 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2295 // CHECK7-NEXT:  entry:
2296 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2297 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2298 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2299 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2300 // CHECK7-NEXT:    store float 0.000000e+00, ptr [[F]], align 4
2301 // CHECK7-NEXT:    ret void
2302 //
2303 //
2304 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2305 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2306 // CHECK7-NEXT:  entry:
2307 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2308 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2309 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2310 // CHECK7-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2311 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2312 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2313 // CHECK7-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2314 // CHECK7-NEXT:    store float [[TMP0]], ptr [[F]], align 4
2315 // CHECK7-NEXT:    ret void
2316 //
2317 //
2318 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2319 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2320 // CHECK7-NEXT:  entry:
2321 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2322 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2323 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2324 // CHECK7-NEXT:    ret void
2325 //
2326 //
2327 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2328 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2329 // CHECK7-NEXT:  entry:
2330 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2331 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2332 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2333 // CHECK7-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2334 // CHECK7-NEXT:    ret void
2335 //
2336 //
2337 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2338 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2339 // CHECK7-NEXT:  entry:
2340 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2341 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2342 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2343 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2344 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2345 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2346 // CHECK7-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
2347 // CHECK7-NEXT:    ret void
2348 //
2349 //
2350 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50
2351 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
2352 // CHECK7-NEXT:  entry:
2353 // CHECK7-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
2354 // CHECK7-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2355 // CHECK7-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
2356 // CHECK7-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
2357 // CHECK7-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
2358 // CHECK7-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2359 // CHECK7-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
2360 // CHECK7-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
2361 // CHECK7-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
2362 // CHECK7-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
2363 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
2364 // CHECK7-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
2365 // CHECK7-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
2366 // CHECK7-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 4
2367 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
2368 // CHECK7-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
2369 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
2370 // CHECK7-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
2371 // CHECK7-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])
2372 // CHECK7-NEXT:    ret void
2373 //
2374 //
2375 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined
2376 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
2377 // CHECK7-NEXT:  entry:
2378 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2379 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2380 // CHECK7-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
2381 // CHECK7-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2382 // CHECK7-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
2383 // CHECK7-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
2384 // CHECK7-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
2385 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2386 // CHECK7-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2387 // CHECK7-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2388 // CHECK7-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2389 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2390 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2391 // CHECK7-NEXT:    [[T_VAR2:%.*]] = alloca i32, align 4
2392 // CHECK7-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 4
2393 // CHECK7-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
2394 // CHECK7-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2395 // CHECK7-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 4
2396 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
2397 // CHECK7-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2398 // CHECK7-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2399 // CHECK7-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2400 // CHECK7-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
2401 // CHECK7-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
2402 // CHECK7-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
2403 // CHECK7-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
2404 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
2405 // CHECK7-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
2406 // CHECK7-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
2407 // CHECK7-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 4
2408 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2409 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
2410 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2411 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2412 // CHECK7-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
2413 // CHECK7-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
2414 // CHECK7-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
2415 // CHECK7:       arrayctor.loop:
2416 // CHECK7-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2417 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2418 // CHECK7-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1
2419 // CHECK7-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2420 // CHECK7-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2421 // CHECK7:       arrayctor.cont:
2422 // CHECK7-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
2423 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
2424 // CHECK7-NEXT:    store ptr [[VAR5]], ptr [[_TMP6]], align 4
2425 // CHECK7-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2426 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
2427 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2428 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2429 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
2430 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2431 // CHECK7:       cond.true:
2432 // CHECK7-NEXT:    br label [[COND_END:%.*]]
2433 // CHECK7:       cond.false:
2434 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2435 // CHECK7-NEXT:    br label [[COND_END]]
2436 // CHECK7:       cond.end:
2437 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
2438 // CHECK7-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2439 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2440 // CHECK7-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
2441 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2442 // CHECK7:       omp.inner.for.cond:
2443 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2444 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2445 // CHECK7-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
2446 // CHECK7-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2447 // CHECK7:       omp.inner.for.cond.cleanup:
2448 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2449 // CHECK7:       omp.inner.for.body:
2450 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2451 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2452 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, ptr [[T_VAR2]], align 4
2453 // CHECK7-NEXT:    store i32 [[TMP13]], ptr [[T_VAR_CASTED]], align 4
2454 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
2455 // CHECK7-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4
2456 // CHECK7-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined.omp_outlined, i32 [[TMP11]], i32 [[TMP12]], ptr [[VEC3]], i32 [[TMP14]], ptr [[S_ARR4]], ptr [[TMP15]])
2457 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2458 // CHECK7:       omp.inner.for.inc:
2459 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2460 // CHECK7-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2461 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
2462 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
2463 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]]
2464 // CHECK7:       omp.inner.for.end:
2465 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2466 // CHECK7:       omp.loop.exit:
2467 // CHECK7-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2468 // CHECK7-NEXT:    [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
2469 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])
2470 // CHECK7-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2471 // CHECK7-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
2472 // CHECK7-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
2473 // CHECK7:       .omp.lastprivate.then:
2474 // CHECK7-NEXT:    [[TMP22:%.*]] = load i32, ptr [[T_VAR2]], align 4
2475 // CHECK7-NEXT:    store i32 [[TMP22]], ptr [[T_VAR_ADDR]], align 4
2476 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false)
2477 // CHECK7-NEXT:    [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0
2478 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i32 2
2479 // CHECK7-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP23]]
2480 // CHECK7-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2481 // CHECK7:       omp.arraycpy.body:
2482 // CHECK7-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2483 // CHECK7-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN8]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2484 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)
2485 // CHECK7-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2486 // CHECK7-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2487 // CHECK7-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP23]]
2488 // CHECK7-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]]
2489 // CHECK7:       omp.arraycpy.done9:
2490 // CHECK7-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[_TMP6]], align 4
2491 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP3]], ptr align 4 [[TMP24]], i32 4, i1 false)
2492 // CHECK7-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
2493 // CHECK7:       .omp.lastprivate.done:
2494 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
2495 // CHECK7-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
2496 // CHECK7-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2
2497 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2498 // CHECK7:       arraydestroy.body:
2499 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2500 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2501 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2502 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
2503 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
2504 // CHECK7:       arraydestroy.done11:
2505 // CHECK7-NEXT:    ret void
2506 //
2507 //
2508 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined.omp_outlined
2509 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
2510 // CHECK7-NEXT:  entry:
2511 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2512 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2513 // CHECK7-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2514 // CHECK7-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2515 // CHECK7-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
2516 // CHECK7-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2517 // CHECK7-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
2518 // CHECK7-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
2519 // CHECK7-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
2520 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2521 // CHECK7-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2522 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2523 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2524 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2525 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2526 // CHECK7-NEXT:    [[T_VAR2:%.*]] = alloca i32, align 4
2527 // CHECK7-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 4
2528 // CHECK7-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
2529 // CHECK7-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2530 // CHECK7-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 4
2531 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
2532 // CHECK7-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2533 // CHECK7-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2534 // CHECK7-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2535 // CHECK7-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2536 // CHECK7-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
2537 // CHECK7-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
2538 // CHECK7-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
2539 // CHECK7-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
2540 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
2541 // CHECK7-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
2542 // CHECK7-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
2543 // CHECK7-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 4
2544 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2545 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2546 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2547 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2548 // CHECK7-NEXT:    store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4
2549 // CHECK7-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
2550 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2551 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2552 // CHECK7-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
2553 // CHECK7-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
2554 // CHECK7-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
2555 // CHECK7:       arrayctor.loop:
2556 // CHECK7-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2557 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2558 // CHECK7-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1
2559 // CHECK7-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2560 // CHECK7-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2561 // CHECK7:       arrayctor.cont:
2562 // CHECK7-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
2563 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
2564 // CHECK7-NEXT:    store ptr [[VAR5]], ptr [[_TMP6]], align 4
2565 // CHECK7-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2566 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
2567 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2568 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2569 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
2570 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2571 // CHECK7:       cond.true:
2572 // CHECK7-NEXT:    br label [[COND_END:%.*]]
2573 // CHECK7:       cond.false:
2574 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2575 // CHECK7-NEXT:    br label [[COND_END]]
2576 // CHECK7:       cond.end:
2577 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
2578 // CHECK7-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2579 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2580 // CHECK7-NEXT:    store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4
2581 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2582 // CHECK7:       omp.inner.for.cond:
2583 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2584 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2585 // CHECK7-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
2586 // CHECK7-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2587 // CHECK7:       omp.inner.for.cond.cleanup:
2588 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2589 // CHECK7:       omp.inner.for.body:
2590 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2591 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
2592 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2593 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
2594 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4
2595 // CHECK7-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4
2596 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP15]]
2597 // CHECK7-NEXT:    store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4
2598 // CHECK7-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4
2599 // CHECK7-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4
2600 // CHECK7-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP17]]
2601 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP16]], i32 4, i1 false)
2602 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2603 // CHECK7:       omp.body.continue:
2604 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2605 // CHECK7:       omp.inner.for.inc:
2606 // CHECK7-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2607 // CHECK7-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP18]], 1
2608 // CHECK7-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
2609 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]]
2610 // CHECK7:       omp.inner.for.end:
2611 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2612 // CHECK7:       omp.loop.exit:
2613 // CHECK7-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2614 // CHECK7-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
2615 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP20]])
2616 // CHECK7-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2617 // CHECK7-NEXT:    [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
2618 // CHECK7-NEXT:    br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
2619 // CHECK7:       .omp.lastprivate.then:
2620 // CHECK7-NEXT:    [[TMP23:%.*]] = load i32, ptr [[T_VAR2]], align 4
2621 // CHECK7-NEXT:    store i32 [[TMP23]], ptr [[T_VAR_ADDR]], align 4
2622 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false)
2623 // CHECK7-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0
2624 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2
2625 // CHECK7-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP24]]
2626 // CHECK7-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2627 // CHECK7:       omp.arraycpy.body:
2628 // CHECK7-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2629 // CHECK7-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2630 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)
2631 // CHECK7-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2632 // CHECK7-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2633 // CHECK7-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP24]]
2634 // CHECK7-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]]
2635 // CHECK7:       omp.arraycpy.done11:
2636 // CHECK7-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[_TMP6]], align 4
2637 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP25]], i32 4, i1 false)
2638 // CHECK7-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
2639 // CHECK7:       .omp.lastprivate.done:
2640 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
2641 // CHECK7-NEXT:    [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
2642 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2
2643 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2644 // CHECK7:       arraydestroy.body:
2645 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2646 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2647 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2648 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
2649 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
2650 // CHECK7:       arraydestroy.done13:
2651 // CHECK7-NEXT:    ret void
2652 //
2653 //
2654 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2655 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2656 // CHECK7-NEXT:  entry:
2657 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2658 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2659 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2660 // CHECK7-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2661 // CHECK7-NEXT:    ret void
2662 //
2663 //
2664 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2665 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2666 // CHECK7-NEXT:  entry:
2667 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2668 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2669 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2670 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2671 // CHECK7-NEXT:    store i32 0, ptr [[F]], align 4
2672 // CHECK7-NEXT:    ret void
2673 //
2674 //
2675 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2676 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2677 // CHECK7-NEXT:  entry:
2678 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2679 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2680 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2681 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2682 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2683 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2684 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2685 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
2686 // CHECK7-NEXT:    ret void
2687 //
2688 //
2689 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2690 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2691 // CHECK7-NEXT:  entry:
2692 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2693 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2694 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2695 // CHECK7-NEXT:    ret void
2696 //