clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1
   3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
   4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1
   5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK3
   6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
   7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK3
   8
   9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK5
  10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK5
  12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK7
  13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK7
  15
  16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK9
  17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK9
  19
  20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK11
  21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK11
  23
  24 // expected-no-diagnostics
  25 #ifndef HEADER
  26 #define HEADER
  27
  28 struct St {
  29   int a, b;
  30   St() : a(0), b(0) {}
  31   St(const St &st) : a(st.a + st.b), b(0) {}
  32   ~St() {}
  33 };
  34
  35 volatile int g = 1212;
  36 volatile int &g1 = g;
  37
  38 template <class T>
  39 struct S {
  40   T f;
  41   S(T a) : f(a + g) {}
  42   S() : f(g) {}
  43   S(const S &s, St t = St()) : f(s.f + t.a) {}
  44   operator T() { return T(); }
  45   ~S() {}
  46 };
  47
  48
  49 template <typename T>
  50 T tmain() {
  51   S<T> test;
  52   T t_var = T();
  53   T vec[] = {1, 2};
  54   S<T> s_arr[] = {1, 2};
  55   S<T> &var = test;
  56 #pragma omp target
  57 #pragma omp teams distribute simd private(t_var, vec, s_arr, var)
  58   for (int i = 0; i < 2; ++i) {
  59     vec[i] = t_var;
  60     s_arr[i] = var;
  61   }
  62   return T();
  63 }
  64
  65 S<float> test;
  66 int t_var = 333;
  67 int vec[] = {1, 2};
  68 S<float> s_arr[] = {1, 2};
  69 S<float> var(3);
  70
  71 int main() {
  72   static int sivar;
  73 #ifdef LAMBDA
  74   [&]() {
  75 #pragma omp target
  76 #pragma omp teams distribute simd private(g, g1, sivar)
  77   for (int i = 0; i < 2; ++i) {
  78
  79     // Skip global, bound tid and loop vars
  80
  81     g = 1;
  82     g1 = 1;
  83     sivar = 2;
  84     [&]() {
  85       g = 2;
  86       g1 = 2;
  87       sivar = 4;
  88
  89     }();
  90   }
  91   }();
  92   return 0;
  93 #else
  94 #pragma omp target
  95 #pragma omp teams distribute simd private(t_var, vec, s_arr, var, sivar)
  96   for (int i = 0; i < 2; ++i) {
  97     vec[i] = t_var;
  98     s_arr[i] = var;
  99     sivar += i;
 100   }
 101   return tmain<int>();
 102 #endif
 103 }
 104
 105
 106
 107 // Skip global, bound tid and loop vars
 108
 109 // private(s_arr)
 110
 111 // private(var)
 112
 113
 114
 115
 116
 117 // Skip global, bound tid and loop vars
 118
 119 // private(s_arr)
 120
 121
 122 // private(var)
 123
 124
 125 #endif
 126 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
 127 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
 128 // CHECK1-NEXT:  entry:
 129 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
 130 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
 131 // CHECK1-NEXT:    ret void
 132 //
 133 //
 134 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 135 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
 136 // CHECK1-NEXT:  entry:
 137 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 138 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 139 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 140 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 141 // CHECK1-NEXT:    ret void
 142 //
 143 //
 144 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
 145 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 146 // CHECK1-NEXT:  entry:
 147 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 148 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 149 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 150 // CHECK1-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
 151 // CHECK1-NEXT:    ret void
 152 //
 153 //
 154 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
 155 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 156 // CHECK1-NEXT:  entry:
 157 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 158 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 159 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 160 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 161 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
 162 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
 163 // CHECK1-NEXT:    store float [[CONV]], ptr [[F]], align 4
 164 // CHECK1-NEXT:    ret void
 165 //
 166 //
 167 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
 168 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 169 // CHECK1-NEXT:  entry:
 170 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 171 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 172 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 173 // CHECK1-NEXT:    ret void
 174 //
 175 //
 176 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
 177 // CHECK1-SAME: () #[[ATTR0]] {
 178 // CHECK1-NEXT:  entry:
 179 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
 180 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
 181 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
 182 // CHECK1-NEXT:    ret void
 183 //
 184 //
 185 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 186 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 187 // CHECK1-NEXT:  entry:
 188 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 189 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 190 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 191 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 192 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 193 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 194 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 195 // CHECK1-NEXT:    ret void
 196 //
 197 //
 198 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
 199 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
 200 // CHECK1-NEXT:  entry:
 201 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 202 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 203 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 204 // CHECK1:       arraydestroy.body:
 205 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 206 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 207 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 208 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
 209 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 210 // CHECK1:       arraydestroy.done1:
 211 // CHECK1-NEXT:    ret void
 212 //
 213 //
 214 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
 215 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 216 // CHECK1-NEXT:  entry:
 217 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 218 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 219 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 220 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 221 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 222 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 223 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 224 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
 225 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
 226 // CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
 227 // CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4
 228 // CHECK1-NEXT:    ret void
 229 //
 230 //
 231 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
 232 // CHECK1-SAME: () #[[ATTR0]] {
 233 // CHECK1-NEXT:  entry:
 234 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
 235 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
 236 // CHECK1-NEXT:    ret void
 237 //
 238 //
 239 // CHECK1-LABEL: define {{[^@]+}}@main
 240 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
 241 // CHECK1-NEXT:  entry:
 242 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 243 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 244 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 245 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 246 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 247 // CHECK1-NEXT:    store i32 3, ptr [[TMP0]], align 4
 248 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 249 // CHECK1-NEXT:    store i32 0, ptr [[TMP1]], align 4
 250 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 251 // CHECK1-NEXT:    store ptr null, ptr [[TMP2]], align 8
 252 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 253 // CHECK1-NEXT:    store ptr null, ptr [[TMP3]], align 8
 254 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 255 // CHECK1-NEXT:    store ptr null, ptr [[TMP4]], align 8
 256 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 257 // CHECK1-NEXT:    store ptr null, ptr [[TMP5]], align 8
 258 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 259 // CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8
 260 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 261 // CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 8
 262 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 263 // CHECK1-NEXT:    store i64 2, ptr [[TMP8]], align 8
 264 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 265 // CHECK1-NEXT:    store i64 0, ptr [[TMP9]], align 8
 266 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 267 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
 268 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 269 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4
 270 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 271 // CHECK1-NEXT:    store i32 0, ptr [[TMP12]], align 4
 272 // CHECK1-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, ptr [[KERNEL_ARGS]])
 273 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
 274 // CHECK1-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 275 // CHECK1:       omp_offload.failed:
 276 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]]
 277 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 278 // CHECK1:       omp_offload.cont:
 279 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
 280 // CHECK1-NEXT:    ret i32 [[CALL]]
 281 //
 282 //
 283 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94
 284 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
 285 // CHECK1-NEXT:  entry:
 286 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined)
 287 // CHECK1-NEXT:    ret void
 288 //
 289 //
 290 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined
 291 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
 292 // CHECK1-NEXT:  entry:
 293 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 294 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 295 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 296 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 297 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 298 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 299 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 300 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 301 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 302 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 303 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
 304 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 305 // CHECK1-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
 306 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 307 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 308 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 309 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 310 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 311 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 312 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 313 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 314 // CHECK1-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
 315 // CHECK1-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 316 // CHECK1:       arrayctor.loop:
 317 // CHECK1-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 318 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
 319 // CHECK1-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
 320 // CHECK1-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 321 // CHECK1-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 322 // CHECK1:       arrayctor.cont:
 323 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
 324 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 325 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 326 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 327 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 328 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
 329 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 330 // CHECK1:       cond.true:
 331 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 332 // CHECK1:       cond.false:
 333 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 334 // CHECK1-NEXT:    br label [[COND_END]]
 335 // CHECK1:       cond.end:
 336 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 337 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 338 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 339 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 340 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 341 // CHECK1:       omp.inner.for.cond:
 342 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
 343 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]]
 344 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 345 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 346 // CHECK1:       omp.inner.for.cond.cleanup:
 347 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 348 // CHECK1:       omp.inner.for.body:
 349 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 350 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
 351 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 352 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
 353 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP5]]
 354 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
 355 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
 356 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
 357 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]]
 358 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
 359 // CHECK1-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64
 360 // CHECK1-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]]
 361 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP5]]
 362 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
 363 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP5]]
 364 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
 365 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP5]]
 366 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 367 // CHECK1:       omp.body.continue:
 368 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 369 // CHECK1:       omp.inner.for.inc:
 370 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 371 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1
 372 // CHECK1-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 373 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
 374 // CHECK1:       omp.inner.for.end:
 375 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 376 // CHECK1:       omp.loop.exit:
 377 // CHECK1-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 378 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
 379 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]])
 380 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 381 // CHECK1-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
 382 // CHECK1-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 383 // CHECK1:       .omp.final.then:
 384 // CHECK1-NEXT:    store i32 2, ptr [[I]], align 4
 385 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 386 // CHECK1:       .omp.final.done:
 387 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
 388 // CHECK1-NEXT:    [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 389 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2
 390 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 391 // CHECK1:       arraydestroy.body:
 392 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 393 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 394 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 395 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
 396 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
 397 // CHECK1:       arraydestroy.done7:
 398 // CHECK1-NEXT:    ret void
 399 //
 400 //
 401 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
 402 // CHECK1-SAME: () #[[ATTR1]] comdat {
 403 // CHECK1-NEXT:  entry:
 404 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 405 // CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 406 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 407 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 408 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 409 // CHECK1-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
 410 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 411 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 412 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 413 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 414 // CHECK1-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 415 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
 416 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)
 417 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1
 418 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
 419 // CHECK1-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
 420 // CHECK1-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
 421 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 422 // CHECK1-NEXT:    store i32 3, ptr [[TMP0]], align 4
 423 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 424 // CHECK1-NEXT:    store i32 0, ptr [[TMP1]], align 4
 425 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 426 // CHECK1-NEXT:    store ptr null, ptr [[TMP2]], align 8
 427 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 428 // CHECK1-NEXT:    store ptr null, ptr [[TMP3]], align 8
 429 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 430 // CHECK1-NEXT:    store ptr null, ptr [[TMP4]], align 8
 431 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 432 // CHECK1-NEXT:    store ptr null, ptr [[TMP5]], align 8
 433 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 434 // CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8
 435 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 436 // CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 8
 437 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 438 // CHECK1-NEXT:    store i64 2, ptr [[TMP8]], align 8
 439 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 440 // CHECK1-NEXT:    store i64 0, ptr [[TMP9]], align 8
 441 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 442 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
 443 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 444 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4
 445 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 446 // CHECK1-NEXT:    store i32 0, ptr [[TMP12]], align 4
 447 // CHECK1-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])
 448 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
 449 // CHECK1-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 450 // CHECK1:       omp_offload.failed:
 451 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
 452 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 453 // CHECK1:       omp_offload.cont:
 454 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 455 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 456 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 457 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 458 // CHECK1:       arraydestroy.body:
 459 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 460 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 461 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 462 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
 463 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
 464 // CHECK1:       arraydestroy.done2:
 465 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
 466 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
 467 // CHECK1-NEXT:    ret i32 [[TMP16]]
 468 //
 469 //
 470 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
 471 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 472 // CHECK1-NEXT:  entry:
 473 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 474 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 475 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 476 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 477 // CHECK1-NEXT:    ret void
 478 //
 479 //
 480 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
 481 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 482 // CHECK1-NEXT:  entry:
 483 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 484 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 485 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 486 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 487 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 488 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 489 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
 490 // CHECK1-NEXT:    ret void
 491 //
 492 //
 493 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
 494 // CHECK1-SAME: () #[[ATTR4]] {
 495 // CHECK1-NEXT:  entry:
 496 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined)
 497 // CHECK1-NEXT:    ret void
 498 //
 499 //
 500 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined
 501 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
 502 // CHECK1-NEXT:  entry:
 503 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 504 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 505 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 506 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 507 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 508 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 509 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 510 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 511 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 512 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 513 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 514 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 515 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 516 // CHECK1-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
 517 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 518 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 519 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 520 // CHECK1-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
 521 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 522 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 523 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 524 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 525 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 526 // CHECK1-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 527 // CHECK1-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 528 // CHECK1:       arrayctor.loop:
 529 // CHECK1-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 530 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
 531 // CHECK1-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
 532 // CHECK1-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 533 // CHECK1-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 534 // CHECK1:       arrayctor.cont:
 535 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
 536 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[_TMP2]], align 8
 537 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 538 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 539 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 540 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 541 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
 542 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 543 // CHECK1:       cond.true:
 544 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 545 // CHECK1:       cond.false:
 546 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 547 // CHECK1-NEXT:    br label [[COND_END]]
 548 // CHECK1:       cond.end:
 549 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 550 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 551 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 552 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 553 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 554 // CHECK1:       omp.inner.for.cond:
 555 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]
 556 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]
 557 // CHECK1-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 558 // CHECK1-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 559 // CHECK1:       omp.inner.for.cond.cleanup:
 560 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 561 // CHECK1:       omp.inner.for.body:
 562 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
 563 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
 564 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 565 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
 566 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP11]]
 567 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
 568 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
 569 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
 570 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]]
 571 // CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP11]]
 572 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
 573 // CHECK1-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
 574 // CHECK1-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]
 575 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]]
 576 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 577 // CHECK1:       omp.body.continue:
 578 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 579 // CHECK1:       omp.inner.for.inc:
 580 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
 581 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
 582 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
 583 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
 584 // CHECK1:       omp.inner.for.end:
 585 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 586 // CHECK1:       omp.loop.exit:
 587 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 588 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
 589 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])
 590 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 591 // CHECK1-NEXT:    [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
 592 // CHECK1-NEXT:    br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 593 // CHECK1:       .omp.final.then:
 594 // CHECK1-NEXT:    store i32 2, ptr [[I]], align 4
 595 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 596 // CHECK1:       .omp.final.done:
 597 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
 598 // CHECK1-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 599 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2
 600 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 601 // CHECK1:       arraydestroy.body:
 602 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 603 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 604 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 605 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
 606 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
 607 // CHECK1:       arraydestroy.done8:
 608 // CHECK1-NEXT:    ret void
 609 //
 610 //
 611 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
 612 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 613 // CHECK1-NEXT:  entry:
 614 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 615 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 616 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 617 // CHECK1-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
 618 // CHECK1-NEXT:    ret void
 619 //
 620 //
 621 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
 622 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 623 // CHECK1-NEXT:  entry:
 624 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 625 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 626 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 627 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 628 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
 629 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
 630 // CHECK1-NEXT:    ret void
 631 //
 632 //
 633 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
 634 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 635 // CHECK1-NEXT:  entry:
 636 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 637 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 638 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 639 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 640 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 641 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 642 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 643 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
 644 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
 645 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
 646 // CHECK1-NEXT:    ret void
 647 //
 648 //
 649 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
 650 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 651 // CHECK1-NEXT:  entry:
 652 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 653 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 654 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 655 // CHECK1-NEXT:    ret void
 656 //
 657 //
 658 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
 659 // CHECK1-SAME: () #[[ATTR0]] {
 660 // CHECK1-NEXT:  entry:
 661 // CHECK1-NEXT:    call void @__cxx_global_var_init()
 662 // CHECK1-NEXT:    call void @__cxx_global_var_init.1()
 663 // CHECK1-NEXT:    call void @__cxx_global_var_init.2()
 664 // CHECK1-NEXT:    ret void
 665 //
 666 //
 667 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
 668 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
 669 // CHECK3-NEXT:  entry:
 670 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
 671 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
 672 // CHECK3-NEXT:    ret void
 673 //
 674 //
 675 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 676 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
 677 // CHECK3-NEXT:  entry:
 678 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 679 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 680 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 681 // CHECK3-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 682 // CHECK3-NEXT:    ret void
 683 //
 684 //
 685 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
 686 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 687 // CHECK3-NEXT:  entry:
 688 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 689 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 690 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 691 // CHECK3-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
 692 // CHECK3-NEXT:    ret void
 693 //
 694 //
 695 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
 696 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 697 // CHECK3-NEXT:  entry:
 698 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 699 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 700 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 701 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 702 // CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
 703 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
 704 // CHECK3-NEXT:    store float [[CONV]], ptr [[F]], align 4
 705 // CHECK3-NEXT:    ret void
 706 //
 707 //
 708 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
 709 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 710 // CHECK3-NEXT:  entry:
 711 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 712 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 713 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 714 // CHECK3-NEXT:    ret void
 715 //
 716 //
 717 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
 718 // CHECK3-SAME: () #[[ATTR0]] {
 719 // CHECK3-NEXT:  entry:
 720 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
 721 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)
 722 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
 723 // CHECK3-NEXT:    ret void
 724 //
 725 //
 726 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 727 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 728 // CHECK3-NEXT:  entry:
 729 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 730 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 731 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 732 // CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 733 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 734 // CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 735 // CHECK3-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 736 // CHECK3-NEXT:    ret void
 737 //
 738 //
 739 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
 740 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
 741 // CHECK3-NEXT:  entry:
 742 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 4
 743 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 4
 744 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 745 // CHECK3:       arraydestroy.body:
 746 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 747 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
 748 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 749 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
 750 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 751 // CHECK3:       arraydestroy.done1:
 752 // CHECK3-NEXT:    ret void
 753 //
 754 //
 755 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
 756 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 757 // CHECK3-NEXT:  entry:
 758 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 759 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 760 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 761 // CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 762 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 763 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 764 // CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 765 // CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
 766 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
 767 // CHECK3-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
 768 // CHECK3-NEXT:    store float [[ADD]], ptr [[F]], align 4
 769 // CHECK3-NEXT:    ret void
 770 //
 771 //
 772 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
 773 // CHECK3-SAME: () #[[ATTR0]] {
 774 // CHECK3-NEXT:  entry:
 775 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
 776 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
 777 // CHECK3-NEXT:    ret void
 778 //
 779 //
 780 // CHECK3-LABEL: define {{[^@]+}}@main
 781 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
 782 // CHECK3-NEXT:  entry:
 783 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 784 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 785 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 786 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 787 // CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 788 // CHECK3-NEXT:    store i32 3, ptr [[TMP0]], align 4
 789 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 790 // CHECK3-NEXT:    store i32 0, ptr [[TMP1]], align 4
 791 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 792 // CHECK3-NEXT:    store ptr null, ptr [[TMP2]], align 4
 793 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 794 // CHECK3-NEXT:    store ptr null, ptr [[TMP3]], align 4
 795 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 796 // CHECK3-NEXT:    store ptr null, ptr [[TMP4]], align 4
 797 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 798 // CHECK3-NEXT:    store ptr null, ptr [[TMP5]], align 4
 799 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 800 // CHECK3-NEXT:    store ptr null, ptr [[TMP6]], align 4
 801 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 802 // CHECK3-NEXT:    store ptr null, ptr [[TMP7]], align 4
 803 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 804 // CHECK3-NEXT:    store i64 2, ptr [[TMP8]], align 8
 805 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 806 // CHECK3-NEXT:    store i64 0, ptr [[TMP9]], align 8
 807 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 808 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
 809 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 810 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4
 811 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 812 // CHECK3-NEXT:    store i32 0, ptr [[TMP12]], align 4
 813 // CHECK3-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, ptr [[KERNEL_ARGS]])
 814 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
 815 // CHECK3-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 816 // CHECK3:       omp_offload.failed:
 817 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]]
 818 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 819 // CHECK3:       omp_offload.cont:
 820 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
 821 // CHECK3-NEXT:    ret i32 [[CALL]]
 822 //
 823 //
 824 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94
 825 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
 826 // CHECK3-NEXT:  entry:
 827 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined)
 828 // CHECK3-NEXT:    ret void
 829 //
 830 //
 831 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined
 832 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
 833 // CHECK3-NEXT:  entry:
 834 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
 835 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
 836 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 837 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 838 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 839 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 840 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 841 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 842 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 843 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 844 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
 845 // CHECK3-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 846 // CHECK3-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
 847 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
 848 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
 849 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
 850 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 851 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 852 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 853 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 854 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 855 // CHECK3-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
 856 // CHECK3-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 857 // CHECK3:       arrayctor.loop:
 858 // CHECK3-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 859 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
 860 // CHECK3-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1
 861 // CHECK3-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 862 // CHECK3-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 863 // CHECK3:       arrayctor.cont:
 864 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
 865 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
 866 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 867 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 868 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 869 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
 870 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 871 // CHECK3:       cond.true:
 872 // CHECK3-NEXT:    br label [[COND_END:%.*]]
 873 // CHECK3:       cond.false:
 874 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 875 // CHECK3-NEXT:    br label [[COND_END]]
 876 // CHECK3:       cond.end:
 877 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 878 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 879 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 880 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 881 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 882 // CHECK3:       omp.inner.for.cond:
 883 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
 884 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
 885 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 886 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 887 // CHECK3:       omp.inner.for.cond.cleanup:
 888 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 889 // CHECK3:       omp.inner.for.body:
 890 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
 891 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
 892 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 893 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
 894 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]]
 895 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
 896 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]
 897 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]]
 898 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
 899 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]]
 900 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP6]]
 901 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
 902 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP6]]
 903 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
 904 // CHECK3-NEXT:    store i32 [[ADD3]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP6]]
 905 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 906 // CHECK3:       omp.body.continue:
 907 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 908 // CHECK3:       omp.inner.for.inc:
 909 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
 910 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
 911 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
 912 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
 913 // CHECK3:       omp.inner.for.end:
 914 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 915 // CHECK3:       omp.loop.exit:
 916 // CHECK3-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
 917 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
 918 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]])
 919 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 920 // CHECK3-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
 921 // CHECK3-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 922 // CHECK3:       .omp.final.then:
 923 // CHECK3-NEXT:    store i32 2, ptr [[I]], align 4
 924 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 925 // CHECK3:       .omp.final.done:
 926 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
 927 // CHECK3-NEXT:    [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 928 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2
 929 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 930 // CHECK3:       arraydestroy.body:
 931 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 932 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
 933 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 934 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
 935 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
 936 // CHECK3:       arraydestroy.done6:
 937 // CHECK3-NEXT:    ret void
 938 //
 939 //
 940 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
 941 // CHECK3-SAME: () #[[ATTR1]] comdat {
 942 // CHECK3-NEXT:  entry:
 943 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 944 // CHECK3-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 945 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 946 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 947 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 948 // CHECK3-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
 949 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 950 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
 951 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 952 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 953 // CHECK3-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 954 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
 955 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)
 956 // CHECK3-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1
 957 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
 958 // CHECK3-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
 959 // CHECK3-NEXT:    store ptr undef, ptr [[_TMP1]], align 4
 960 // CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 961 // CHECK3-NEXT:    store i32 3, ptr [[TMP0]], align 4
 962 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 963 // CHECK3-NEXT:    store i32 0, ptr [[TMP1]], align 4
 964 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 965 // CHECK3-NEXT:    store ptr null, ptr [[TMP2]], align 4
 966 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 967 // CHECK3-NEXT:    store ptr null, ptr [[TMP3]], align 4
 968 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 969 // CHECK3-NEXT:    store ptr null, ptr [[TMP4]], align 4
 970 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 971 // CHECK3-NEXT:    store ptr null, ptr [[TMP5]], align 4
 972 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 973 // CHECK3-NEXT:    store ptr null, ptr [[TMP6]], align 4
 974 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 975 // CHECK3-NEXT:    store ptr null, ptr [[TMP7]], align 4
 976 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 977 // CHECK3-NEXT:    store i64 2, ptr [[TMP8]], align 8
 978 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 979 // CHECK3-NEXT:    store i64 0, ptr [[TMP9]], align 8
 980 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 981 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
 982 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 983 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4
 984 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 985 // CHECK3-NEXT:    store i32 0, ptr [[TMP12]], align 4
 986 // CHECK3-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])
 987 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
 988 // CHECK3-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 989 // CHECK3:       omp_offload.failed:
 990 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
 991 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 992 // CHECK3:       omp_offload.cont:
 993 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 994 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 995 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
 996 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 997 // CHECK3:       arraydestroy.body:
 998 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 999 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1000 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1001 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1002 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1003 // CHECK3:       arraydestroy.done2:
1004 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1005 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
1006 // CHECK3-NEXT:    ret i32 [[TMP16]]
1007 //
1008 //
1009 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1010 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1011 // CHECK3-NEXT:  entry:
1012 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1013 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1014 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1015 // CHECK3-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1016 // CHECK3-NEXT:    ret void
1017 //
1018 //
1019 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1020 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1021 // CHECK3-NEXT:  entry:
1022 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1023 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1024 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1025 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1026 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1027 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1028 // CHECK3-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1029 // CHECK3-NEXT:    ret void
1030 //
1031 //
1032 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1033 // CHECK3-SAME: () #[[ATTR4]] {
1034 // CHECK3-NEXT:  entry:
1035 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined)
1036 // CHECK3-NEXT:    ret void
1037 //
1038 //
1039 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined
1040 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1041 // CHECK3-NEXT:  entry:
1042 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1043 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1044 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1045 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1046 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
1047 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1048 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1049 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1050 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1051 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1052 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1053 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1054 // CHECK3-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1055 // CHECK3-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 4
1056 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1057 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1058 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1059 // CHECK3-NEXT:    store ptr undef, ptr [[_TMP1]], align 4
1060 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1061 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1062 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1063 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1064 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1065 // CHECK3-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
1066 // CHECK3-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1067 // CHECK3:       arrayctor.loop:
1068 // CHECK3-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1069 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1070 // CHECK3-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1
1071 // CHECK3-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1072 // CHECK3-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1073 // CHECK3:       arrayctor.cont:
1074 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
1075 // CHECK3-NEXT:    store ptr [[VAR]], ptr [[_TMP2]], align 4
1076 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1077 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1078 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1079 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1080 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1081 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1082 // CHECK3:       cond.true:
1083 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1084 // CHECK3:       cond.false:
1085 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1086 // CHECK3-NEXT:    br label [[COND_END]]
1087 // CHECK3:       cond.end:
1088 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1089 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1090 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1091 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
1092 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1093 // CHECK3:       omp.inner.for.cond:
1094 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
1095 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]
1096 // CHECK3-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1097 // CHECK3-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1098 // CHECK3:       omp.inner.for.cond.cleanup:
1099 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1100 // CHECK3:       omp.inner.for.body:
1101 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1102 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1103 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1104 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
1105 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP12]]
1106 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
1107 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]
1108 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]]
1109 // CHECK3-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP12]]
1110 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
1111 // CHECK3-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]]
1112 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]]
1113 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1114 // CHECK3:       omp.body.continue:
1115 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1116 // CHECK3:       omp.inner.for.inc:
1117 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1118 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1
1119 // CHECK3-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1120 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
1121 // CHECK3:       omp.inner.for.end:
1122 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1123 // CHECK3:       omp.loop.exit:
1124 // CHECK3-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1125 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
1126 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])
1127 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1128 // CHECK3-NEXT:    [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
1129 // CHECK3-NEXT:    br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1130 // CHECK3:       .omp.final.then:
1131 // CHECK3-NEXT:    store i32 2, ptr [[I]], align 4
1132 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1133 // CHECK3:       .omp.final.done:
1134 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1135 // CHECK3-NEXT:    [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1136 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2
1137 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1138 // CHECK3:       arraydestroy.body:
1139 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1140 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1141 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1142 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
1143 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
1144 // CHECK3:       arraydestroy.done7:
1145 // CHECK3-NEXT:    ret void
1146 //
1147 //
1148 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1149 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1150 // CHECK3-NEXT:  entry:
1151 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1152 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1153 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1154 // CHECK3-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1155 // CHECK3-NEXT:    ret void
1156 //
1157 //
1158 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1159 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1160 // CHECK3-NEXT:  entry:
1161 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1162 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1163 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1164 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1165 // CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1166 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
1167 // CHECK3-NEXT:    ret void
1168 //
1169 //
1170 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1171 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1172 // CHECK3-NEXT:  entry:
1173 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1174 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1175 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1176 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1177 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1178 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1179 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1180 // CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1181 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1182 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
1183 // CHECK3-NEXT:    ret void
1184 //
1185 //
1186 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1187 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1188 // CHECK3-NEXT:  entry:
1189 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1190 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1191 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1192 // CHECK3-NEXT:    ret void
1193 //
1194 //
1195 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
1196 // CHECK3-SAME: () #[[ATTR0]] {
1197 // CHECK3-NEXT:  entry:
1198 // CHECK3-NEXT:    call void @__cxx_global_var_init()
1199 // CHECK3-NEXT:    call void @__cxx_global_var_init.1()
1200 // CHECK3-NEXT:    call void @__cxx_global_var_init.2()
1201 // CHECK3-NEXT:    ret void
1202 //
1203 //
1204 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init
1205 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
1206 // CHECK5-NEXT:  entry:
1207 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
1208 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
1209 // CHECK5-NEXT:    ret void
1210 //
1211 //
1212 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1213 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
1214 // CHECK5-NEXT:  entry:
1215 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1216 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1217 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1218 // CHECK5-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1219 // CHECK5-NEXT:    ret void
1220 //
1221 //
1222 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1223 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1224 // CHECK5-NEXT:  entry:
1225 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1226 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1227 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1228 // CHECK5-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1229 // CHECK5-NEXT:    ret void
1230 //
1231 //
1232 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1233 // CHECK5-SAME: () #[[ATTR0]] {
1234 // CHECK5-NEXT:  entry:
1235 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
1236 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
1237 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
1238 // CHECK5-NEXT:    ret void
1239 //
1240 //
1241 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1242 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1243 // CHECK5-NEXT:  entry:
1244 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1245 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1246 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1247 // CHECK5-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1248 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1249 // CHECK5-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1250 // CHECK5-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1251 // CHECK5-NEXT:    ret void
1252 //
1253 //
1254 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1255 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1256 // CHECK5-NEXT:  entry:
1257 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1258 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1259 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1260 // CHECK5:       arraydestroy.body:
1261 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1262 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1263 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1264 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
1265 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1266 // CHECK5:       arraydestroy.done1:
1267 // CHECK5-NEXT:    ret void
1268 //
1269 //
1270 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1271 // CHECK5-SAME: () #[[ATTR0]] {
1272 // CHECK5-NEXT:  entry:
1273 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1274 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
1275 // CHECK5-NEXT:    ret void
1276 //
1277 //
1278 // CHECK5-LABEL: define {{[^@]+}}@main
1279 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
1280 // CHECK5-NEXT:  entry:
1281 // CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1282 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1283 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1284 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1285 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1286 // CHECK5-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1287 // CHECK5-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1288 // CHECK5-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1289 // CHECK5-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1290 // CHECK5-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
1291 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
1292 // CHECK5-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1293 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1294 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1295 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1296 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
1297 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1298 // CHECK5-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
1299 // CHECK5-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1300 // CHECK5:       arrayctor.loop:
1301 // CHECK5-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1302 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1303 // CHECK5-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
1304 // CHECK5-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1305 // CHECK5-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1306 // CHECK5:       arrayctor.cont:
1307 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
1308 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1309 // CHECK5:       omp.inner.for.cond:
1310 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
1311 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
1312 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1313 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1314 // CHECK5:       omp.inner.for.cond.cleanup:
1315 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1316 // CHECK5:       omp.inner.for.body:
1317 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1318 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1319 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1320 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1321 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]]
1322 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1323 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
1324 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
1325 // CHECK5-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]]
1326 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1327 // CHECK5-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
1328 // CHECK5-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]]
1329 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]]
1330 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1331 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]
1332 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]
1333 // CHECK5-NEXT:    store i32 [[ADD3]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]
1334 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1335 // CHECK5:       omp.body.continue:
1336 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1337 // CHECK5:       omp.inner.for.inc:
1338 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1339 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
1340 // CHECK5-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1341 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
1342 // CHECK5:       omp.inner.for.end:
1343 // CHECK5-NEXT:    store i32 2, ptr [[I]], align 4
1344 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1345 // CHECK5-NEXT:    [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1346 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i64 2
1347 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1348 // CHECK5:       arraydestroy.body:
1349 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1350 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1351 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1352 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
1353 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
1354 // CHECK5:       arraydestroy.done6:
1355 // CHECK5-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
1356 // CHECK5-NEXT:    ret i32 [[CALL]]
1357 //
1358 //
1359 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1360 // CHECK5-SAME: () #[[ATTR1]] comdat {
1361 // CHECK5-NEXT:  entry:
1362 // CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1363 // CHECK5-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1364 // CHECK5-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1365 // CHECK5-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1366 // CHECK5-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1367 // CHECK5-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
1368 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1369 // CHECK5-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
1370 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1371 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1372 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1373 // CHECK5-NEXT:    [[T_VAR2:%.*]] = alloca i32, align 4
1374 // CHECK5-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 4
1375 // CHECK5-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
1376 // CHECK5-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
1377 // CHECK5-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 8
1378 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
1379 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1380 // CHECK5-NEXT:    store i32 0, ptr [[T_VAR]], align 4
1381 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
1382 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)
1383 // CHECK5-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1
1384 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
1385 // CHECK5-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
1386 // CHECK5-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
1387 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1388 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1389 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1390 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
1391 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1392 // CHECK5-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1393 // CHECK5-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1394 // CHECK5:       arrayctor.loop:
1395 // CHECK5-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1396 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1397 // CHECK5-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
1398 // CHECK5-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1399 // CHECK5-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1400 // CHECK5:       arrayctor.cont:
1401 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
1402 // CHECK5-NEXT:    store ptr [[VAR5]], ptr [[_TMP6]], align 8
1403 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1404 // CHECK5:       omp.inner.for.cond:
1405 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
1406 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
1407 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1408 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1409 // CHECK5:       omp.inner.for.cond.cleanup:
1410 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1411 // CHECK5:       omp.inner.for.body:
1412 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1413 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1414 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1415 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1416 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]]
1417 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1418 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
1419 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]]
1420 // CHECK5-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]]
1421 // CHECK5-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP6]]
1422 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1423 // CHECK5-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64
1424 // CHECK5-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]]
1425 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]]
1426 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1427 // CHECK5:       omp.body.continue:
1428 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1429 // CHECK5:       omp.inner.for.inc:
1430 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1431 // CHECK5-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1
1432 // CHECK5-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1433 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1434 // CHECK5:       omp.inner.for.end:
1435 // CHECK5-NEXT:    store i32 2, ptr [[I]], align 4
1436 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1437 // CHECK5-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1438 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2
1439 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1440 // CHECK5:       arraydestroy.body:
1441 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1442 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1443 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1444 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1445 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1446 // CHECK5:       arraydestroy.done11:
1447 // CHECK5-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1448 // CHECK5-NEXT:    [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1449 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2
1450 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY13:%.*]]
1451 // CHECK5:       arraydestroy.body13:
1452 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ]
1453 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1
1454 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]]
1455 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]]
1456 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
1457 // CHECK5:       arraydestroy.done17:
1458 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1459 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4
1460 // CHECK5-NEXT:    ret i32 [[TMP11]]
1461 //
1462 //
1463 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1464 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1465 // CHECK5-NEXT:  entry:
1466 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1467 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1468 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1469 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1470 // CHECK5-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1471 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1472 // CHECK5-NEXT:    store float [[CONV]], ptr [[F]], align 4
1473 // CHECK5-NEXT:    ret void
1474 //
1475 //
1476 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1477 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1478 // CHECK5-NEXT:  entry:
1479 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1480 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1481 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1482 // CHECK5-NEXT:    ret void
1483 //
1484 //
1485 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1486 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1487 // CHECK5-NEXT:  entry:
1488 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1489 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1490 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1491 // CHECK5-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1492 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1493 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1494 // CHECK5-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1495 // CHECK5-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1496 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1497 // CHECK5-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1498 // CHECK5-NEXT:    store float [[ADD]], ptr [[F]], align 4
1499 // CHECK5-NEXT:    ret void
1500 //
1501 //
1502 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1503 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1504 // CHECK5-NEXT:  entry:
1505 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1506 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1507 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1508 // CHECK5-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1509 // CHECK5-NEXT:    ret void
1510 //
1511 //
1512 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1513 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1514 // CHECK5-NEXT:  entry:
1515 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1516 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1517 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1518 // CHECK5-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1519 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1520 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1521 // CHECK5-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
1522 // CHECK5-NEXT:    ret void
1523 //
1524 //
1525 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1526 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1527 // CHECK5-NEXT:  entry:
1528 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1529 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1530 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1531 // CHECK5-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1532 // CHECK5-NEXT:    ret void
1533 //
1534 //
1535 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1536 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1537 // CHECK5-NEXT:  entry:
1538 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1539 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1540 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1541 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1542 // CHECK5-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1543 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
1544 // CHECK5-NEXT:    ret void
1545 //
1546 //
1547 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1548 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1549 // CHECK5-NEXT:  entry:
1550 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1551 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1552 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1553 // CHECK5-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1554 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1555 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1556 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1557 // CHECK5-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1558 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1559 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
1560 // CHECK5-NEXT:    ret void
1561 //
1562 //
1563 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1564 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1565 // CHECK5-NEXT:  entry:
1566 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1567 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1568 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1569 // CHECK5-NEXT:    ret void
1570 //
1571 //
1572 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
1573 // CHECK5-SAME: () #[[ATTR0]] {
1574 // CHECK5-NEXT:  entry:
1575 // CHECK5-NEXT:    call void @__cxx_global_var_init()
1576 // CHECK5-NEXT:    call void @__cxx_global_var_init.1()
1577 // CHECK5-NEXT:    call void @__cxx_global_var_init.2()
1578 // CHECK5-NEXT:    ret void
1579 //
1580 //
1581 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init
1582 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
1583 // CHECK7-NEXT:  entry:
1584 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
1585 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
1586 // CHECK7-NEXT:    ret void
1587 //
1588 //
1589 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1590 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1591 // CHECK7-NEXT:  entry:
1592 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1593 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1594 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1595 // CHECK7-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1596 // CHECK7-NEXT:    ret void
1597 //
1598 //
1599 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1600 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1601 // CHECK7-NEXT:  entry:
1602 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1603 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1604 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1605 // CHECK7-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1606 // CHECK7-NEXT:    ret void
1607 //
1608 //
1609 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1610 // CHECK7-SAME: () #[[ATTR0]] {
1611 // CHECK7-NEXT:  entry:
1612 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
1613 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)
1614 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
1615 // CHECK7-NEXT:    ret void
1616 //
1617 //
1618 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1619 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1620 // CHECK7-NEXT:  entry:
1621 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1622 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1623 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1624 // CHECK7-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1625 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1626 // CHECK7-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1627 // CHECK7-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1628 // CHECK7-NEXT:    ret void
1629 //
1630 //
1631 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1632 // CHECK7-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1633 // CHECK7-NEXT:  entry:
1634 // CHECK7-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 4
1635 // CHECK7-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 4
1636 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1637 // CHECK7:       arraydestroy.body:
1638 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1639 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1640 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1641 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
1642 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1643 // CHECK7:       arraydestroy.done1:
1644 // CHECK7-NEXT:    ret void
1645 //
1646 //
1647 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1648 // CHECK7-SAME: () #[[ATTR0]] {
1649 // CHECK7-NEXT:  entry:
1650 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1651 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
1652 // CHECK7-NEXT:    ret void
1653 //
1654 //
1655 // CHECK7-LABEL: define {{[^@]+}}@main
1656 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] {
1657 // CHECK7-NEXT:  entry:
1658 // CHECK7-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1659 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1660 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1661 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1662 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1663 // CHECK7-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1664 // CHECK7-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1665 // CHECK7-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1666 // CHECK7-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1667 // CHECK7-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
1668 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
1669 // CHECK7-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1670 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1671 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1672 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1673 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
1674 // CHECK7-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1675 // CHECK7-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
1676 // CHECK7-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1677 // CHECK7:       arrayctor.loop:
1678 // CHECK7-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1679 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1680 // CHECK7-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1
1681 // CHECK7-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1682 // CHECK7-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1683 // CHECK7:       arrayctor.cont:
1684 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
1685 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1686 // CHECK7:       omp.inner.for.cond:
1687 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
1688 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]
1689 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1690 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1691 // CHECK7:       omp.inner.for.cond.cleanup:
1692 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1693 // CHECK7:       omp.inner.for.body:
1694 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1695 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1696 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1697 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
1698 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP3]]
1699 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
1700 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP5]]
1701 // CHECK7-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
1702 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
1703 // CHECK7-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP6]]
1704 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]]
1705 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
1706 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]]
1707 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]
1708 // CHECK7-NEXT:    store i32 [[ADD2]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]]
1709 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1710 // CHECK7:       omp.body.continue:
1711 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1712 // CHECK7:       omp.inner.for.inc:
1713 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1714 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
1715 // CHECK7-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1716 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1717 // CHECK7:       omp.inner.for.end:
1718 // CHECK7-NEXT:    store i32 2, ptr [[I]], align 4
1719 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1720 // CHECK7-NEXT:    [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1721 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i32 2
1722 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1723 // CHECK7:       arraydestroy.body:
1724 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1725 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1726 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1727 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
1728 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
1729 // CHECK7:       arraydestroy.done5:
1730 // CHECK7-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1731 // CHECK7-NEXT:    ret i32 [[CALL]]
1732 //
1733 //
1734 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1735 // CHECK7-SAME: () #[[ATTR1]] comdat {
1736 // CHECK7-NEXT:  entry:
1737 // CHECK7-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1738 // CHECK7-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1739 // CHECK7-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1740 // CHECK7-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1741 // CHECK7-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1742 // CHECK7-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
1743 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1744 // CHECK7-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
1745 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1746 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1747 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1748 // CHECK7-NEXT:    [[T_VAR2:%.*]] = alloca i32, align 4
1749 // CHECK7-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 4
1750 // CHECK7-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
1751 // CHECK7-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
1752 // CHECK7-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 4
1753 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
1754 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1755 // CHECK7-NEXT:    store i32 0, ptr [[T_VAR]], align 4
1756 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
1757 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)
1758 // CHECK7-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1
1759 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
1760 // CHECK7-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
1761 // CHECK7-NEXT:    store ptr undef, ptr [[_TMP1]], align 4
1762 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1763 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1764 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1765 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
1766 // CHECK7-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1767 // CHECK7-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
1768 // CHECK7-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1769 // CHECK7:       arrayctor.loop:
1770 // CHECK7-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1771 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1772 // CHECK7-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1
1773 // CHECK7-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1774 // CHECK7-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1775 // CHECK7:       arrayctor.cont:
1776 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
1777 // CHECK7-NEXT:    store ptr [[VAR5]], ptr [[_TMP6]], align 4
1778 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1779 // CHECK7:       omp.inner.for.cond:
1780 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
1781 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
1782 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1783 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1784 // CHECK7:       omp.inner.for.cond.cleanup:
1785 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1786 // CHECK7:       omp.inner.for.body:
1787 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
1788 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1789 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1790 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
1791 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP7]]
1792 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
1793 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP5]]
1794 // CHECK7-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]]
1795 // CHECK7-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP7]]
1796 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
1797 // CHECK7-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]]
1798 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]]
1799 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1800 // CHECK7:       omp.body.continue:
1801 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1802 // CHECK7:       omp.inner.for.inc:
1803 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
1804 // CHECK7-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
1805 // CHECK7-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
1806 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
1807 // CHECK7:       omp.inner.for.end:
1808 // CHECK7-NEXT:    store i32 2, ptr [[I]], align 4
1809 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1810 // CHECK7-NEXT:    [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1811 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2
1812 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1813 // CHECK7:       arraydestroy.body:
1814 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1815 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1816 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1817 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
1818 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
1819 // CHECK7:       arraydestroy.done10:
1820 // CHECK7-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1821 // CHECK7-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1822 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2
1823 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY12:%.*]]
1824 // CHECK7:       arraydestroy.body12:
1825 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ]
1826 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1
1827 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]]
1828 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE15:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]]
1829 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]]
1830 // CHECK7:       arraydestroy.done16:
1831 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1832 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4
1833 // CHECK7-NEXT:    ret i32 [[TMP11]]
1834 //
1835 //
1836 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1837 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1838 // CHECK7-NEXT:  entry:
1839 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1840 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1841 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1842 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1843 // CHECK7-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1844 // CHECK7-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1845 // CHECK7-NEXT:    store float [[CONV]], ptr [[F]], align 4
1846 // CHECK7-NEXT:    ret void
1847 //
1848 //
1849 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1850 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1851 // CHECK7-NEXT:  entry:
1852 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1853 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1854 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1855 // CHECK7-NEXT:    ret void
1856 //
1857 //
1858 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1859 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1860 // CHECK7-NEXT:  entry:
1861 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1862 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1863 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1864 // CHECK7-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1865 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1866 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1867 // CHECK7-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1868 // CHECK7-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1869 // CHECK7-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1870 // CHECK7-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1871 // CHECK7-NEXT:    store float [[ADD]], ptr [[F]], align 4
1872 // CHECK7-NEXT:    ret void
1873 //
1874 //
1875 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1876 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1877 // CHECK7-NEXT:  entry:
1878 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1879 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1880 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1881 // CHECK7-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1882 // CHECK7-NEXT:    ret void
1883 //
1884 //
1885 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1886 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1887 // CHECK7-NEXT:  entry:
1888 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1889 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1890 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1891 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1892 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1893 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1894 // CHECK7-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1895 // CHECK7-NEXT:    ret void
1896 //
1897 //
1898 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1899 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1900 // CHECK7-NEXT:  entry:
1901 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1902 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1903 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1904 // CHECK7-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1905 // CHECK7-NEXT:    ret void
1906 //
1907 //
1908 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1909 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1910 // CHECK7-NEXT:  entry:
1911 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1912 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1913 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1914 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1915 // CHECK7-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1916 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
1917 // CHECK7-NEXT:    ret void
1918 //
1919 //
1920 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1921 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1922 // CHECK7-NEXT:  entry:
1923 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1924 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1925 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1926 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1927 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1928 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1929 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1930 // CHECK7-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1931 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1932 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
1933 // CHECK7-NEXT:    ret void
1934 //
1935 //
1936 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1937 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1938 // CHECK7-NEXT:  entry:
1939 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1940 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1941 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1942 // CHECK7-NEXT:    ret void
1943 //
1944 //
1945 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
1946 // CHECK7-SAME: () #[[ATTR0]] {
1947 // CHECK7-NEXT:  entry:
1948 // CHECK7-NEXT:    call void @__cxx_global_var_init()
1949 // CHECK7-NEXT:    call void @__cxx_global_var_init.1()
1950 // CHECK7-NEXT:    call void @__cxx_global_var_init.2()
1951 // CHECK7-NEXT:    ret void
1952 //
1953 //
1954 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init
1955 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
1956 // CHECK9-NEXT:  entry:
1957 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
1958 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
1959 // CHECK9-NEXT:    ret void
1960 //
1961 //
1962 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1963 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
1964 // CHECK9-NEXT:  entry:
1965 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1966 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1967 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1968 // CHECK9-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1969 // CHECK9-NEXT:    ret void
1970 //
1971 //
1972 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1973 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1974 // CHECK9-NEXT:  entry:
1975 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1976 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1977 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1978 // CHECK9-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1979 // CHECK9-NEXT:    ret void
1980 //
1981 //
1982 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1983 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1984 // CHECK9-NEXT:  entry:
1985 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1986 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1987 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1988 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1989 // CHECK9-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1990 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1991 // CHECK9-NEXT:    store float [[CONV]], ptr [[F]], align 4
1992 // CHECK9-NEXT:    ret void
1993 //
1994 //
1995 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1996 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1997 // CHECK9-NEXT:  entry:
1998 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1999 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2000 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2001 // CHECK9-NEXT:    ret void
2002 //
2003 //
2004 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2005 // CHECK9-SAME: () #[[ATTR0]] {
2006 // CHECK9-NEXT:  entry:
2007 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
2008 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
2009 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
2010 // CHECK9-NEXT:    ret void
2011 //
2012 //
2013 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2014 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2015 // CHECK9-NEXT:  entry:
2016 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2017 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2018 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2019 // CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2020 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2021 // CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2022 // CHECK9-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2023 // CHECK9-NEXT:    ret void
2024 //
2025 //
2026 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2027 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
2028 // CHECK9-NEXT:  entry:
2029 // CHECK9-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
2030 // CHECK9-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
2031 // CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2032 // CHECK9:       arraydestroy.body:
2033 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2034 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2035 // CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2036 // CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
2037 // CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2038 // CHECK9:       arraydestroy.done1:
2039 // CHECK9-NEXT:    ret void
2040 //
2041 //
2042 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2043 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2044 // CHECK9-NEXT:  entry:
2045 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2046 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2047 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2048 // CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2049 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2050 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2051 // CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2052 // CHECK9-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
2053 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2054 // CHECK9-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2055 // CHECK9-NEXT:    store float [[ADD]], ptr [[F]], align 4
2056 // CHECK9-NEXT:    ret void
2057 //
2058 //
2059 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2060 // CHECK9-SAME: () #[[ATTR0]] {
2061 // CHECK9-NEXT:  entry:
2062 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2063 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
2064 // CHECK9-NEXT:    ret void
2065 //
2066 //
2067 // CHECK9-LABEL: define {{[^@]+}}@main
2068 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
2069 // CHECK9-NEXT:  entry:
2070 // CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2071 // CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2072 // CHECK9-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2073 // CHECK9-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
2074 // CHECK9-NEXT:    ret i32 0
2075 //
2076 //
2077 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75
2078 // CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR4:[0-9]+]] {
2079 // CHECK9-NEXT:  entry:
2080 // CHECK9-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8
2081 // CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
2082 // CHECK9-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 8
2083 // CHECK9-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 8
2084 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined)
2085 // CHECK9-NEXT:    ret void
2086 //
2087 //
2088 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined
2089 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
2090 // CHECK9-NEXT:  entry:
2091 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2092 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2093 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2094 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2095 // CHECK9-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
2096 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2097 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2098 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2099 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2100 // CHECK9-NEXT:    [[G:%.*]] = alloca i32, align 4
2101 // CHECK9-NEXT:    [[G1:%.*]] = alloca i32, align 4
2102 // CHECK9-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
2103 // CHECK9-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
2104 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
2105 // CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
2106 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2107 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2108 // CHECK9-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
2109 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2110 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2111 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2112 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2113 // CHECK9-NEXT:    store ptr [[G1]], ptr [[_TMP2]], align 8
2114 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2115 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2116 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2117 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2118 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2119 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2120 // CHECK9:       cond.true:
2121 // CHECK9-NEXT:    br label [[COND_END:%.*]]
2122 // CHECK9:       cond.false:
2123 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2124 // CHECK9-NEXT:    br label [[COND_END]]
2125 // CHECK9:       cond.end:
2126 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2127 // CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2128 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2129 // CHECK9-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2130 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2131 // CHECK9:       omp.inner.for.cond:
2132 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]]
2133 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]]
2134 // CHECK9-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2135 // CHECK9-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2136 // CHECK9:       omp.inner.for.body:
2137 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
2138 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2139 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2140 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]
2141 // CHECK9-NEXT:    store i32 1, ptr [[G]], align 4, !llvm.access.group [[ACC_GRP4]]
2142 // CHECK9-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP4]]
2143 // CHECK9-NEXT:    store volatile i32 1, ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP4]]
2144 // CHECK9-NEXT:    store i32 2, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP4]]
2145 // CHECK9-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
2146 // CHECK9-NEXT:    store ptr [[G]], ptr [[TMP9]], align 8, !llvm.access.group [[ACC_GRP4]]
2147 // CHECK9-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
2148 // CHECK9-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP4]]
2149 // CHECK9-NEXT:    store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP4]]
2150 // CHECK9-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
2151 // CHECK9-NEXT:    store ptr [[SIVAR]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP4]]
2152 // CHECK9-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group [[ACC_GRP4]]
2153 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2154 // CHECK9:       omp.body.continue:
2155 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2156 // CHECK9:       omp.inner.for.inc:
2157 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
2158 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
2159 // CHECK9-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
2160 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
2161 // CHECK9:       omp.inner.for.end:
2162 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2163 // CHECK9:       omp.loop.exit:
2164 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
2165 // CHECK9-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2166 // CHECK9-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
2167 // CHECK9-NEXT:    br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2168 // CHECK9:       .omp.final.then:
2169 // CHECK9-NEXT:    store i32 2, ptr [[I]], align 4
2170 // CHECK9-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2171 // CHECK9:       .omp.final.done:
2172 // CHECK9-NEXT:    ret void
2173 //
2174 //
2175 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
2176 // CHECK9-SAME: () #[[ATTR0]] {
2177 // CHECK9-NEXT:  entry:
2178 // CHECK9-NEXT:    call void @__cxx_global_var_init()
2179 // CHECK9-NEXT:    call void @__cxx_global_var_init.1()
2180 // CHECK9-NEXT:    call void @__cxx_global_var_init.2()
2181 // CHECK9-NEXT:    ret void
2182 //
2183 //
2184 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init
2185 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
2186 // CHECK11-NEXT:  entry:
2187 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
2188 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
2189 // CHECK11-NEXT:    ret void
2190 //
2191 //
2192 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2193 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
2194 // CHECK11-NEXT:  entry:
2195 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2196 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2197 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2198 // CHECK11-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2199 // CHECK11-NEXT:    ret void
2200 //
2201 //
2202 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2203 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2204 // CHECK11-NEXT:  entry:
2205 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2206 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2207 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2208 // CHECK11-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2209 // CHECK11-NEXT:    ret void
2210 //
2211 //
2212 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2213 // CHECK11-SAME: () #[[ATTR0]] {
2214 // CHECK11-NEXT:  entry:
2215 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
2216 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
2217 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
2218 // CHECK11-NEXT:    ret void
2219 //
2220 //
2221 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2222 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2223 // CHECK11-NEXT:  entry:
2224 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2225 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2226 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2227 // CHECK11-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2228 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2229 // CHECK11-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2230 // CHECK11-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2231 // CHECK11-NEXT:    ret void
2232 //
2233 //
2234 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2235 // CHECK11-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
2236 // CHECK11-NEXT:  entry:
2237 // CHECK11-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
2238 // CHECK11-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
2239 // CHECK11-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2240 // CHECK11:       arraydestroy.body:
2241 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2242 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2243 // CHECK11-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2244 // CHECK11-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
2245 // CHECK11-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2246 // CHECK11:       arraydestroy.done1:
2247 // CHECK11-NEXT:    ret void
2248 //
2249 //
2250 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2251 // CHECK11-SAME: () #[[ATTR0]] {
2252 // CHECK11-NEXT:  entry:
2253 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2254 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
2255 // CHECK11-NEXT:    ret void
2256 //
2257 //
2258 // CHECK11-LABEL: define {{[^@]+}}@main
2259 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
2260 // CHECK11-NEXT:  entry:
2261 // CHECK11-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2262 // CHECK11-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2263 // CHECK11-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2264 // CHECK11-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
2265 // CHECK11-NEXT:    ret i32 0
2266 //
2267 //
2268 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2269 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2270 // CHECK11-NEXT:  entry:
2271 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2272 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2273 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2274 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2275 // CHECK11-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2276 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2277 // CHECK11-NEXT:    store float [[CONV]], ptr [[F]], align 4
2278 // CHECK11-NEXT:    ret void
2279 //
2280 //
2281 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2282 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2283 // CHECK11-NEXT:  entry:
2284 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2285 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2286 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2287 // CHECK11-NEXT:    ret void
2288 //
2289 //
2290 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2291 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2292 // CHECK11-NEXT:  entry:
2293 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2294 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2295 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2296 // CHECK11-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2297 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2298 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2299 // CHECK11-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2300 // CHECK11-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
2301 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2302 // CHECK11-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2303 // CHECK11-NEXT:    store float [[ADD]], ptr [[F]], align 4
2304 // CHECK11-NEXT:    ret void
2305 //
2306 //
2307 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
2308 // CHECK11-SAME: () #[[ATTR0]] {
2309 // CHECK11-NEXT:  entry:
2310 // CHECK11-NEXT:    call void @__cxx_global_var_init()
2311 // CHECK11-NEXT:    call void @__cxx_global_var_init.1()
2312 // CHECK11-NEXT:    call void @__cxx_global_var_init.2()
2313 // CHECK11-NEXT:    ret void
2314 //