| blob | 17c87a5dae4199ed7eb6156aae1e62ba48e07124 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-CVT
3 ; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-FP16
4 ; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-CVT
5 ; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP16
7 ;
8 ; 32-bit float to signed integer
9 ;
11 declare i1 @llvm.fptosi.sat.i1.f32 (float)
12 declare i8 @llvm.fptosi.sat.i8.f32 (float)
13 declare i13 @llvm.fptosi.sat.i13.f32 (float)
14 declare i16 @llvm.fptosi.sat.i16.f32 (float)
15 declare i19 @llvm.fptosi.sat.i19.f32 (float)
16 declare i32 @llvm.fptosi.sat.i32.f32 (float)
17 declare i50 @llvm.fptosi.sat.i50.f32 (float)
18 declare i64 @llvm.fptosi.sat.i64.f32 (float)
19 declare i100 @llvm.fptosi.sat.i100.f32(float)
20 declare i128 @llvm.fptosi.sat.i128.f32(float)
22 define i1 @test_signed_i1_f32(float %f) nounwind {
23 ; CHECK-SD-LABEL: test_signed_i1_f32:
24 ; CHECK-SD: // %bb.0:
25 ; CHECK-SD-NEXT: fcvtzs w8, s0
26 ; CHECK-SD-NEXT: ands w8, w8, w8, asr #31
27 ; CHECK-SD-NEXT: csinv w8, w8, wzr, ge
28 ; CHECK-SD-NEXT: and w0, w8, #0x1
29 ; CHECK-SD-NEXT: ret
30 ;
31 ; CHECK-GI-LABEL: test_signed_i1_f32:
32 ; CHECK-GI: // %bb.0:
33 ; CHECK-GI-NEXT: fcvtzs w8, s0
34 ; CHECK-GI-NEXT: cmp w8, #0
35 ; CHECK-GI-NEXT: csel w8, w8, wzr, lt
36 ; CHECK-GI-NEXT: cmp w8, #0
37 ; CHECK-GI-NEXT: csinv w8, w8, wzr, ge
38 ; CHECK-GI-NEXT: and w0, w8, #0x1
39 ; CHECK-GI-NEXT: ret
40 %x = call i1 @llvm.fptosi.sat.i1.f32(float %f)
41 ret i1 %x
42 }
44 define i8 @test_signed_i8_f32(float %f) nounwind {
45 ; CHECK-LABEL: test_signed_i8_f32:
46 ; CHECK: // %bb.0:
47 ; CHECK-NEXT: fcvtzs w9, s0
48 ; CHECK-NEXT: mov w8, #127 // =0x7f
49 ; CHECK-NEXT: cmp w9, #127
50 ; CHECK-NEXT: csel w8, w9, w8, lt
51 ; CHECK-NEXT: mov w9, #-128 // =0xffffff80
52 ; CHECK-NEXT: cmn w8, #128
53 ; CHECK-NEXT: csel w0, w8, w9, gt
54 ; CHECK-NEXT: ret
55 %x = call i8 @llvm.fptosi.sat.i8.f32(float %f)
56 ret i8 %x
57 }
59 define i13 @test_signed_i13_f32(float %f) nounwind {
60 ; CHECK-LABEL: test_signed_i13_f32:
61 ; CHECK: // %bb.0:
62 ; CHECK-NEXT: fcvtzs w9, s0
63 ; CHECK-NEXT: mov w8, #4095 // =0xfff
64 ; CHECK-NEXT: cmp w9, #4095
65 ; CHECK-NEXT: csel w8, w9, w8, lt
66 ; CHECK-NEXT: mov w9, #-4096 // =0xfffff000
67 ; CHECK-NEXT: cmn w8, #1, lsl #12 // =4096
68 ; CHECK-NEXT: csel w0, w8, w9, gt
69 ; CHECK-NEXT: ret
70 %x = call i13 @llvm.fptosi.sat.i13.f32(float %f)
71 ret i13 %x
72 }
74 define i16 @test_signed_i16_f32(float %f) nounwind {
75 ; CHECK-LABEL: test_signed_i16_f32:
76 ; CHECK: // %bb.0:
77 ; CHECK-NEXT: fcvtzs w8, s0
78 ; CHECK-NEXT: mov w9, #32767 // =0x7fff
79 ; CHECK-NEXT: cmp w8, w9
80 ; CHECK-NEXT: csel w8, w8, w9, lt
81 ; CHECK-NEXT: mov w9, #-32768 // =0xffff8000
82 ; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768
83 ; CHECK-NEXT: csel w0, w8, w9, gt
84 ; CHECK-NEXT: ret
85 %x = call i16 @llvm.fptosi.sat.i16.f32(float %f)
86 ret i16 %x
87 }
89 define i19 @test_signed_i19_f32(float %f) nounwind {
90 ; CHECK-LABEL: test_signed_i19_f32:
91 ; CHECK: // %bb.0:
92 ; CHECK-NEXT: fcvtzs w8, s0
93 ; CHECK-NEXT: mov w9, #262143 // =0x3ffff
94 ; CHECK-NEXT: cmp w8, w9
95 ; CHECK-NEXT: csel w8, w8, w9, lt
96 ; CHECK-NEXT: mov w9, #-262144 // =0xfffc0000
97 ; CHECK-NEXT: cmn w8, #64, lsl #12 // =262144
98 ; CHECK-NEXT: csel w0, w8, w9, gt
99 ; CHECK-NEXT: ret
100 %x = call i19 @llvm.fptosi.sat.i19.f32(float %f)
101 ret i19 %x
102 }
104 define i32 @test_signed_i32_f32(float %f) nounwind {
105 ; CHECK-LABEL: test_signed_i32_f32:
106 ; CHECK: // %bb.0:
107 ; CHECK-NEXT: fcvtzs w0, s0
108 ; CHECK-NEXT: ret
109 %x = call i32 @llvm.fptosi.sat.i32.f32(float %f)
110 ret i32 %x
111 }
113 define i50 @test_signed_i50_f32(float %f) nounwind {
114 ; CHECK-SD-LABEL: test_signed_i50_f32:
115 ; CHECK-SD: // %bb.0:
116 ; CHECK-SD-NEXT: fcvtzs x8, s0
117 ; CHECK-SD-NEXT: mov x9, #562949953421311 // =0x1ffffffffffff
118 ; CHECK-SD-NEXT: cmp x8, x9
119 ; CHECK-SD-NEXT: csel x8, x8, x9, lt
120 ; CHECK-SD-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
121 ; CHECK-SD-NEXT: cmp x8, x9
122 ; CHECK-SD-NEXT: csel x0, x8, x9, gt
123 ; CHECK-SD-NEXT: ret
124 ;
125 ; CHECK-GI-LABEL: test_signed_i50_f32:
126 ; CHECK-GI: // %bb.0:
127 ; CHECK-GI-NEXT: fcvtzs x8, s0
128 ; CHECK-GI-NEXT: mov x9, #562949953421311 // =0x1ffffffffffff
129 ; CHECK-GI-NEXT: mov x10, #-562949953421312 // =0xfffe000000000000
130 ; CHECK-GI-NEXT: cmp x8, x9
131 ; CHECK-GI-NEXT: csel x8, x8, x9, lt
132 ; CHECK-GI-NEXT: cmp x8, x10
133 ; CHECK-GI-NEXT: csel x0, x8, x10, gt
134 ; CHECK-GI-NEXT: ret
135 %x = call i50 @llvm.fptosi.sat.i50.f32(float %f)
136 ret i50 %x
137 }
139 define i64 @test_signed_i64_f32(float %f) nounwind {
140 ; CHECK-LABEL: test_signed_i64_f32:
141 ; CHECK: // %bb.0:
142 ; CHECK-NEXT: fcvtzs x0, s0
143 ; CHECK-NEXT: ret
144 %x = call i64 @llvm.fptosi.sat.i64.f32(float %f)
145 ret i64 %x
146 }
148 define i100 @test_signed_i100_f32(float %f) nounwind {
149 ; CHECK-SD-LABEL: test_signed_i100_f32:
150 ; CHECK-SD: // %bb.0:
151 ; CHECK-SD-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
152 ; CHECK-SD-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
153 ; CHECK-SD-NEXT: fmov s8, s0
154 ; CHECK-SD-NEXT: bl __fixsfti
155 ; CHECK-SD-NEXT: movi v0.2s, #241, lsl #24
156 ; CHECK-SD-NEXT: mov w8, #1895825407 // =0x70ffffff
157 ; CHECK-SD-NEXT: mov x10, #34359738367 // =0x7ffffffff
158 ; CHECK-SD-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
159 ; CHECK-SD-NEXT: fcmp s8, s0
160 ; CHECK-SD-NEXT: fmov s0, w8
161 ; CHECK-SD-NEXT: mov x8, #-34359738368 // =0xfffffff800000000
162 ; CHECK-SD-NEXT: csel x9, xzr, x0, lt
163 ; CHECK-SD-NEXT: csel x8, x8, x1, lt
164 ; CHECK-SD-NEXT: fcmp s8, s0
165 ; CHECK-SD-NEXT: csel x8, x10, x8, gt
166 ; CHECK-SD-NEXT: csinv x9, x9, xzr, le
167 ; CHECK-SD-NEXT: fcmp s8, s8
168 ; CHECK-SD-NEXT: csel x0, xzr, x9, vs
169 ; CHECK-SD-NEXT: csel x1, xzr, x8, vs
170 ; CHECK-SD-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
171 ; CHECK-SD-NEXT: ret
172 ;
173 ; CHECK-GI-LABEL: test_signed_i100_f32:
174 ; CHECK-GI: // %bb.0:
175 ; CHECK-GI-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
176 ; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
177 ; CHECK-GI-NEXT: fmov s8, s0
178 ; CHECK-GI-NEXT: bl __fixsfti
179 ; CHECK-GI-NEXT: movi v0.2s, #241, lsl #24
180 ; CHECK-GI-NEXT: mov w8, #1895825407 // =0x70ffffff
181 ; CHECK-GI-NEXT: mov x10, #34359738367 // =0x7ffffffff
182 ; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
183 ; CHECK-GI-NEXT: fcmp s8, s0
184 ; CHECK-GI-NEXT: fmov s0, w8
185 ; CHECK-GI-NEXT: mov x8, #34359738368 // =0x800000000
186 ; CHECK-GI-NEXT: csel x9, xzr, x0, lt
187 ; CHECK-GI-NEXT: csel x8, x8, x1, lt
188 ; CHECK-GI-NEXT: fcmp s8, s0
189 ; CHECK-GI-NEXT: csinv x9, x9, xzr, le
190 ; CHECK-GI-NEXT: csel x8, x10, x8, gt
191 ; CHECK-GI-NEXT: fcmp s8, s8
192 ; CHECK-GI-NEXT: csel x0, xzr, x9, vs
193 ; CHECK-GI-NEXT: csel x1, xzr, x8, vs
194 ; CHECK-GI-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
195 ; CHECK-GI-NEXT: ret
196 %x = call i100 @llvm.fptosi.sat.i100.f32(float %f)
197 ret i100 %x
198 }
200 define i128 @test_signed_i128_f32(float %f) nounwind {
201 ; CHECK-SD-LABEL: test_signed_i128_f32:
202 ; CHECK-SD: // %bb.0:
203 ; CHECK-SD-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
204 ; CHECK-SD-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
205 ; CHECK-SD-NEXT: fmov s8, s0
206 ; CHECK-SD-NEXT: bl __fixsfti
207 ; CHECK-SD-NEXT: movi v0.2s, #255, lsl #24
208 ; CHECK-SD-NEXT: mov w8, #2130706431 // =0x7effffff
209 ; CHECK-SD-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
210 ; CHECK-SD-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
211 ; CHECK-SD-NEXT: fcmp s8, s0
212 ; CHECK-SD-NEXT: fmov s0, w8
213 ; CHECK-SD-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
214 ; CHECK-SD-NEXT: csel x9, xzr, x0, lt
215 ; CHECK-SD-NEXT: csel x8, x8, x1, lt
216 ; CHECK-SD-NEXT: fcmp s8, s0
217 ; CHECK-SD-NEXT: csel x8, x10, x8, gt
218 ; CHECK-SD-NEXT: csinv x9, x9, xzr, le
219 ; CHECK-SD-NEXT: fcmp s8, s8
220 ; CHECK-SD-NEXT: csel x0, xzr, x9, vs
221 ; CHECK-SD-NEXT: csel x1, xzr, x8, vs
222 ; CHECK-SD-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
223 ; CHECK-SD-NEXT: ret
224 ;
225 ; CHECK-GI-LABEL: test_signed_i128_f32:
226 ; CHECK-GI: // %bb.0:
227 ; CHECK-GI-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
228 ; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
229 ; CHECK-GI-NEXT: fmov s8, s0
230 ; CHECK-GI-NEXT: bl __fixsfti
231 ; CHECK-GI-NEXT: movi v0.2s, #255, lsl #24
232 ; CHECK-GI-NEXT: mov w8, #2130706431 // =0x7effffff
233 ; CHECK-GI-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
234 ; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
235 ; CHECK-GI-NEXT: fcmp s8, s0
236 ; CHECK-GI-NEXT: fmov s0, w8
237 ; CHECK-GI-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
238 ; CHECK-GI-NEXT: csel x9, xzr, x0, lt
239 ; CHECK-GI-NEXT: csel x8, x8, x1, lt
240 ; CHECK-GI-NEXT: fcmp s8, s0
241 ; CHECK-GI-NEXT: csinv x9, x9, xzr, le
242 ; CHECK-GI-NEXT: csel x8, x10, x8, gt
243 ; CHECK-GI-NEXT: fcmp s8, s8
244 ; CHECK-GI-NEXT: csel x0, xzr, x9, vs
245 ; CHECK-GI-NEXT: csel x1, xzr, x8, vs
246 ; CHECK-GI-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
247 ; CHECK-GI-NEXT: ret
248 %x = call i128 @llvm.fptosi.sat.i128.f32(float %f)
249 ret i128 %x
250 }
252 ;
253 ; 64-bit float to signed integer
254 ;
256 declare i1 @llvm.fptosi.sat.i1.f64 (double)
257 declare i8 @llvm.fptosi.sat.i8.f64 (double)
258 declare i13 @llvm.fptosi.sat.i13.f64 (double)
259 declare i16 @llvm.fptosi.sat.i16.f64 (double)
260 declare i19 @llvm.fptosi.sat.i19.f64 (double)
261 declare i32 @llvm.fptosi.sat.i32.f64 (double)
262 declare i50 @llvm.fptosi.sat.i50.f64 (double)
263 declare i64 @llvm.fptosi.sat.i64.f64 (double)
264 declare i100 @llvm.fptosi.sat.i100.f64(double)
265 declare i128 @llvm.fptosi.sat.i128.f64(double)
267 define i1 @test_signed_i1_f64(double %f) nounwind {
268 ; CHECK-SD-LABEL: test_signed_i1_f64:
269 ; CHECK-SD: // %bb.0:
270 ; CHECK-SD-NEXT: fcvtzs w8, d0
271 ; CHECK-SD-NEXT: ands w8, w8, w8, asr #31
272 ; CHECK-SD-NEXT: csinv w8, w8, wzr, ge
273 ; CHECK-SD-NEXT: and w0, w8, #0x1
274 ; CHECK-SD-NEXT: ret
275 ;
276 ; CHECK-GI-LABEL: test_signed_i1_f64:
277 ; CHECK-GI: // %bb.0:
278 ; CHECK-GI-NEXT: fcvtzs w8, d0
279 ; CHECK-GI-NEXT: cmp w8, #0
280 ; CHECK-GI-NEXT: csel w8, w8, wzr, lt
281 ; CHECK-GI-NEXT: cmp w8, #0
282 ; CHECK-GI-NEXT: csinv w8, w8, wzr, ge
283 ; CHECK-GI-NEXT: and w0, w8, #0x1
284 ; CHECK-GI-NEXT: ret
285 %x = call i1 @llvm.fptosi.sat.i1.f64(double %f)
286 ret i1 %x
287 }
289 define i8 @test_signed_i8_f64(double %f) nounwind {
290 ; CHECK-LABEL: test_signed_i8_f64:
291 ; CHECK: // %bb.0:
292 ; CHECK-NEXT: fcvtzs w9, d0
293 ; CHECK-NEXT: mov w8, #127 // =0x7f
294 ; CHECK-NEXT: cmp w9, #127
295 ; CHECK-NEXT: csel w8, w9, w8, lt
296 ; CHECK-NEXT: mov w9, #-128 // =0xffffff80
297 ; CHECK-NEXT: cmn w8, #128
298 ; CHECK-NEXT: csel w0, w8, w9, gt
299 ; CHECK-NEXT: ret
300 %x = call i8 @llvm.fptosi.sat.i8.f64(double %f)
301 ret i8 %x
302 }
304 define i13 @test_signed_i13_f64(double %f) nounwind {
305 ; CHECK-LABEL: test_signed_i13_f64:
306 ; CHECK: // %bb.0:
307 ; CHECK-NEXT: fcvtzs w9, d0
308 ; CHECK-NEXT: mov w8, #4095 // =0xfff
309 ; CHECK-NEXT: cmp w9, #4095
310 ; CHECK-NEXT: csel w8, w9, w8, lt
311 ; CHECK-NEXT: mov w9, #-4096 // =0xfffff000
312 ; CHECK-NEXT: cmn w8, #1, lsl #12 // =4096
313 ; CHECK-NEXT: csel w0, w8, w9, gt
314 ; CHECK-NEXT: ret
315 %x = call i13 @llvm.fptosi.sat.i13.f64(double %f)
316 ret i13 %x
317 }
319 define i16 @test_signed_i16_f64(double %f) nounwind {
320 ; CHECK-LABEL: test_signed_i16_f64:
321 ; CHECK: // %bb.0:
322 ; CHECK-NEXT: fcvtzs w8, d0
323 ; CHECK-NEXT: mov w9, #32767 // =0x7fff
324 ; CHECK-NEXT: cmp w8, w9
325 ; CHECK-NEXT: csel w8, w8, w9, lt
326 ; CHECK-NEXT: mov w9, #-32768 // =0xffff8000
327 ; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768
328 ; CHECK-NEXT: csel w0, w8, w9, gt
329 ; CHECK-NEXT: ret
330 %x = call i16 @llvm.fptosi.sat.i16.f64(double %f)
331 ret i16 %x
332 }
334 define i19 @test_signed_i19_f64(double %f) nounwind {
335 ; CHECK-LABEL: test_signed_i19_f64:
336 ; CHECK: // %bb.0:
337 ; CHECK-NEXT: fcvtzs w8, d0
338 ; CHECK-NEXT: mov w9, #262143 // =0x3ffff
339 ; CHECK-NEXT: cmp w8, w9
340 ; CHECK-NEXT: csel w8, w8, w9, lt
341 ; CHECK-NEXT: mov w9, #-262144 // =0xfffc0000
342 ; CHECK-NEXT: cmn w8, #64, lsl #12 // =262144
343 ; CHECK-NEXT: csel w0, w8, w9, gt
344 ; CHECK-NEXT: ret
345 %x = call i19 @llvm.fptosi.sat.i19.f64(double %f)
346 ret i19 %x
347 }
349 define i32 @test_signed_i32_f64(double %f) nounwind {
350 ; CHECK-LABEL: test_signed_i32_f64:
351 ; CHECK: // %bb.0:
352 ; CHECK-NEXT: fcvtzs w0, d0
353 ; CHECK-NEXT: ret
354 %x = call i32 @llvm.fptosi.sat.i32.f64(double %f)
355 ret i32 %x
356 }
358 define i50 @test_signed_i50_f64(double %f) nounwind {
359 ; CHECK-SD-LABEL: test_signed_i50_f64:
360 ; CHECK-SD: // %bb.0:
361 ; CHECK-SD-NEXT: fcvtzs x8, d0
362 ; CHECK-SD-NEXT: mov x9, #562949953421311 // =0x1ffffffffffff
363 ; CHECK-SD-NEXT: cmp x8, x9
364 ; CHECK-SD-NEXT: csel x8, x8, x9, lt
365 ; CHECK-SD-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
366 ; CHECK-SD-NEXT: cmp x8, x9
367 ; CHECK-SD-NEXT: csel x0, x8, x9, gt
368 ; CHECK-SD-NEXT: ret
369 ;
370 ; CHECK-GI-LABEL: test_signed_i50_f64:
371 ; CHECK-GI: // %bb.0:
372 ; CHECK-GI-NEXT: fcvtzs x8, d0
373 ; CHECK-GI-NEXT: mov x9, #562949953421311 // =0x1ffffffffffff
374 ; CHECK-GI-NEXT: mov x10, #-562949953421312 // =0xfffe000000000000
375 ; CHECK-GI-NEXT: cmp x8, x9
376 ; CHECK-GI-NEXT: csel x8, x8, x9, lt
377 ; CHECK-GI-NEXT: cmp x8, x10
378 ; CHECK-GI-NEXT: csel x0, x8, x10, gt
379 ; CHECK-GI-NEXT: ret
380 %x = call i50 @llvm.fptosi.sat.i50.f64(double %f)
381 ret i50 %x
382 }
384 define i64 @test_signed_i64_f64(double %f) nounwind {
385 ; CHECK-LABEL: test_signed_i64_f64:
386 ; CHECK: // %bb.0:
387 ; CHECK-NEXT: fcvtzs x0, d0
388 ; CHECK-NEXT: ret
389 %x = call i64 @llvm.fptosi.sat.i64.f64(double %f)
390 ret i64 %x
391 }
393 define i100 @test_signed_i100_f64(double %f) nounwind {
394 ; CHECK-SD-LABEL: test_signed_i100_f64:
395 ; CHECK-SD: // %bb.0:
396 ; CHECK-SD-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
397 ; CHECK-SD-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
398 ; CHECK-SD-NEXT: fmov d8, d0
399 ; CHECK-SD-NEXT: bl __fixdfti
400 ; CHECK-SD-NEXT: mov x8, #-4170333254945079296 // =0xc620000000000000
401 ; CHECK-SD-NEXT: mov x10, #34359738367 // =0x7ffffffff
402 ; CHECK-SD-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
403 ; CHECK-SD-NEXT: fmov d0, x8
404 ; CHECK-SD-NEXT: mov x8, #5053038781909696511 // =0x461fffffffffffff
405 ; CHECK-SD-NEXT: fcmp d8, d0
406 ; CHECK-SD-NEXT: fmov d0, x8
407 ; CHECK-SD-NEXT: mov x8, #-34359738368 // =0xfffffff800000000
408 ; CHECK-SD-NEXT: csel x9, xzr, x0, lt
409 ; CHECK-SD-NEXT: csel x8, x8, x1, lt
410 ; CHECK-SD-NEXT: fcmp d8, d0
411 ; CHECK-SD-NEXT: csel x8, x10, x8, gt
412 ; CHECK-SD-NEXT: csinv x9, x9, xzr, le
413 ; CHECK-SD-NEXT: fcmp d8, d8
414 ; CHECK-SD-NEXT: csel x0, xzr, x9, vs
415 ; CHECK-SD-NEXT: csel x1, xzr, x8, vs
416 ; CHECK-SD-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
417 ; CHECK-SD-NEXT: ret
418 ;
419 ; CHECK-GI-LABEL: test_signed_i100_f64:
420 ; CHECK-GI: // %bb.0:
421 ; CHECK-GI-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
422 ; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
423 ; CHECK-GI-NEXT: fmov d8, d0
424 ; CHECK-GI-NEXT: bl __fixdfti
425 ; CHECK-GI-NEXT: mov x8, #-4170333254945079296 // =0xc620000000000000
426 ; CHECK-GI-NEXT: mov x10, #34359738367 // =0x7ffffffff
427 ; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
428 ; CHECK-GI-NEXT: fmov d0, x8
429 ; CHECK-GI-NEXT: mov x8, #5053038781909696511 // =0x461fffffffffffff
430 ; CHECK-GI-NEXT: fcmp d8, d0
431 ; CHECK-GI-NEXT: fmov d0, x8
432 ; CHECK-GI-NEXT: mov x8, #34359738368 // =0x800000000
433 ; CHECK-GI-NEXT: csel x9, xzr, x0, lt
434 ; CHECK-GI-NEXT: csel x8, x8, x1, lt
435 ; CHECK-GI-NEXT: fcmp d8, d0
436 ; CHECK-GI-NEXT: csinv x9, x9, xzr, le
437 ; CHECK-GI-NEXT: csel x8, x10, x8, gt
438 ; CHECK-GI-NEXT: fcmp d8, d8
439 ; CHECK-GI-NEXT: csel x0, xzr, x9, vs
440 ; CHECK-GI-NEXT: csel x1, xzr, x8, vs
441 ; CHECK-GI-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
442 ; CHECK-GI-NEXT: ret
443 %x = call i100 @llvm.fptosi.sat.i100.f64(double %f)
444 ret i100 %x
445 }
447 define i128 @test_signed_i128_f64(double %f) nounwind {
448 ; CHECK-SD-LABEL: test_signed_i128_f64:
449 ; CHECK-SD: // %bb.0:
450 ; CHECK-SD-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
451 ; CHECK-SD-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
452 ; CHECK-SD-NEXT: fmov d8, d0
453 ; CHECK-SD-NEXT: bl __fixdfti
454 ; CHECK-SD-NEXT: mov x8, #-4044232465378705408 // =0xc7e0000000000000
455 ; CHECK-SD-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
456 ; CHECK-SD-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
457 ; CHECK-SD-NEXT: fmov d0, x8
458 ; CHECK-SD-NEXT: mov x8, #5179139571476070399 // =0x47dfffffffffffff
459 ; CHECK-SD-NEXT: fcmp d8, d0
460 ; CHECK-SD-NEXT: fmov d0, x8
461 ; CHECK-SD-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
462 ; CHECK-SD-NEXT: csel x9, xzr, x0, lt
463 ; CHECK-SD-NEXT: csel x8, x8, x1, lt
464 ; CHECK-SD-NEXT: fcmp d8, d0
465 ; CHECK-SD-NEXT: csel x8, x10, x8, gt
466 ; CHECK-SD-NEXT: csinv x9, x9, xzr, le
467 ; CHECK-SD-NEXT: fcmp d8, d8
468 ; CHECK-SD-NEXT: csel x0, xzr, x9, vs
469 ; CHECK-SD-NEXT: csel x1, xzr, x8, vs
470 ; CHECK-SD-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
471 ; CHECK-SD-NEXT: ret
472 ;
473 ; CHECK-GI-LABEL: test_signed_i128_f64:
474 ; CHECK-GI: // %bb.0:
475 ; CHECK-GI-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
476 ; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
477 ; CHECK-GI-NEXT: fmov d8, d0
478 ; CHECK-GI-NEXT: bl __fixdfti
479 ; CHECK-GI-NEXT: mov x8, #-4044232465378705408 // =0xc7e0000000000000
480 ; CHECK-GI-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
481 ; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
482 ; CHECK-GI-NEXT: fmov d0, x8
483 ; CHECK-GI-NEXT: mov x8, #5179139571476070399 // =0x47dfffffffffffff
484 ; CHECK-GI-NEXT: fcmp d8, d0
485 ; CHECK-GI-NEXT: fmov d0, x8
486 ; CHECK-GI-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
487 ; CHECK-GI-NEXT: csel x9, xzr, x0, lt
488 ; CHECK-GI-NEXT: csel x8, x8, x1, lt
489 ; CHECK-GI-NEXT: fcmp d8, d0
490 ; CHECK-GI-NEXT: csinv x9, x9, xzr, le
491 ; CHECK-GI-NEXT: csel x8, x10, x8, gt
492 ; CHECK-GI-NEXT: fcmp d8, d8
493 ; CHECK-GI-NEXT: csel x0, xzr, x9, vs
494 ; CHECK-GI-NEXT: csel x1, xzr, x8, vs
495 ; CHECK-GI-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
496 ; CHECK-GI-NEXT: ret
497 %x = call i128 @llvm.fptosi.sat.i128.f64(double %f)
498 ret i128 %x
499 }
501 ;
502 ; 16-bit float to signed integer
503 ;
505 declare i1 @llvm.fptosi.sat.i1.f16 (half)
506 declare i8 @llvm.fptosi.sat.i8.f16 (half)
507 declare i13 @llvm.fptosi.sat.i13.f16 (half)
508 declare i16 @llvm.fptosi.sat.i16.f16 (half)
509 declare i19 @llvm.fptosi.sat.i19.f16 (half)
510 declare i32 @llvm.fptosi.sat.i32.f16 (half)
511 declare i50 @llvm.fptosi.sat.i50.f16 (half)
512 declare i64 @llvm.fptosi.sat.i64.f16 (half)
513 declare i100 @llvm.fptosi.sat.i100.f16(half)
514 declare i128 @llvm.fptosi.sat.i128.f16(half)
516 define i1 @test_signed_i1_f16(half %f) nounwind {
517 ; CHECK-SD-CVT-LABEL: test_signed_i1_f16:
518 ; CHECK-SD-CVT: // %bb.0:
519 ; CHECK-SD-CVT-NEXT: fcvt s0, h0
520 ; CHECK-SD-CVT-NEXT: fcvtzs w8, s0
521 ; CHECK-SD-CVT-NEXT: ands w8, w8, w8, asr #31
522 ; CHECK-SD-CVT-NEXT: csinv w8, w8, wzr, ge
523 ; CHECK-SD-CVT-NEXT: and w0, w8, #0x1
524 ; CHECK-SD-CVT-NEXT: ret
525 ;
526 ; CHECK-SD-FP16-LABEL: test_signed_i1_f16:
527 ; CHECK-SD-FP16: // %bb.0:
528 ; CHECK-SD-FP16-NEXT: fcvtzs w8, h0
529 ; CHECK-SD-FP16-NEXT: ands w8, w8, w8, asr #31
530 ; CHECK-SD-FP16-NEXT: csinv w8, w8, wzr, ge
531 ; CHECK-SD-FP16-NEXT: and w0, w8, #0x1
532 ; CHECK-SD-FP16-NEXT: ret
533 ;
534 ; CHECK-GI-CVT-LABEL: test_signed_i1_f16:
535 ; CHECK-GI-CVT: // %bb.0:
536 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
537 ; CHECK-GI-CVT-NEXT: fcvtzs w8, s0
538 ; CHECK-GI-CVT-NEXT: cmp w8, #0
539 ; CHECK-GI-CVT-NEXT: csel w8, w8, wzr, lt
540 ; CHECK-GI-CVT-NEXT: cmp w8, #0
541 ; CHECK-GI-CVT-NEXT: csinv w8, w8, wzr, ge
542 ; CHECK-GI-CVT-NEXT: and w0, w8, #0x1
543 ; CHECK-GI-CVT-NEXT: ret
544 ;
545 ; CHECK-GI-FP16-LABEL: test_signed_i1_f16:
546 ; CHECK-GI-FP16: // %bb.0:
547 ; CHECK-GI-FP16-NEXT: fcvtzs w8, h0
548 ; CHECK-GI-FP16-NEXT: cmp w8, #0
549 ; CHECK-GI-FP16-NEXT: csel w8, w8, wzr, lt
550 ; CHECK-GI-FP16-NEXT: cmp w8, #0
551 ; CHECK-GI-FP16-NEXT: csinv w8, w8, wzr, ge
552 ; CHECK-GI-FP16-NEXT: and w0, w8, #0x1
553 ; CHECK-GI-FP16-NEXT: ret
554 %x = call i1 @llvm.fptosi.sat.i1.f16(half %f)
555 ret i1 %x
556 }
558 define i8 @test_signed_i8_f16(half %f) nounwind {
559 ; CHECK-SD-CVT-LABEL: test_signed_i8_f16:
560 ; CHECK-SD-CVT: // %bb.0:
561 ; CHECK-SD-CVT-NEXT: fcvt s0, h0
562 ; CHECK-SD-CVT-NEXT: mov w8, #127 // =0x7f
563 ; CHECK-SD-CVT-NEXT: fcvtzs w9, s0
564 ; CHECK-SD-CVT-NEXT: cmp w9, #127
565 ; CHECK-SD-CVT-NEXT: csel w8, w9, w8, lt
566 ; CHECK-SD-CVT-NEXT: mov w9, #-128 // =0xffffff80
567 ; CHECK-SD-CVT-NEXT: cmn w8, #128
568 ; CHECK-SD-CVT-NEXT: csel w0, w8, w9, gt
569 ; CHECK-SD-CVT-NEXT: ret
570 ;
571 ; CHECK-SD-FP16-LABEL: test_signed_i8_f16:
572 ; CHECK-SD-FP16: // %bb.0:
573 ; CHECK-SD-FP16-NEXT: fcvtzs w9, h0
574 ; CHECK-SD-FP16-NEXT: mov w8, #127 // =0x7f
575 ; CHECK-SD-FP16-NEXT: cmp w9, #127
576 ; CHECK-SD-FP16-NEXT: csel w8, w9, w8, lt
577 ; CHECK-SD-FP16-NEXT: mov w9, #-128 // =0xffffff80
578 ; CHECK-SD-FP16-NEXT: cmn w8, #128
579 ; CHECK-SD-FP16-NEXT: csel w0, w8, w9, gt
580 ; CHECK-SD-FP16-NEXT: ret
581 ;
582 ; CHECK-GI-CVT-LABEL: test_signed_i8_f16:
583 ; CHECK-GI-CVT: // %bb.0:
584 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
585 ; CHECK-GI-CVT-NEXT: mov w8, #127 // =0x7f
586 ; CHECK-GI-CVT-NEXT: fcvtzs w9, s0
587 ; CHECK-GI-CVT-NEXT: cmp w9, #127
588 ; CHECK-GI-CVT-NEXT: csel w8, w9, w8, lt
589 ; CHECK-GI-CVT-NEXT: mov w9, #-128 // =0xffffff80
590 ; CHECK-GI-CVT-NEXT: cmn w8, #128
591 ; CHECK-GI-CVT-NEXT: csel w0, w8, w9, gt
592 ; CHECK-GI-CVT-NEXT: ret
593 ;
594 ; CHECK-GI-FP16-LABEL: test_signed_i8_f16:
595 ; CHECK-GI-FP16: // %bb.0:
596 ; CHECK-GI-FP16-NEXT: fcvtzs w9, h0
597 ; CHECK-GI-FP16-NEXT: mov w8, #127 // =0x7f
598 ; CHECK-GI-FP16-NEXT: cmp w9, #127
599 ; CHECK-GI-FP16-NEXT: csel w8, w9, w8, lt
600 ; CHECK-GI-FP16-NEXT: mov w9, #-128 // =0xffffff80
601 ; CHECK-GI-FP16-NEXT: cmn w8, #128
602 ; CHECK-GI-FP16-NEXT: csel w0, w8, w9, gt
603 ; CHECK-GI-FP16-NEXT: ret
604 %x = call i8 @llvm.fptosi.sat.i8.f16(half %f)
605 ret i8 %x
606 }
608 define i13 @test_signed_i13_f16(half %f) nounwind {
609 ; CHECK-SD-CVT-LABEL: test_signed_i13_f16:
610 ; CHECK-SD-CVT: // %bb.0:
611 ; CHECK-SD-CVT-NEXT: fcvt s0, h0
612 ; CHECK-SD-CVT-NEXT: mov w8, #4095 // =0xfff
613 ; CHECK-SD-CVT-NEXT: fcvtzs w9, s0
614 ; CHECK-SD-CVT-NEXT: cmp w9, #4095
615 ; CHECK-SD-CVT-NEXT: csel w8, w9, w8, lt
616 ; CHECK-SD-CVT-NEXT: mov w9, #-4096 // =0xfffff000
617 ; CHECK-SD-CVT-NEXT: cmn w8, #1, lsl #12 // =4096
618 ; CHECK-SD-CVT-NEXT: csel w0, w8, w9, gt
619 ; CHECK-SD-CVT-NEXT: ret
620 ;
621 ; CHECK-SD-FP16-LABEL: test_signed_i13_f16:
622 ; CHECK-SD-FP16: // %bb.0:
623 ; CHECK-SD-FP16-NEXT: fcvtzs w9, h0
624 ; CHECK-SD-FP16-NEXT: mov w8, #4095 // =0xfff
625 ; CHECK-SD-FP16-NEXT: cmp w9, #4095
626 ; CHECK-SD-FP16-NEXT: csel w8, w9, w8, lt
627 ; CHECK-SD-FP16-NEXT: mov w9, #-4096 // =0xfffff000
628 ; CHECK-SD-FP16-NEXT: cmn w8, #1, lsl #12 // =4096
629 ; CHECK-SD-FP16-NEXT: csel w0, w8, w9, gt
630 ; CHECK-SD-FP16-NEXT: ret
631 ;
632 ; CHECK-GI-CVT-LABEL: test_signed_i13_f16:
633 ; CHECK-GI-CVT: // %bb.0:
634 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
635 ; CHECK-GI-CVT-NEXT: mov w8, #4095 // =0xfff
636 ; CHECK-GI-CVT-NEXT: fcvtzs w9, s0
637 ; CHECK-GI-CVT-NEXT: cmp w9, #4095
638 ; CHECK-GI-CVT-NEXT: csel w8, w9, w8, lt
639 ; CHECK-GI-CVT-NEXT: mov w9, #-4096 // =0xfffff000
640 ; CHECK-GI-CVT-NEXT: cmn w8, #1, lsl #12 // =4096
641 ; CHECK-GI-CVT-NEXT: csel w0, w8, w9, gt
642 ; CHECK-GI-CVT-NEXT: ret
643 ;
644 ; CHECK-GI-FP16-LABEL: test_signed_i13_f16:
645 ; CHECK-GI-FP16: // %bb.0:
646 ; CHECK-GI-FP16-NEXT: fcvtzs w9, h0
647 ; CHECK-GI-FP16-NEXT: mov w8, #4095 // =0xfff
648 ; CHECK-GI-FP16-NEXT: cmp w9, #4095
649 ; CHECK-GI-FP16-NEXT: csel w8, w9, w8, lt
650 ; CHECK-GI-FP16-NEXT: mov w9, #-4096 // =0xfffff000
651 ; CHECK-GI-FP16-NEXT: cmn w8, #1, lsl #12 // =4096
652 ; CHECK-GI-FP16-NEXT: csel w0, w8, w9, gt
653 ; CHECK-GI-FP16-NEXT: ret
654 %x = call i13 @llvm.fptosi.sat.i13.f16(half %f)
655 ret i13 %x
656 }
658 define i16 @test_signed_i16_f16(half %f) nounwind {
659 ; CHECK-SD-CVT-LABEL: test_signed_i16_f16:
660 ; CHECK-SD-CVT: // %bb.0:
661 ; CHECK-SD-CVT-NEXT: fcvt s0, h0
662 ; CHECK-SD-CVT-NEXT: mov w9, #32767 // =0x7fff
663 ; CHECK-SD-CVT-NEXT: fcvtzs w8, s0
664 ; CHECK-SD-CVT-NEXT: cmp w8, w9
665 ; CHECK-SD-CVT-NEXT: csel w8, w8, w9, lt
666 ; CHECK-SD-CVT-NEXT: mov w9, #-32768 // =0xffff8000
667 ; CHECK-SD-CVT-NEXT: cmn w8, #8, lsl #12 // =32768
668 ; CHECK-SD-CVT-NEXT: csel w0, w8, w9, gt
669 ; CHECK-SD-CVT-NEXT: ret
670 ;
671 ; CHECK-SD-FP16-LABEL: test_signed_i16_f16:
672 ; CHECK-SD-FP16: // %bb.0:
673 ; CHECK-SD-FP16-NEXT: fcvtzs w8, h0
674 ; CHECK-SD-FP16-NEXT: mov w9, #32767 // =0x7fff
675 ; CHECK-SD-FP16-NEXT: cmp w8, w9
676 ; CHECK-SD-FP16-NEXT: csel w8, w8, w9, lt
677 ; CHECK-SD-FP16-NEXT: mov w9, #-32768 // =0xffff8000
678 ; CHECK-SD-FP16-NEXT: cmn w8, #8, lsl #12 // =32768
679 ; CHECK-SD-FP16-NEXT: csel w0, w8, w9, gt
680 ; CHECK-SD-FP16-NEXT: ret
681 ;
682 ; CHECK-GI-CVT-LABEL: test_signed_i16_f16:
683 ; CHECK-GI-CVT: // %bb.0:
684 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
685 ; CHECK-GI-CVT-NEXT: mov w9, #32767 // =0x7fff
686 ; CHECK-GI-CVT-NEXT: fcvtzs w8, s0
687 ; CHECK-GI-CVT-NEXT: cmp w8, w9
688 ; CHECK-GI-CVT-NEXT: csel w8, w8, w9, lt
689 ; CHECK-GI-CVT-NEXT: mov w9, #-32768 // =0xffff8000
690 ; CHECK-GI-CVT-NEXT: cmn w8, #8, lsl #12 // =32768
691 ; CHECK-GI-CVT-NEXT: csel w0, w8, w9, gt
692 ; CHECK-GI-CVT-NEXT: ret
693 ;
694 ; CHECK-GI-FP16-LABEL: test_signed_i16_f16:
695 ; CHECK-GI-FP16: // %bb.0:
696 ; CHECK-GI-FP16-NEXT: fcvtzs w8, h0
697 ; CHECK-GI-FP16-NEXT: mov w9, #32767 // =0x7fff
698 ; CHECK-GI-FP16-NEXT: cmp w8, w9
699 ; CHECK-GI-FP16-NEXT: csel w8, w8, w9, lt
700 ; CHECK-GI-FP16-NEXT: mov w9, #-32768 // =0xffff8000
701 ; CHECK-GI-FP16-NEXT: cmn w8, #8, lsl #12 // =32768
702 ; CHECK-GI-FP16-NEXT: csel w0, w8, w9, gt
703 ; CHECK-GI-FP16-NEXT: ret
704 %x = call i16 @llvm.fptosi.sat.i16.f16(half %f)
705 ret i16 %x
706 }
708 define i19 @test_signed_i19_f16(half %f) nounwind {
709 ; CHECK-SD-CVT-LABEL: test_signed_i19_f16:
710 ; CHECK-SD-CVT: // %bb.0:
711 ; CHECK-SD-CVT-NEXT: fcvt s0, h0
712 ; CHECK-SD-CVT-NEXT: mov w9, #262143 // =0x3ffff
713 ; CHECK-SD-CVT-NEXT: fcvtzs w8, s0
714 ; CHECK-SD-CVT-NEXT: cmp w8, w9
715 ; CHECK-SD-CVT-NEXT: csel w8, w8, w9, lt
716 ; CHECK-SD-CVT-NEXT: mov w9, #-262144 // =0xfffc0000
717 ; CHECK-SD-CVT-NEXT: cmn w8, #64, lsl #12 // =262144
718 ; CHECK-SD-CVT-NEXT: csel w0, w8, w9, gt
719 ; CHECK-SD-CVT-NEXT: ret
720 ;
721 ; CHECK-SD-FP16-LABEL: test_signed_i19_f16:
722 ; CHECK-SD-FP16: // %bb.0:
723 ; CHECK-SD-FP16-NEXT: fcvtzs w8, h0
724 ; CHECK-SD-FP16-NEXT: mov w9, #262143 // =0x3ffff
725 ; CHECK-SD-FP16-NEXT: cmp w8, w9
726 ; CHECK-SD-FP16-NEXT: csel w8, w8, w9, lt
727 ; CHECK-SD-FP16-NEXT: mov w9, #-262144 // =0xfffc0000
728 ; CHECK-SD-FP16-NEXT: cmn w8, #64, lsl #12 // =262144
729 ; CHECK-SD-FP16-NEXT: csel w0, w8, w9, gt
730 ; CHECK-SD-FP16-NEXT: ret
731 ;
732 ; CHECK-GI-CVT-LABEL: test_signed_i19_f16:
733 ; CHECK-GI-CVT: // %bb.0:
734 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
735 ; CHECK-GI-CVT-NEXT: mov w9, #262143 // =0x3ffff
736 ; CHECK-GI-CVT-NEXT: fcvtzs w8, s0
737 ; CHECK-GI-CVT-NEXT: cmp w8, w9
738 ; CHECK-GI-CVT-NEXT: csel w8, w8, w9, lt
739 ; CHECK-GI-CVT-NEXT: mov w9, #-262144 // =0xfffc0000
740 ; CHECK-GI-CVT-NEXT: cmn w8, #64, lsl #12 // =262144
741 ; CHECK-GI-CVT-NEXT: csel w0, w8, w9, gt
742 ; CHECK-GI-CVT-NEXT: ret
743 ;
744 ; CHECK-GI-FP16-LABEL: test_signed_i19_f16:
745 ; CHECK-GI-FP16: // %bb.0:
746 ; CHECK-GI-FP16-NEXT: fcvtzs w8, h0
747 ; CHECK-GI-FP16-NEXT: mov w9, #262143 // =0x3ffff
748 ; CHECK-GI-FP16-NEXT: cmp w8, w9
749 ; CHECK-GI-FP16-NEXT: csel w8, w8, w9, lt
750 ; CHECK-GI-FP16-NEXT: mov w9, #-262144 // =0xfffc0000
751 ; CHECK-GI-FP16-NEXT: cmn w8, #64, lsl #12 // =262144
752 ; CHECK-GI-FP16-NEXT: csel w0, w8, w9, gt
753 ; CHECK-GI-FP16-NEXT: ret
754 %x = call i19 @llvm.fptosi.sat.i19.f16(half %f)
755 ret i19 %x
756 }
758 define i32 @test_signed_i32_f16(half %f) nounwind {
759 ; CHECK-SD-CVT-LABEL: test_signed_i32_f16:
760 ; CHECK-SD-CVT: // %bb.0:
761 ; CHECK-SD-CVT-NEXT: fcvt s0, h0
762 ; CHECK-SD-CVT-NEXT: fcvtzs w0, s0
763 ; CHECK-SD-CVT-NEXT: ret
764 ;
765 ; CHECK-SD-FP16-LABEL: test_signed_i32_f16:
766 ; CHECK-SD-FP16: // %bb.0:
767 ; CHECK-SD-FP16-NEXT: fcvtzs w0, h0
768 ; CHECK-SD-FP16-NEXT: ret
769 ;
770 ; CHECK-GI-CVT-LABEL: test_signed_i32_f16:
771 ; CHECK-GI-CVT: // %bb.0:
772 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
773 ; CHECK-GI-CVT-NEXT: fcvtzs w0, s0
774 ; CHECK-GI-CVT-NEXT: ret
775 ;
776 ; CHECK-GI-FP16-LABEL: test_signed_i32_f16:
777 ; CHECK-GI-FP16: // %bb.0:
778 ; CHECK-GI-FP16-NEXT: fcvtzs w0, h0
779 ; CHECK-GI-FP16-NEXT: ret
780 %x = call i32 @llvm.fptosi.sat.i32.f16(half %f)
781 ret i32 %x
782 }
784 define i50 @test_signed_i50_f16(half %f) nounwind {
785 ; CHECK-SD-CVT-LABEL: test_signed_i50_f16:
786 ; CHECK-SD-CVT: // %bb.0:
787 ; CHECK-SD-CVT-NEXT: fcvt s0, h0
788 ; CHECK-SD-CVT-NEXT: mov x9, #562949953421311 // =0x1ffffffffffff
789 ; CHECK-SD-CVT-NEXT: fcvtzs x8, s0
790 ; CHECK-SD-CVT-NEXT: cmp x8, x9
791 ; CHECK-SD-CVT-NEXT: csel x8, x8, x9, lt
792 ; CHECK-SD-CVT-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
793 ; CHECK-SD-CVT-NEXT: cmp x8, x9
794 ; CHECK-SD-CVT-NEXT: csel x0, x8, x9, gt
795 ; CHECK-SD-CVT-NEXT: ret
796 ;
797 ; CHECK-SD-FP16-LABEL: test_signed_i50_f16:
798 ; CHECK-SD-FP16: // %bb.0:
799 ; CHECK-SD-FP16-NEXT: fcvtzs x8, h0
800 ; CHECK-SD-FP16-NEXT: mov x9, #562949953421311 // =0x1ffffffffffff
801 ; CHECK-SD-FP16-NEXT: cmp x8, x9
802 ; CHECK-SD-FP16-NEXT: csel x8, x8, x9, lt
803 ; CHECK-SD-FP16-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
804 ; CHECK-SD-FP16-NEXT: cmp x8, x9
805 ; CHECK-SD-FP16-NEXT: csel x0, x8, x9, gt
806 ; CHECK-SD-FP16-NEXT: ret
807 ;
808 ; CHECK-GI-CVT-LABEL: test_signed_i50_f16:
809 ; CHECK-GI-CVT: // %bb.0:
810 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
811 ; CHECK-GI-CVT-NEXT: mov x9, #562949953421311 // =0x1ffffffffffff
812 ; CHECK-GI-CVT-NEXT: mov x10, #-562949953421312 // =0xfffe000000000000
813 ; CHECK-GI-CVT-NEXT: fcvtzs x8, s0
814 ; CHECK-GI-CVT-NEXT: cmp x8, x9
815 ; CHECK-GI-CVT-NEXT: csel x8, x8, x9, lt
816 ; CHECK-GI-CVT-NEXT: cmp x8, x10
817 ; CHECK-GI-CVT-NEXT: csel x0, x8, x10, gt
818 ; CHECK-GI-CVT-NEXT: ret
819 ;
820 ; CHECK-GI-FP16-LABEL: test_signed_i50_f16:
821 ; CHECK-GI-FP16: // %bb.0:
822 ; CHECK-GI-FP16-NEXT: fcvtzs x8, h0
823 ; CHECK-GI-FP16-NEXT: mov x9, #562949953421311 // =0x1ffffffffffff
824 ; CHECK-GI-FP16-NEXT: mov x10, #-562949953421312 // =0xfffe000000000000
825 ; CHECK-GI-FP16-NEXT: cmp x8, x9
826 ; CHECK-GI-FP16-NEXT: csel x8, x8, x9, lt
827 ; CHECK-GI-FP16-NEXT: cmp x8, x10
828 ; CHECK-GI-FP16-NEXT: csel x0, x8, x10, gt
829 ; CHECK-GI-FP16-NEXT: ret
830 %x = call i50 @llvm.fptosi.sat.i50.f16(half %f)
831 ret i50 %x
832 }
834 define i64 @test_signed_i64_f16(half %f) nounwind {
835 ; CHECK-SD-CVT-LABEL: test_signed_i64_f16:
836 ; CHECK-SD-CVT: // %bb.0:
837 ; CHECK-SD-CVT-NEXT: fcvt s0, h0
838 ; CHECK-SD-CVT-NEXT: fcvtzs x0, s0
839 ; CHECK-SD-CVT-NEXT: ret
840 ;
841 ; CHECK-SD-FP16-LABEL: test_signed_i64_f16:
842 ; CHECK-SD-FP16: // %bb.0:
843 ; CHECK-SD-FP16-NEXT: fcvtzs x0, h0
844 ; CHECK-SD-FP16-NEXT: ret
845 ;
846 ; CHECK-GI-CVT-LABEL: test_signed_i64_f16:
847 ; CHECK-GI-CVT: // %bb.0:
848 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
849 ; CHECK-GI-CVT-NEXT: fcvtzs x0, s0
850 ; CHECK-GI-CVT-NEXT: ret
851 ;
852 ; CHECK-GI-FP16-LABEL: test_signed_i64_f16:
853 ; CHECK-GI-FP16: // %bb.0:
854 ; CHECK-GI-FP16-NEXT: fcvtzs x0, h0
855 ; CHECK-GI-FP16-NEXT: ret
856 %x = call i64 @llvm.fptosi.sat.i64.f16(half %f)
857 ret i64 %x
858 }
860 define i100 @test_signed_i100_f16(half %f) nounwind {
861 ; CHECK-SD-LABEL: test_signed_i100_f16:
862 ; CHECK-SD: // %bb.0:
863 ; CHECK-SD-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
864 ; CHECK-SD-NEXT: fcvt s8, h0
865 ; CHECK-SD-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
866 ; CHECK-SD-NEXT: fmov s0, s8
867 ; CHECK-SD-NEXT: bl __fixsfti
868 ; CHECK-SD-NEXT: movi v0.2s, #241, lsl #24
869 ; CHECK-SD-NEXT: mov w8, #1895825407 // =0x70ffffff
870 ; CHECK-SD-NEXT: mov x10, #34359738367 // =0x7ffffffff
871 ; CHECK-SD-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
872 ; CHECK-SD-NEXT: fcmp s8, s0
873 ; CHECK-SD-NEXT: fmov s0, w8
874 ; CHECK-SD-NEXT: mov x8, #-34359738368 // =0xfffffff800000000
875 ; CHECK-SD-NEXT: csel x9, xzr, x0, lt
876 ; CHECK-SD-NEXT: csel x8, x8, x1, lt
877 ; CHECK-SD-NEXT: fcmp s8, s0
878 ; CHECK-SD-NEXT: csel x8, x10, x8, gt
879 ; CHECK-SD-NEXT: csinv x9, x9, xzr, le
880 ; CHECK-SD-NEXT: fcmp s8, s8
881 ; CHECK-SD-NEXT: csel x0, xzr, x9, vs
882 ; CHECK-SD-NEXT: csel x1, xzr, x8, vs
883 ; CHECK-SD-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
884 ; CHECK-SD-NEXT: ret
885 ;
886 ; CHECK-GI-CVT-LABEL: test_signed_i100_f16:
887 ; CHECK-GI-CVT: // %bb.0:
888 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
889 ; CHECK-GI-CVT-NEXT: mov x1, xzr
890 ; CHECK-GI-CVT-NEXT: fcvtzs x0, s0
891 ; CHECK-GI-CVT-NEXT: ret
892 ;
893 ; CHECK-GI-FP16-LABEL: test_signed_i100_f16:
894 ; CHECK-GI-FP16: // %bb.0:
895 ; CHECK-GI-FP16-NEXT: fcvtzs x0, h0
896 ; CHECK-GI-FP16-NEXT: mov x1, xzr
897 ; CHECK-GI-FP16-NEXT: ret
898 %x = call i100 @llvm.fptosi.sat.i100.f16(half %f)
899 ret i100 %x
900 }
902 define i128 @test_signed_i128_f16(half %f) nounwind {
903 ; CHECK-SD-LABEL: test_signed_i128_f16:
904 ; CHECK-SD: // %bb.0:
905 ; CHECK-SD-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
906 ; CHECK-SD-NEXT: fcvt s8, h0
907 ; CHECK-SD-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
908 ; CHECK-SD-NEXT: fmov s0, s8
909 ; CHECK-SD-NEXT: bl __fixsfti
910 ; CHECK-SD-NEXT: movi v0.2s, #255, lsl #24
911 ; CHECK-SD-NEXT: mov w8, #2130706431 // =0x7effffff
912 ; CHECK-SD-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
913 ; CHECK-SD-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
914 ; CHECK-SD-NEXT: fcmp s8, s0
915 ; CHECK-SD-NEXT: fmov s0, w8
916 ; CHECK-SD-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
917 ; CHECK-SD-NEXT: csel x9, xzr, x0, lt
918 ; CHECK-SD-NEXT: csel x8, x8, x1, lt
919 ; CHECK-SD-NEXT: fcmp s8, s0
920 ; CHECK-SD-NEXT: csel x8, x10, x8, gt
921 ; CHECK-SD-NEXT: csinv x9, x9, xzr, le
922 ; CHECK-SD-NEXT: fcmp s8, s8
923 ; CHECK-SD-NEXT: csel x0, xzr, x9, vs
924 ; CHECK-SD-NEXT: csel x1, xzr, x8, vs
925 ; CHECK-SD-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
926 ; CHECK-SD-NEXT: ret
927 ;
928 ; CHECK-GI-CVT-LABEL: test_signed_i128_f16:
929 ; CHECK-GI-CVT: // %bb.0:
930 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
931 ; CHECK-GI-CVT-NEXT: mov x1, xzr
932 ; CHECK-GI-CVT-NEXT: fcvtzs x0, s0
933 ; CHECK-GI-CVT-NEXT: ret
934 ;
935 ; CHECK-GI-FP16-LABEL: test_signed_i128_f16:
936 ; CHECK-GI-FP16: // %bb.0:
937 ; CHECK-GI-FP16-NEXT: fcvtzs x0, h0
938 ; CHECK-GI-FP16-NEXT: mov x1, xzr
939 ; CHECK-GI-FP16-NEXT: ret
940 %x = call i128 @llvm.fptosi.sat.i128.f16(half %f)
941 ret i128 %x
942 }
944 define i32 @test_signed_f128_i32(fp128 %f) {
945 ; CHECK-SD-LABEL: test_signed_f128_i32:
946 ; CHECK-SD: // %bb.0:
947 ; CHECK-SD-NEXT: sub sp, sp, #32
948 ; CHECK-SD-NEXT: stp x30, x19, [sp, #16] // 16-byte Folded Spill
949 ; CHECK-SD-NEXT: .cfi_def_cfa_offset 32
950 ; CHECK-SD-NEXT: .cfi_offset w19, -8
951 ; CHECK-SD-NEXT: .cfi_offset w30, -16
952 ; CHECK-SD-NEXT: adrp x8, .LCPI30_0
953 ; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
954 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI30_0]
955 ; CHECK-SD-NEXT: bl __getf2
956 ; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
957 ; CHECK-SD-NEXT: mov w19, w0
958 ; CHECK-SD-NEXT: bl __fixtfsi
959 ; CHECK-SD-NEXT: cmp w19, #0
960 ; CHECK-SD-NEXT: mov w8, #-2147483648 // =0x80000000
961 ; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
962 ; CHECK-SD-NEXT: csel w19, w8, w0, lt
963 ; CHECK-SD-NEXT: adrp x8, .LCPI30_1
964 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
965 ; CHECK-SD-NEXT: bl __gttf2
966 ; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
967 ; CHECK-SD-NEXT: mov w8, #2147483647 // =0x7fffffff
968 ; CHECK-SD-NEXT: cmp w0, #0
969 ; CHECK-SD-NEXT: csel w19, w8, w19, gt
970 ; CHECK-SD-NEXT: mov v1.16b, v0.16b
971 ; CHECK-SD-NEXT: bl __unordtf2
972 ; CHECK-SD-NEXT: cmp w0, #0
973 ; CHECK-SD-NEXT: csel w0, wzr, w19, ne
974 ; CHECK-SD-NEXT: ldp x30, x19, [sp, #16] // 16-byte Folded Reload
975 ; CHECK-SD-NEXT: add sp, sp, #32
976 ; CHECK-SD-NEXT: ret
977 ;
978 ; CHECK-GI-LABEL: test_signed_f128_i32:
979 ; CHECK-GI: // %bb.0:
980 ; CHECK-GI-NEXT: sub sp, sp, #48
981 ; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
982 ; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
983 ; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
984 ; CHECK-GI-NEXT: .cfi_offset w19, -8
985 ; CHECK-GI-NEXT: .cfi_offset w20, -16
986 ; CHECK-GI-NEXT: .cfi_offset w30, -32
987 ; CHECK-GI-NEXT: adrp x8, .LCPI30_1
988 ; CHECK-GI-NEXT: str q0, [sp] // 16-byte Folded Spill
989 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
990 ; CHECK-GI-NEXT: bl __getf2
991 ; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Folded Reload
992 ; CHECK-GI-NEXT: cmp w0, #0
993 ; CHECK-GI-NEXT: mov x9, #-4603241769126068224 // =0xc01e000000000000
994 ; CHECK-GI-NEXT: fmov x8, d0
995 ; CHECK-GI-NEXT: csel x19, x8, xzr, lt
996 ; CHECK-GI-NEXT: mov x8, v0.d[1]
997 ; CHECK-GI-NEXT: mov v0.d[0], x19
998 ; CHECK-GI-NEXT: csel x20, x8, x9, lt
999 ; CHECK-GI-NEXT: adrp x8, .LCPI30_0
1000 ; CHECK-GI-NEXT: mov v0.d[1], x20
1001 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_0]
1002 ; CHECK-GI-NEXT: bl __gttf2
1003 ; CHECK-GI-NEXT: cmp w0, #0
1004 ; CHECK-GI-NEXT: csel x8, x19, xzr, gt
1005 ; CHECK-GI-NEXT: mov v0.d[0], x8
1006 ; CHECK-GI-NEXT: mov x8, #281474976448512 // =0xfffffffc0000
1007 ; CHECK-GI-NEXT: movk x8, #16413, lsl #48
1008 ; CHECK-GI-NEXT: csel x8, x20, x8, gt
1009 ; CHECK-GI-NEXT: mov v0.d[1], x8
1010 ; CHECK-GI-NEXT: bl __fixtfsi
1011 ; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Folded Reload
1012 ; CHECK-GI-NEXT: mov w19, w0
1013 ; CHECK-GI-NEXT: mov v1.16b, v0.16b
1014 ; CHECK-GI-NEXT: bl __unordtf2
1015 ; CHECK-GI-NEXT: cmp w0, #0
1016 ; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
1017 ; CHECK-GI-NEXT: csel w0, wzr, w19, ne
1018 ; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
1019 ; CHECK-GI-NEXT: add sp, sp, #48
1020 ; CHECK-GI-NEXT: ret
1021 %x = call i32 @llvm.fptosi.sat.i32.f128(fp128 %f)
1022 ret i32 %x
1023 }