1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3 ; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
5 declare <1 x i8> @llvm.sadd.sat.v1i8(<1 x i8>, <1 x i8>)
6 declare <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8>, <2 x i8>)
7 declare <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8>, <4 x i8>)
8 declare <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8>, <8 x i8>)
9 declare <12 x i8> @llvm.sadd.sat.v12i8(<12 x i8>, <12 x i8>)
10 declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>)
11 declare <32 x i8> @llvm.sadd.sat.v32i8(<32 x i8>, <32 x i8>)
12 declare <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8>, <64 x i8>)
14 declare <1 x i16> @llvm.sadd.sat.v1i16(<1 x i16>, <1 x i16>)
15 declare <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16>, <2 x i16>)
16 declare <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16>, <4 x i16>)
17 declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)
18 declare <12 x i16> @llvm.sadd.sat.v12i16(<12 x i16>, <12 x i16>)
19 declare <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16>, <16 x i16>)
20 declare <32 x i16> @llvm.sadd.sat.v32i16(<32 x i16>, <32 x i16>)
22 declare <16 x i1> @llvm.sadd.sat.v16i1(<16 x i1>, <16 x i1>)
23 declare <16 x i4> @llvm.sadd.sat.v16i4(<16 x i4>, <16 x i4>)
25 declare <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32>, <2 x i32>)
26 declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
27 declare <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32>, <8 x i32>)
28 declare <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32>, <16 x i32>)
29 declare <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64>, <2 x i64>)
30 declare <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64>, <4 x i64>)
31 declare <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64>, <8 x i64>)
33 declare <4 x i24> @llvm.sadd.sat.v4i24(<4 x i24>, <4 x i24>)
34 declare <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128>, <2 x i128>)
36 define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
39 ; CHECK-NEXT: sqadd v0.16b, v0.16b, v1.16b
41 %z = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
45 define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
46 ; CHECK-SD-LABEL: v32i8:
48 ; CHECK-SD-NEXT: sqadd v1.16b, v1.16b, v3.16b
49 ; CHECK-SD-NEXT: sqadd v0.16b, v0.16b, v2.16b
52 ; CHECK-GI-LABEL: v32i8:
54 ; CHECK-GI-NEXT: sqadd v0.16b, v0.16b, v2.16b
55 ; CHECK-GI-NEXT: sqadd v1.16b, v1.16b, v3.16b
57 %z = call <32 x i8> @llvm.sadd.sat.v32i8(<32 x i8> %x, <32 x i8> %y)
61 define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {
62 ; CHECK-SD-LABEL: v64i8:
64 ; CHECK-SD-NEXT: sqadd v2.16b, v2.16b, v6.16b
65 ; CHECK-SD-NEXT: sqadd v0.16b, v0.16b, v4.16b
66 ; CHECK-SD-NEXT: sqadd v1.16b, v1.16b, v5.16b
67 ; CHECK-SD-NEXT: sqadd v3.16b, v3.16b, v7.16b
70 ; CHECK-GI-LABEL: v64i8:
72 ; CHECK-GI-NEXT: sqadd v0.16b, v0.16b, v4.16b
73 ; CHECK-GI-NEXT: sqadd v1.16b, v1.16b, v5.16b
74 ; CHECK-GI-NEXT: sqadd v2.16b, v2.16b, v6.16b
75 ; CHECK-GI-NEXT: sqadd v3.16b, v3.16b, v7.16b
77 %z = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> %x, <64 x i8> %y)
81 define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
84 ; CHECK-NEXT: sqadd v0.8h, v0.8h, v1.8h
86 %z = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
90 define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind {
91 ; CHECK-SD-LABEL: v16i16:
93 ; CHECK-SD-NEXT: sqadd v1.8h, v1.8h, v3.8h
94 ; CHECK-SD-NEXT: sqadd v0.8h, v0.8h, v2.8h
97 ; CHECK-GI-LABEL: v16i16:
99 ; CHECK-GI-NEXT: sqadd v0.8h, v0.8h, v2.8h
100 ; CHECK-GI-NEXT: sqadd v1.8h, v1.8h, v3.8h
102 %z = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> %x, <16 x i16> %y)
106 define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind {
107 ; CHECK-SD-LABEL: v32i16:
108 ; CHECK-SD: // %bb.0:
109 ; CHECK-SD-NEXT: sqadd v2.8h, v2.8h, v6.8h
110 ; CHECK-SD-NEXT: sqadd v0.8h, v0.8h, v4.8h
111 ; CHECK-SD-NEXT: sqadd v1.8h, v1.8h, v5.8h
112 ; CHECK-SD-NEXT: sqadd v3.8h, v3.8h, v7.8h
115 ; CHECK-GI-LABEL: v32i16:
116 ; CHECK-GI: // %bb.0:
117 ; CHECK-GI-NEXT: sqadd v0.8h, v0.8h, v4.8h
118 ; CHECK-GI-NEXT: sqadd v1.8h, v1.8h, v5.8h
119 ; CHECK-GI-NEXT: sqadd v2.8h, v2.8h, v6.8h
120 ; CHECK-GI-NEXT: sqadd v3.8h, v3.8h, v7.8h
122 %z = call <32 x i16> @llvm.sadd.sat.v32i16(<32 x i16> %x, <32 x i16> %y)
126 define void @v8i8(ptr %px, ptr %py, ptr %pz) nounwind {
129 ; CHECK-NEXT: ldr d0, [x0]
130 ; CHECK-NEXT: ldr d1, [x1]
131 ; CHECK-NEXT: sqadd v0.8b, v0.8b, v1.8b
132 ; CHECK-NEXT: str d0, [x2]
134 %x = load <8 x i8>, ptr %px
135 %y = load <8 x i8>, ptr %py
136 %z = call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> %x, <8 x i8> %y)
137 store <8 x i8> %z, ptr %pz
141 define void @v4i8(ptr %px, ptr %py, ptr %pz) nounwind {
142 ; CHECK-SD-LABEL: v4i8:
143 ; CHECK-SD: // %bb.0:
144 ; CHECK-SD-NEXT: ldr s0, [x0]
145 ; CHECK-SD-NEXT: ldr s1, [x1]
146 ; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
147 ; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0
148 ; CHECK-SD-NEXT: shl v1.4h, v1.4h, #8
149 ; CHECK-SD-NEXT: shl v0.4h, v0.4h, #8
150 ; CHECK-SD-NEXT: sqadd v0.4h, v0.4h, v1.4h
151 ; CHECK-SD-NEXT: ushr v0.4h, v0.4h, #8
152 ; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v0.8b
153 ; CHECK-SD-NEXT: str s0, [x2]
156 ; CHECK-GI-LABEL: v4i8:
157 ; CHECK-GI: // %bb.0:
158 ; CHECK-GI-NEXT: ldr w8, [x0]
159 ; CHECK-GI-NEXT: ldr w9, [x1]
160 ; CHECK-GI-NEXT: fmov s0, w8
161 ; CHECK-GI-NEXT: fmov s1, w9
162 ; CHECK-GI-NEXT: mov b2, v0.b[1]
163 ; CHECK-GI-NEXT: mov v3.b[0], v0.b[0]
164 ; CHECK-GI-NEXT: mov b4, v1.b[1]
165 ; CHECK-GI-NEXT: mov v5.b[0], v1.b[0]
166 ; CHECK-GI-NEXT: mov v3.b[1], v2.b[0]
167 ; CHECK-GI-NEXT: mov b2, v0.b[2]
168 ; CHECK-GI-NEXT: mov b0, v0.b[3]
169 ; CHECK-GI-NEXT: mov v5.b[1], v4.b[0]
170 ; CHECK-GI-NEXT: mov b4, v1.b[2]
171 ; CHECK-GI-NEXT: mov b1, v1.b[3]
172 ; CHECK-GI-NEXT: mov v3.b[2], v2.b[0]
173 ; CHECK-GI-NEXT: mov v5.b[2], v4.b[0]
174 ; CHECK-GI-NEXT: mov v3.b[3], v0.b[0]
175 ; CHECK-GI-NEXT: mov v5.b[3], v1.b[0]
176 ; CHECK-GI-NEXT: sqadd v0.8b, v3.8b, v5.8b
177 ; CHECK-GI-NEXT: fmov w8, s0
178 ; CHECK-GI-NEXT: str w8, [x2]
180 %x = load <4 x i8>, ptr %px
181 %y = load <4 x i8>, ptr %py
182 %z = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> %x, <4 x i8> %y)
183 store <4 x i8> %z, ptr %pz
187 define void @v2i8(ptr %px, ptr %py, ptr %pz) nounwind {
188 ; CHECK-SD-LABEL: v2i8:
189 ; CHECK-SD: // %bb.0:
190 ; CHECK-SD-NEXT: ld1 { v0.b }[0], [x0]
191 ; CHECK-SD-NEXT: ld1 { v1.b }[0], [x1]
192 ; CHECK-SD-NEXT: add x8, x0, #1
193 ; CHECK-SD-NEXT: add x9, x1, #1
194 ; CHECK-SD-NEXT: ld1 { v0.b }[4], [x8]
195 ; CHECK-SD-NEXT: ld1 { v1.b }[4], [x9]
196 ; CHECK-SD-NEXT: shl v1.2s, v1.2s, #24
197 ; CHECK-SD-NEXT: shl v0.2s, v0.2s, #24
198 ; CHECK-SD-NEXT: sqadd v0.2s, v0.2s, v1.2s
199 ; CHECK-SD-NEXT: ushr v0.2s, v0.2s, #24
200 ; CHECK-SD-NEXT: mov w8, v0.s[1]
201 ; CHECK-SD-NEXT: fmov w9, s0
202 ; CHECK-SD-NEXT: strb w9, [x2]
203 ; CHECK-SD-NEXT: strb w8, [x2, #1]
206 ; CHECK-GI-LABEL: v2i8:
207 ; CHECK-GI: // %bb.0:
208 ; CHECK-GI-NEXT: ldr b0, [x0]
209 ; CHECK-GI-NEXT: ldr b1, [x1]
210 ; CHECK-GI-NEXT: add x8, x2, #1
211 ; CHECK-GI-NEXT: ldr b2, [x0, #1]
212 ; CHECK-GI-NEXT: ldr b3, [x1, #1]
213 ; CHECK-GI-NEXT: mov v0.b[0], v0.b[0]
214 ; CHECK-GI-NEXT: mov v1.b[0], v1.b[0]
215 ; CHECK-GI-NEXT: mov v0.b[1], v2.b[0]
216 ; CHECK-GI-NEXT: mov v1.b[1], v3.b[0]
217 ; CHECK-GI-NEXT: sqadd v0.8b, v0.8b, v1.8b
218 ; CHECK-GI-NEXT: st1 { v0.b }[0], [x2]
219 ; CHECK-GI-NEXT: st1 { v0.b }[1], [x8]
221 %x = load <2 x i8>, ptr %px
222 %y = load <2 x i8>, ptr %py
223 %z = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %x, <2 x i8> %y)
224 store <2 x i8> %z, ptr %pz
228 define void @v4i16(ptr %px, ptr %py, ptr %pz) nounwind {
229 ; CHECK-LABEL: v4i16:
231 ; CHECK-NEXT: ldr d0, [x0]
232 ; CHECK-NEXT: ldr d1, [x1]
233 ; CHECK-NEXT: sqadd v0.4h, v0.4h, v1.4h
234 ; CHECK-NEXT: str d0, [x2]
236 %x = load <4 x i16>, ptr %px
237 %y = load <4 x i16>, ptr %py
238 %z = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %x, <4 x i16> %y)
239 store <4 x i16> %z, ptr %pz
243 define void @v2i16(ptr %px, ptr %py, ptr %pz) nounwind {
244 ; CHECK-SD-LABEL: v2i16:
245 ; CHECK-SD: // %bb.0:
246 ; CHECK-SD-NEXT: ld1 { v0.h }[0], [x0]
247 ; CHECK-SD-NEXT: ld1 { v1.h }[0], [x1]
248 ; CHECK-SD-NEXT: add x8, x0, #2
249 ; CHECK-SD-NEXT: add x9, x1, #2
250 ; CHECK-SD-NEXT: ld1 { v0.h }[2], [x8]
251 ; CHECK-SD-NEXT: ld1 { v1.h }[2], [x9]
252 ; CHECK-SD-NEXT: shl v1.2s, v1.2s, #16
253 ; CHECK-SD-NEXT: shl v0.2s, v0.2s, #16
254 ; CHECK-SD-NEXT: sqadd v0.2s, v0.2s, v1.2s
255 ; CHECK-SD-NEXT: ushr v0.2s, v0.2s, #16
256 ; CHECK-SD-NEXT: mov w8, v0.s[1]
257 ; CHECK-SD-NEXT: fmov w9, s0
258 ; CHECK-SD-NEXT: strh w9, [x2]
259 ; CHECK-SD-NEXT: strh w8, [x2, #2]
262 ; CHECK-GI-LABEL: v2i16:
263 ; CHECK-GI: // %bb.0:
264 ; CHECK-GI-NEXT: ldr h0, [x0]
265 ; CHECK-GI-NEXT: ldr h1, [x1]
266 ; CHECK-GI-NEXT: add x8, x0, #2
267 ; CHECK-GI-NEXT: add x9, x1, #2
268 ; CHECK-GI-NEXT: ld1 { v0.h }[1], [x8]
269 ; CHECK-GI-NEXT: ld1 { v1.h }[1], [x9]
270 ; CHECK-GI-NEXT: add x8, x2, #2
271 ; CHECK-GI-NEXT: sqadd v0.4h, v0.4h, v1.4h
272 ; CHECK-GI-NEXT: str h0, [x2]
273 ; CHECK-GI-NEXT: st1 { v0.h }[1], [x8]
275 %x = load <2 x i16>, ptr %px
276 %y = load <2 x i16>, ptr %py
277 %z = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
278 store <2 x i16> %z, ptr %pz
282 define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind {
283 ; CHECK-LABEL: v12i8:
285 ; CHECK-NEXT: sqadd v0.16b, v0.16b, v1.16b
287 %z = call <12 x i8> @llvm.sadd.sat.v12i8(<12 x i8> %x, <12 x i8> %y)
291 define void @v12i16(ptr %px, ptr %py, ptr %pz) nounwind {
292 ; CHECK-SD-LABEL: v12i16:
293 ; CHECK-SD: // %bb.0:
294 ; CHECK-SD-NEXT: ldp q0, q3, [x1]
295 ; CHECK-SD-NEXT: ldp q1, q2, [x0]
296 ; CHECK-SD-NEXT: sqadd v0.8h, v1.8h, v0.8h
297 ; CHECK-SD-NEXT: sqadd v1.8h, v2.8h, v3.8h
298 ; CHECK-SD-NEXT: str q0, [x2]
299 ; CHECK-SD-NEXT: str d1, [x2, #16]
302 ; CHECK-GI-LABEL: v12i16:
303 ; CHECK-GI: // %bb.0:
304 ; CHECK-GI-NEXT: ldr q0, [x0]
305 ; CHECK-GI-NEXT: ldr q1, [x1]
306 ; CHECK-GI-NEXT: ldr d2, [x0, #16]
307 ; CHECK-GI-NEXT: ldr d3, [x1, #16]
308 ; CHECK-GI-NEXT: sqadd v0.8h, v0.8h, v1.8h
309 ; CHECK-GI-NEXT: sqadd v1.4h, v2.4h, v3.4h
310 ; CHECK-GI-NEXT: str q0, [x2]
311 ; CHECK-GI-NEXT: str d1, [x2, #16]
313 %x = load <12 x i16>, ptr %px
314 %y = load <12 x i16>, ptr %py
315 %z = call <12 x i16> @llvm.sadd.sat.v12i16(<12 x i16> %x, <12 x i16> %y)
316 store <12 x i16> %z, ptr %pz
320 define void @v1i8(ptr %px, ptr %py, ptr %pz) nounwind {
321 ; CHECK-SD-LABEL: v1i8:
322 ; CHECK-SD: // %bb.0:
323 ; CHECK-SD-NEXT: ldr b0, [x0]
324 ; CHECK-SD-NEXT: ldr b1, [x1]
325 ; CHECK-SD-NEXT: sqadd v0.8b, v0.8b, v1.8b
326 ; CHECK-SD-NEXT: st1 { v0.b }[0], [x2]
329 ; CHECK-GI-LABEL: v1i8:
330 ; CHECK-GI: // %bb.0:
331 ; CHECK-GI-NEXT: ldrsb w8, [x0]
332 ; CHECK-GI-NEXT: ldrsb w9, [x1]
333 ; CHECK-GI-NEXT: add w8, w8, w9
334 ; CHECK-GI-NEXT: sxtb w9, w8
335 ; CHECK-GI-NEXT: sbfx w10, w8, #7, #1
336 ; CHECK-GI-NEXT: sub w10, w10, #128
337 ; CHECK-GI-NEXT: cmp w8, w9
338 ; CHECK-GI-NEXT: csel w8, w10, w8, ne
339 ; CHECK-GI-NEXT: strb w8, [x2]
341 %x = load <1 x i8>, ptr %px
342 %y = load <1 x i8>, ptr %py
343 %z = call <1 x i8> @llvm.sadd.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
344 store <1 x i8> %z, ptr %pz
348 define void @v1i16(ptr %px, ptr %py, ptr %pz) nounwind {
349 ; CHECK-SD-LABEL: v1i16:
350 ; CHECK-SD: // %bb.0:
351 ; CHECK-SD-NEXT: ldr h0, [x0]
352 ; CHECK-SD-NEXT: ldr h1, [x1]
353 ; CHECK-SD-NEXT: sqadd v0.4h, v0.4h, v1.4h
354 ; CHECK-SD-NEXT: str h0, [x2]
357 ; CHECK-GI-LABEL: v1i16:
358 ; CHECK-GI: // %bb.0:
359 ; CHECK-GI-NEXT: ldrsh w8, [x0]
360 ; CHECK-GI-NEXT: ldrsh w9, [x1]
361 ; CHECK-GI-NEXT: add w8, w8, w9
362 ; CHECK-GI-NEXT: sxth w9, w8
363 ; CHECK-GI-NEXT: sbfx w10, w8, #15, #1
364 ; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
365 ; CHECK-GI-NEXT: cmp w8, w9
366 ; CHECK-GI-NEXT: csel w8, w10, w8, ne
367 ; CHECK-GI-NEXT: strh w8, [x2]
369 %x = load <1 x i16>, ptr %px
370 %y = load <1 x i16>, ptr %py
371 %z = call <1 x i16> @llvm.sadd.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
372 store <1 x i16> %z, ptr %pz
376 define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
377 ; CHECK-LABEL: v16i4:
379 ; CHECK-NEXT: shl v1.16b, v1.16b, #4
380 ; CHECK-NEXT: shl v0.16b, v0.16b, #4
381 ; CHECK-NEXT: sqadd v0.16b, v0.16b, v1.16b
382 ; CHECK-NEXT: sshr v0.16b, v0.16b, #4
384 %z = call <16 x i4> @llvm.sadd.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
388 define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
389 ; CHECK-LABEL: v16i1:
391 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
393 %z = call <16 x i1> @llvm.sadd.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
397 define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
398 ; CHECK-LABEL: v2i32:
400 ; CHECK-NEXT: sqadd v0.2s, v0.2s, v1.2s
402 %z = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %x, <2 x i32> %y)
406 define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
407 ; CHECK-LABEL: v4i32:
409 ; CHECK-NEXT: sqadd v0.4s, v0.4s, v1.4s
411 %z = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
415 define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
416 ; CHECK-SD-LABEL: v8i32:
417 ; CHECK-SD: // %bb.0:
418 ; CHECK-SD-NEXT: sqadd v1.4s, v1.4s, v3.4s
419 ; CHECK-SD-NEXT: sqadd v0.4s, v0.4s, v2.4s
422 ; CHECK-GI-LABEL: v8i32:
423 ; CHECK-GI: // %bb.0:
424 ; CHECK-GI-NEXT: sqadd v0.4s, v0.4s, v2.4s
425 ; CHECK-GI-NEXT: sqadd v1.4s, v1.4s, v3.4s
427 %z = call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> %x, <8 x i32> %y)
431 define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
432 ; CHECK-SD-LABEL: v16i32:
433 ; CHECK-SD: // %bb.0:
434 ; CHECK-SD-NEXT: sqadd v2.4s, v2.4s, v6.4s
435 ; CHECK-SD-NEXT: sqadd v0.4s, v0.4s, v4.4s
436 ; CHECK-SD-NEXT: sqadd v1.4s, v1.4s, v5.4s
437 ; CHECK-SD-NEXT: sqadd v3.4s, v3.4s, v7.4s
440 ; CHECK-GI-LABEL: v16i32:
441 ; CHECK-GI: // %bb.0:
442 ; CHECK-GI-NEXT: sqadd v0.4s, v0.4s, v4.4s
443 ; CHECK-GI-NEXT: sqadd v1.4s, v1.4s, v5.4s
444 ; CHECK-GI-NEXT: sqadd v2.4s, v2.4s, v6.4s
445 ; CHECK-GI-NEXT: sqadd v3.4s, v3.4s, v7.4s
447 %z = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %x, <16 x i32> %y)
451 define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
452 ; CHECK-LABEL: v2i64:
454 ; CHECK-NEXT: sqadd v0.2d, v0.2d, v1.2d
456 %z = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
460 define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
461 ; CHECK-SD-LABEL: v4i64:
462 ; CHECK-SD: // %bb.0:
463 ; CHECK-SD-NEXT: sqadd v1.2d, v1.2d, v3.2d
464 ; CHECK-SD-NEXT: sqadd v0.2d, v0.2d, v2.2d
467 ; CHECK-GI-LABEL: v4i64:
468 ; CHECK-GI: // %bb.0:
469 ; CHECK-GI-NEXT: sqadd v0.2d, v0.2d, v2.2d
470 ; CHECK-GI-NEXT: sqadd v1.2d, v1.2d, v3.2d
472 %z = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
476 define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
477 ; CHECK-SD-LABEL: v8i64:
478 ; CHECK-SD: // %bb.0:
479 ; CHECK-SD-NEXT: sqadd v2.2d, v2.2d, v6.2d
480 ; CHECK-SD-NEXT: sqadd v0.2d, v0.2d, v4.2d
481 ; CHECK-SD-NEXT: sqadd v1.2d, v1.2d, v5.2d
482 ; CHECK-SD-NEXT: sqadd v3.2d, v3.2d, v7.2d
485 ; CHECK-GI-LABEL: v8i64:
486 ; CHECK-GI: // %bb.0:
487 ; CHECK-GI-NEXT: sqadd v0.2d, v0.2d, v4.2d
488 ; CHECK-GI-NEXT: sqadd v1.2d, v1.2d, v5.2d
489 ; CHECK-GI-NEXT: sqadd v2.2d, v2.2d, v6.2d
490 ; CHECK-GI-NEXT: sqadd v3.2d, v3.2d, v7.2d
492 %z = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
496 define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
497 ; CHECK-LABEL: v2i128:
499 ; CHECK-NEXT: adds x8, x0, x4
500 ; CHECK-NEXT: adcs x9, x1, x5
501 ; CHECK-NEXT: asr x10, x9, #63
502 ; CHECK-NEXT: eor x11, x10, #0x8000000000000000
503 ; CHECK-NEXT: csel x0, x10, x8, vs
504 ; CHECK-NEXT: csel x1, x11, x9, vs
505 ; CHECK-NEXT: adds x8, x2, x6
506 ; CHECK-NEXT: adcs x9, x3, x7
507 ; CHECK-NEXT: asr x10, x9, #63
508 ; CHECK-NEXT: eor x11, x10, #0x8000000000000000
509 ; CHECK-NEXT: csel x2, x10, x8, vs
510 ; CHECK-NEXT: csel x3, x11, x9, vs
512 %z = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %x, <2 x i128> %y)