| blob | 4aff5a836e1a1877389e287a8ccdb2c3018b1970 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2 ; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3 ; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
5 define i8 @scmp.8.8(i8 %x, i8 %y) nounwind {
6 ; CHECK-SD-LABEL: scmp.8.8:
7 ; CHECK-SD: // %bb.0:
8 ; CHECK-SD-NEXT: sxtb w8, w0
9 ; CHECK-SD-NEXT: cmp w8, w1, sxtb
10 ; CHECK-SD-NEXT: cset w8, gt
11 ; CHECK-SD-NEXT: csinv w0, w8, wzr, ge
12 ; CHECK-SD-NEXT: ret
13 ;
14 ; CHECK-GI-LABEL: scmp.8.8:
15 ; CHECK-GI: // %bb.0:
16 ; CHECK-GI-NEXT: sxtb w8, w0
17 ; CHECK-GI-NEXT: sxtb w9, w1
18 ; CHECK-GI-NEXT: cmp w8, w9
19 ; CHECK-GI-NEXT: cset w8, gt
20 ; CHECK-GI-NEXT: csinv w0, w8, wzr, ge
21 ; CHECK-GI-NEXT: ret
22 %1 = call i8 @llvm.scmp(i8 %x, i8 %y)
23 ret i8 %1
24 }
26 define i8 @scmp.8.16(i16 %x, i16 %y) nounwind {
27 ; CHECK-SD-LABEL: scmp.8.16:
28 ; CHECK-SD: // %bb.0:
29 ; CHECK-SD-NEXT: sxth w8, w0
30 ; CHECK-SD-NEXT: cmp w8, w1, sxth
31 ; CHECK-SD-NEXT: cset w8, gt
32 ; CHECK-SD-NEXT: csinv w0, w8, wzr, ge
33 ; CHECK-SD-NEXT: ret
34 ;
35 ; CHECK-GI-LABEL: scmp.8.16:
36 ; CHECK-GI: // %bb.0:
37 ; CHECK-GI-NEXT: sxth w8, w0
38 ; CHECK-GI-NEXT: sxth w9, w1
39 ; CHECK-GI-NEXT: cmp w8, w9
40 ; CHECK-GI-NEXT: cset w8, gt
41 ; CHECK-GI-NEXT: csinv w0, w8, wzr, ge
42 ; CHECK-GI-NEXT: ret
43 %1 = call i8 @llvm.scmp(i16 %x, i16 %y)
44 ret i8 %1
45 }
47 define i8 @scmp.8.32(i32 %x, i32 %y) nounwind {
48 ; CHECK-LABEL: scmp.8.32:
49 ; CHECK: // %bb.0:
50 ; CHECK-NEXT: cmp w0, w1
51 ; CHECK-NEXT: cset w8, gt
52 ; CHECK-NEXT: csinv w0, w8, wzr, ge
53 ; CHECK-NEXT: ret
54 %1 = call i8 @llvm.scmp(i32 %x, i32 %y)
55 ret i8 %1
56 }
58 define i8 @scmp.8.64(i64 %x, i64 %y) nounwind {
59 ; CHECK-LABEL: scmp.8.64:
60 ; CHECK: // %bb.0:
61 ; CHECK-NEXT: cmp x0, x1
62 ; CHECK-NEXT: cset w8, gt
63 ; CHECK-NEXT: csinv w0, w8, wzr, ge
64 ; CHECK-NEXT: ret
65 %1 = call i8 @llvm.scmp(i64 %x, i64 %y)
66 ret i8 %1
67 }
69 define i8 @scmp.8.128(i128 %x, i128 %y) nounwind {
70 ; CHECK-SD-LABEL: scmp.8.128:
71 ; CHECK-SD: // %bb.0:
72 ; CHECK-SD-NEXT: cmp x2, x0
73 ; CHECK-SD-NEXT: sbcs xzr, x3, x1
74 ; CHECK-SD-NEXT: cset w8, lt
75 ; CHECK-SD-NEXT: cmp x0, x2
76 ; CHECK-SD-NEXT: sbcs xzr, x1, x3
77 ; CHECK-SD-NEXT: csinv w0, w8, wzr, ge
78 ; CHECK-SD-NEXT: ret
79 ;
80 ; CHECK-GI-LABEL: scmp.8.128:
81 ; CHECK-GI: // %bb.0:
82 ; CHECK-GI-NEXT: cmp x1, x3
83 ; CHECK-GI-NEXT: cset w8, gt
84 ; CHECK-GI-NEXT: cmp x0, x2
85 ; CHECK-GI-NEXT: cset w9, hi
86 ; CHECK-GI-NEXT: cmp x1, x3
87 ; CHECK-GI-NEXT: csel w8, w9, w8, eq
88 ; CHECK-GI-NEXT: tst w8, #0x1
89 ; CHECK-GI-NEXT: cset w8, ne
90 ; CHECK-GI-NEXT: cmp x1, x3
91 ; CHECK-GI-NEXT: cset w9, lt
92 ; CHECK-GI-NEXT: cmp x0, x2
93 ; CHECK-GI-NEXT: cset w10, lo
94 ; CHECK-GI-NEXT: cmp x1, x3
95 ; CHECK-GI-NEXT: csel w9, w10, w9, eq
96 ; CHECK-GI-NEXT: tst w9, #0x1
97 ; CHECK-GI-NEXT: csinv w0, w8, wzr, eq
98 ; CHECK-GI-NEXT: ret
99 %1 = call i8 @llvm.scmp(i128 %x, i128 %y)
100 ret i8 %1
101 }
103 define i32 @scmp.32.32(i32 %x, i32 %y) nounwind {
104 ; CHECK-LABEL: scmp.32.32:
105 ; CHECK: // %bb.0:
106 ; CHECK-NEXT: cmp w0, w1
107 ; CHECK-NEXT: cset w8, gt
108 ; CHECK-NEXT: csinv w0, w8, wzr, ge
109 ; CHECK-NEXT: ret
110 %1 = call i32 @llvm.scmp(i32 %x, i32 %y)
111 ret i32 %1
112 }
114 define i32 @scmp.32.64(i64 %x, i64 %y) nounwind {
115 ; CHECK-LABEL: scmp.32.64:
116 ; CHECK: // %bb.0:
117 ; CHECK-NEXT: cmp x0, x1
118 ; CHECK-NEXT: cset w8, gt
119 ; CHECK-NEXT: csinv w0, w8, wzr, ge
120 ; CHECK-NEXT: ret
121 %1 = call i32 @llvm.scmp(i64 %x, i64 %y)
122 ret i32 %1
123 }
125 define i64 @scmp.64.64(i64 %x, i64 %y) nounwind {
126 ; CHECK-LABEL: scmp.64.64:
127 ; CHECK: // %bb.0:
128 ; CHECK-NEXT: cmp x0, x1
129 ; CHECK-NEXT: cset x8, gt
130 ; CHECK-NEXT: csinv x0, x8, xzr, ge
131 ; CHECK-NEXT: ret
132 %1 = call i64 @llvm.scmp(i64 %x, i64 %y)
133 ret i64 %1
134 }
136 define <8 x i8> @s_v8i8(<8 x i8> %a, <8 x i8> %b) {
137 ; CHECK-SD-LABEL: s_v8i8:
138 ; CHECK-SD: // %bb.0: // %entry
139 ; CHECK-SD-NEXT: cmgt v2.8b, v0.8b, v1.8b
140 ; CHECK-SD-NEXT: cmgt v0.8b, v1.8b, v0.8b
141 ; CHECK-SD-NEXT: sub v0.8b, v0.8b, v2.8b
142 ; CHECK-SD-NEXT: ret
143 ;
144 ; CHECK-GI-LABEL: s_v8i8:
145 ; CHECK-GI: // %bb.0: // %entry
146 ; CHECK-GI-NEXT: movi v2.8b, #1
147 ; CHECK-GI-NEXT: cmgt v3.8b, v0.8b, v1.8b
148 ; CHECK-GI-NEXT: movi d4, #0xffffffffffffffff
149 ; CHECK-GI-NEXT: cmgt v0.8b, v1.8b, v0.8b
150 ; CHECK-GI-NEXT: and v2.8b, v2.8b, v3.8b
151 ; CHECK-GI-NEXT: bsl v0.8b, v4.8b, v2.8b
152 ; CHECK-GI-NEXT: ret
153 entry:
154 %c = call <8 x i8> @llvm.scmp(<8 x i8> %a, <8 x i8> %b)
155 ret <8 x i8> %c
156 }
158 define <16 x i8> @s_v16i8(<16 x i8> %a, <16 x i8> %b) {
159 ; CHECK-SD-LABEL: s_v16i8:
160 ; CHECK-SD: // %bb.0: // %entry
161 ; CHECK-SD-NEXT: cmgt v2.16b, v0.16b, v1.16b
162 ; CHECK-SD-NEXT: cmgt v0.16b, v1.16b, v0.16b
163 ; CHECK-SD-NEXT: sub v0.16b, v0.16b, v2.16b
164 ; CHECK-SD-NEXT: ret
165 ;
166 ; CHECK-GI-LABEL: s_v16i8:
167 ; CHECK-GI: // %bb.0: // %entry
168 ; CHECK-GI-NEXT: movi v2.16b, #1
169 ; CHECK-GI-NEXT: cmgt v3.16b, v0.16b, v1.16b
170 ; CHECK-GI-NEXT: movi v4.2d, #0xffffffffffffffff
171 ; CHECK-GI-NEXT: cmgt v0.16b, v1.16b, v0.16b
172 ; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b
173 ; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v2.16b
174 ; CHECK-GI-NEXT: ret
175 entry:
176 %c = call <16 x i8> @llvm.scmp(<16 x i8> %a, <16 x i8> %b)
177 ret <16 x i8> %c
178 }
180 define <4 x i16> @s_v4i16(<4 x i16> %a, <4 x i16> %b) {
181 ; CHECK-SD-LABEL: s_v4i16:
182 ; CHECK-SD: // %bb.0: // %entry
183 ; CHECK-SD-NEXT: cmgt v2.4h, v0.4h, v1.4h
184 ; CHECK-SD-NEXT: cmgt v0.4h, v1.4h, v0.4h
185 ; CHECK-SD-NEXT: sub v0.4h, v0.4h, v2.4h
186 ; CHECK-SD-NEXT: ret
187 ;
188 ; CHECK-GI-LABEL: s_v4i16:
189 ; CHECK-GI: // %bb.0: // %entry
190 ; CHECK-GI-NEXT: movi v2.4h, #1
191 ; CHECK-GI-NEXT: cmgt v3.4h, v0.4h, v1.4h
192 ; CHECK-GI-NEXT: movi d4, #0xffffffffffffffff
193 ; CHECK-GI-NEXT: cmgt v0.4h, v1.4h, v0.4h
194 ; CHECK-GI-NEXT: and v2.8b, v2.8b, v3.8b
195 ; CHECK-GI-NEXT: bsl v0.8b, v4.8b, v2.8b
196 ; CHECK-GI-NEXT: ret
197 entry:
198 %c = call <4 x i16> @llvm.scmp(<4 x i16> %a, <4 x i16> %b)
199 ret <4 x i16> %c
200 }
202 define <8 x i16> @s_v8i16(<8 x i16> %a, <8 x i16> %b) {
203 ; CHECK-SD-LABEL: s_v8i16:
204 ; CHECK-SD: // %bb.0: // %entry
205 ; CHECK-SD-NEXT: cmgt v2.8h, v0.8h, v1.8h
206 ; CHECK-SD-NEXT: cmgt v0.8h, v1.8h, v0.8h
207 ; CHECK-SD-NEXT: sub v0.8h, v0.8h, v2.8h
208 ; CHECK-SD-NEXT: ret
209 ;
210 ; CHECK-GI-LABEL: s_v8i16:
211 ; CHECK-GI: // %bb.0: // %entry
212 ; CHECK-GI-NEXT: movi v2.8h, #1
213 ; CHECK-GI-NEXT: cmgt v3.8h, v0.8h, v1.8h
214 ; CHECK-GI-NEXT: movi v4.2d, #0xffffffffffffffff
215 ; CHECK-GI-NEXT: cmgt v0.8h, v1.8h, v0.8h
216 ; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b
217 ; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v2.16b
218 ; CHECK-GI-NEXT: ret
219 entry:
220 %c = call <8 x i16> @llvm.scmp(<8 x i16> %a, <8 x i16> %b)
221 ret <8 x i16> %c
222 }
224 define <16 x i16> @s_v16i16(<16 x i16> %a, <16 x i16> %b) {
225 ; CHECK-SD-LABEL: s_v16i16:
226 ; CHECK-SD: // %bb.0: // %entry
227 ; CHECK-SD-NEXT: cmgt v4.8h, v1.8h, v3.8h
228 ; CHECK-SD-NEXT: cmgt v5.8h, v0.8h, v2.8h
229 ; CHECK-SD-NEXT: cmgt v0.8h, v2.8h, v0.8h
230 ; CHECK-SD-NEXT: cmgt v1.8h, v3.8h, v1.8h
231 ; CHECK-SD-NEXT: sub v0.8h, v0.8h, v5.8h
232 ; CHECK-SD-NEXT: sub v1.8h, v1.8h, v4.8h
233 ; CHECK-SD-NEXT: ret
234 ;
235 ; CHECK-GI-LABEL: s_v16i16:
236 ; CHECK-GI: // %bb.0: // %entry
237 ; CHECK-GI-NEXT: movi v4.8h, #1
238 ; CHECK-GI-NEXT: cmgt v5.8h, v0.8h, v2.8h
239 ; CHECK-GI-NEXT: cmgt v6.8h, v1.8h, v3.8h
240 ; CHECK-GI-NEXT: movi v7.2d, #0xffffffffffffffff
241 ; CHECK-GI-NEXT: cmgt v0.8h, v2.8h, v0.8h
242 ; CHECK-GI-NEXT: cmgt v1.8h, v3.8h, v1.8h
243 ; CHECK-GI-NEXT: and v5.16b, v4.16b, v5.16b
244 ; CHECK-GI-NEXT: and v4.16b, v4.16b, v6.16b
245 ; CHECK-GI-NEXT: bsl v0.16b, v7.16b, v5.16b
246 ; CHECK-GI-NEXT: bsl v1.16b, v7.16b, v4.16b
247 ; CHECK-GI-NEXT: ret
248 entry:
249 %c = call <16 x i16> @llvm.scmp(<16 x i16> %a, <16 x i16> %b)
250 ret <16 x i16> %c
251 }
253 define <2 x i32> @s_v2i32(<2 x i32> %a, <2 x i32> %b) {
254 ; CHECK-SD-LABEL: s_v2i32:
255 ; CHECK-SD: // %bb.0: // %entry
256 ; CHECK-SD-NEXT: cmgt v2.2s, v0.2s, v1.2s
257 ; CHECK-SD-NEXT: cmgt v0.2s, v1.2s, v0.2s
258 ; CHECK-SD-NEXT: sub v0.2s, v0.2s, v2.2s
259 ; CHECK-SD-NEXT: ret
260 ;
261 ; CHECK-GI-LABEL: s_v2i32:
262 ; CHECK-GI: // %bb.0: // %entry
263 ; CHECK-GI-NEXT: movi v2.2s, #1
264 ; CHECK-GI-NEXT: cmgt v3.2s, v0.2s, v1.2s
265 ; CHECK-GI-NEXT: movi d4, #0xffffffffffffffff
266 ; CHECK-GI-NEXT: cmgt v0.2s, v1.2s, v0.2s
267 ; CHECK-GI-NEXT: and v2.8b, v2.8b, v3.8b
268 ; CHECK-GI-NEXT: bsl v0.8b, v4.8b, v2.8b
269 ; CHECK-GI-NEXT: ret
270 entry:
271 %c = call <2 x i32> @llvm.scmp(<2 x i32> %a, <2 x i32> %b)
272 ret <2 x i32> %c
273 }
275 define <4 x i32> @s_v4i32(<4 x i32> %a, <4 x i32> %b) {
276 ; CHECK-SD-LABEL: s_v4i32:
277 ; CHECK-SD: // %bb.0: // %entry
278 ; CHECK-SD-NEXT: cmgt v2.4s, v0.4s, v1.4s
279 ; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
280 ; CHECK-SD-NEXT: sub v0.4s, v0.4s, v2.4s
281 ; CHECK-SD-NEXT: ret
282 ;
283 ; CHECK-GI-LABEL: s_v4i32:
284 ; CHECK-GI: // %bb.0: // %entry
285 ; CHECK-GI-NEXT: movi v2.4s, #1
286 ; CHECK-GI-NEXT: cmgt v3.4s, v0.4s, v1.4s
287 ; CHECK-GI-NEXT: movi v4.2d, #0xffffffffffffffff
288 ; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
289 ; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b
290 ; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v2.16b
291 ; CHECK-GI-NEXT: ret
292 entry:
293 %c = call <4 x i32> @llvm.scmp(<4 x i32> %a, <4 x i32> %b)
294 ret <4 x i32> %c
295 }
297 define <8 x i32> @s_v8i32(<8 x i32> %a, <8 x i32> %b) {
298 ; CHECK-SD-LABEL: s_v8i32:
299 ; CHECK-SD: // %bb.0: // %entry
300 ; CHECK-SD-NEXT: cmgt v4.4s, v1.4s, v3.4s
301 ; CHECK-SD-NEXT: cmgt v5.4s, v0.4s, v2.4s
302 ; CHECK-SD-NEXT: cmgt v0.4s, v2.4s, v0.4s
303 ; CHECK-SD-NEXT: cmgt v1.4s, v3.4s, v1.4s
304 ; CHECK-SD-NEXT: sub v0.4s, v0.4s, v5.4s
305 ; CHECK-SD-NEXT: sub v1.4s, v1.4s, v4.4s
306 ; CHECK-SD-NEXT: ret
307 ;
308 ; CHECK-GI-LABEL: s_v8i32:
309 ; CHECK-GI: // %bb.0: // %entry
310 ; CHECK-GI-NEXT: movi v4.4s, #1
311 ; CHECK-GI-NEXT: cmgt v5.4s, v0.4s, v2.4s
312 ; CHECK-GI-NEXT: cmgt v6.4s, v1.4s, v3.4s
313 ; CHECK-GI-NEXT: movi v7.2d, #0xffffffffffffffff
314 ; CHECK-GI-NEXT: cmgt v0.4s, v2.4s, v0.4s
315 ; CHECK-GI-NEXT: cmgt v1.4s, v3.4s, v1.4s
316 ; CHECK-GI-NEXT: and v5.16b, v4.16b, v5.16b
317 ; CHECK-GI-NEXT: and v4.16b, v4.16b, v6.16b
318 ; CHECK-GI-NEXT: bsl v0.16b, v7.16b, v5.16b
319 ; CHECK-GI-NEXT: bsl v1.16b, v7.16b, v4.16b
320 ; CHECK-GI-NEXT: ret
321 entry:
322 %c = call <8 x i32> @llvm.scmp(<8 x i32> %a, <8 x i32> %b)
323 ret <8 x i32> %c
324 }
326 define <2 x i64> @s_v2i64(<2 x i64> %a, <2 x i64> %b) {
327 ; CHECK-SD-LABEL: s_v2i64:
328 ; CHECK-SD: // %bb.0: // %entry
329 ; CHECK-SD-NEXT: cmgt v2.2d, v0.2d, v1.2d
330 ; CHECK-SD-NEXT: cmgt v0.2d, v1.2d, v0.2d
331 ; CHECK-SD-NEXT: sub v0.2d, v0.2d, v2.2d
332 ; CHECK-SD-NEXT: ret
333 ;
334 ; CHECK-GI-LABEL: s_v2i64:
335 ; CHECK-GI: // %bb.0: // %entry
336 ; CHECK-GI-NEXT: adrp x8, .LCPI16_0
337 ; CHECK-GI-NEXT: cmgt v2.2d, v0.2d, v1.2d
338 ; CHECK-GI-NEXT: movi v4.2d, #0xffffffffffffffff
339 ; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI16_0]
340 ; CHECK-GI-NEXT: cmgt v0.2d, v1.2d, v0.2d
341 ; CHECK-GI-NEXT: and v2.16b, v3.16b, v2.16b
342 ; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v2.16b
343 ; CHECK-GI-NEXT: ret
344 entry:
345 %c = call <2 x i64> @llvm.scmp(<2 x i64> %a, <2 x i64> %b)
346 ret <2 x i64> %c
347 }
349 define <4 x i64> @s_v4i64(<4 x i64> %a, <4 x i64> %b) {
350 ; CHECK-SD-LABEL: s_v4i64:
351 ; CHECK-SD: // %bb.0: // %entry
352 ; CHECK-SD-NEXT: cmgt v4.2d, v1.2d, v3.2d
353 ; CHECK-SD-NEXT: cmgt v5.2d, v0.2d, v2.2d
354 ; CHECK-SD-NEXT: cmgt v0.2d, v2.2d, v0.2d
355 ; CHECK-SD-NEXT: cmgt v1.2d, v3.2d, v1.2d
356 ; CHECK-SD-NEXT: sub v0.2d, v0.2d, v5.2d
357 ; CHECK-SD-NEXT: sub v1.2d, v1.2d, v4.2d
358 ; CHECK-SD-NEXT: ret
359 ;
360 ; CHECK-GI-LABEL: s_v4i64:
361 ; CHECK-GI: // %bb.0: // %entry
362 ; CHECK-GI-NEXT: adrp x8, .LCPI17_0
363 ; CHECK-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d
364 ; CHECK-GI-NEXT: cmgt v6.2d, v1.2d, v3.2d
365 ; CHECK-GI-NEXT: ldr q5, [x8, :lo12:.LCPI17_0]
366 ; CHECK-GI-NEXT: movi v7.2d, #0xffffffffffffffff
367 ; CHECK-GI-NEXT: cmgt v0.2d, v2.2d, v0.2d
368 ; CHECK-GI-NEXT: cmgt v1.2d, v3.2d, v1.2d
369 ; CHECK-GI-NEXT: and v4.16b, v5.16b, v4.16b
370 ; CHECK-GI-NEXT: and v5.16b, v5.16b, v6.16b
371 ; CHECK-GI-NEXT: bsl v0.16b, v7.16b, v4.16b
372 ; CHECK-GI-NEXT: bsl v1.16b, v7.16b, v5.16b
373 ; CHECK-GI-NEXT: ret
374 entry:
375 %c = call <4 x i64> @llvm.scmp(<4 x i64> %a, <4 x i64> %b)
376 ret <4 x i64> %c
377 }
379 define <16 x i8> @signOf_neon_scmp(<8 x i16> %s0_lo, <8 x i16> %s0_hi, <8 x i16> %s1_lo, <8 x i16> %s1_hi) {
380 ; CHECK-SD-LABEL: signOf_neon_scmp:
381 ; CHECK-SD: // %bb.0: // %entry
382 ; CHECK-SD-NEXT: cmgt v4.8h, v1.8h, v3.8h
383 ; CHECK-SD-NEXT: cmgt v1.8h, v3.8h, v1.8h
384 ; CHECK-SD-NEXT: cmgt v3.8h, v0.8h, v2.8h
385 ; CHECK-SD-NEXT: cmgt v0.8h, v2.8h, v0.8h
386 ; CHECK-SD-NEXT: sub v1.8h, v1.8h, v4.8h
387 ; CHECK-SD-NEXT: sub v0.8h, v0.8h, v3.8h
388 ; CHECK-SD-NEXT: uzp1 v0.16b, v0.16b, v1.16b
389 ; CHECK-SD-NEXT: ret
390 ;
391 ; CHECK-GI-LABEL: signOf_neon_scmp:
392 ; CHECK-GI: // %bb.0: // %entry
393 ; CHECK-GI-NEXT: cmgt v4.8h, v0.8h, v2.8h
394 ; CHECK-GI-NEXT: cmgt v5.8h, v1.8h, v3.8h
395 ; CHECK-GI-NEXT: cmgt v0.8h, v2.8h, v0.8h
396 ; CHECK-GI-NEXT: cmgt v1.8h, v3.8h, v1.8h
397 ; CHECK-GI-NEXT: movi v2.16b, #1
398 ; CHECK-GI-NEXT: movi v3.2d, #0xffffffffffffffff
399 ; CHECK-GI-NEXT: uzp1 v4.16b, v4.16b, v5.16b
400 ; CHECK-GI-NEXT: uzp1 v0.16b, v0.16b, v1.16b
401 ; CHECK-GI-NEXT: shl v1.16b, v4.16b, #7
402 ; CHECK-GI-NEXT: shl v0.16b, v0.16b, #7
403 ; CHECK-GI-NEXT: sshr v1.16b, v1.16b, #7
404 ; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7
405 ; CHECK-GI-NEXT: and v1.16b, v2.16b, v1.16b
406 ; CHECK-GI-NEXT: bsl v0.16b, v3.16b, v1.16b
407 ; CHECK-GI-NEXT: ret
408 entry:
409 %0 = shufflevector <8 x i16> %s0_lo, <8 x i16> %s0_hi, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
410 %1 = shufflevector <8 x i16> %s1_lo, <8 x i16> %s1_hi, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
411 %or.i = tail call <16 x i8> @llvm.scmp.v16i8.v16i16(<16 x i16> %0, <16 x i16> %1)
412 ret <16 x i8> %or.i
413 }