| blob | 8fd9ae98503665c8fcb64e69d204f64bdf391726 |
1 ; RUN: llc -mtriple=riscv32 -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
2 ; RUN: grep -v "Verify generated machine code" | \
3 ; RUN: FileCheck %s --check-prefixes=CHECK
4 ; RUN: llc -mtriple=riscv64 -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
5 ; RUN: grep -v "Verify generated machine code" | \
6 ; RUN: FileCheck %s --check-prefixes=CHECK,RV64
8 ; REQUIRES: asserts
10 ; CHECK-LABEL: Pass Arguments:
11 ; CHECK-NEXT: Target Library Information
12 ; CHECK-NEXT: Target Pass Configuration
13 ; CHECK-NEXT: Machine Module Information
14 ; CHECK-NEXT: Target Transform Information
15 ; CHECK-NEXT: Assumption Cache Tracker
16 ; CHECK-NEXT: Profile summary info
17 ; CHECK-NEXT: Type-Based Alias Analysis
18 ; CHECK-NEXT: Scoped NoAlias Alias Analysis
19 ; CHECK-NEXT: Create Garbage Collector Module Metadata
20 ; CHECK-NEXT: Machine Branch Probability Analysis
21 ; CHECK-NEXT: Default Regalloc Eviction Advisor
22 ; CHECK-NEXT: Default Regalloc Priority Advisor
23 ; CHECK-NEXT: ModulePass Manager
24 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
25 ; CHECK-NEXT: FunctionPass Manager
26 ; CHECK-NEXT: Expand large div/rem
27 ; CHECK-NEXT: Expand large fp convert
28 ; CHECK-NEXT: Expand Atomic instructions
29 ; CHECK-NEXT: RISC-V Zacas ABI fix
30 ; CHECK-NEXT: Dominator Tree Construction
31 ; CHECK-NEXT: Natural Loop Information
32 ; CHECK-NEXT: Canonicalize natural loops
33 ; CHECK-NEXT: Lazy Branch Probability Analysis
34 ; CHECK-NEXT: Lazy Block Frequency Analysis
35 ; CHECK-NEXT: Optimization Remark Emitter
36 ; CHECK-NEXT: Scalar Evolution Analysis
37 ; CHECK-NEXT: Loop Data Prefetch
38 ; CHECK-NEXT: RISC-V gather/scatter lowering
39 ; CHECK-NEXT: Interleaved Access Pass
40 ; CHECK-NEXT: RISC-V CodeGenPrepare
41 ; CHECK-NEXT: Module Verifier
42 ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
43 ; CHECK-NEXT: Canonicalize natural loops
44 ; CHECK-NEXT: Scalar Evolution Analysis
45 ; CHECK-NEXT: Loop Pass Manager
46 ; CHECK-NEXT: Canonicalize Freeze Instructions in Loops
47 ; CHECK-NEXT: Induction Variable Users
48 ; CHECK-NEXT: Loop Strength Reduction
49 ; CHECK-NEXT: Loop Terminator Folding
50 ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
51 ; CHECK-NEXT: Function Alias Analysis Results
52 ; CHECK-NEXT: Merge contiguous icmps into a memcmp
53 ; CHECK-NEXT: Natural Loop Information
54 ; CHECK-NEXT: Lazy Branch Probability Analysis
55 ; CHECK-NEXT: Lazy Block Frequency Analysis
56 ; CHECK-NEXT: Expand memcmp() to load/stores
57 ; CHECK-NEXT: Lower Garbage Collection Instructions
58 ; CHECK-NEXT: Shadow Stack GC Lowering
59 ; CHECK-NEXT: Remove unreachable blocks from the CFG
60 ; CHECK-NEXT: Natural Loop Information
61 ; CHECK-NEXT: Post-Dominator Tree Construction
62 ; CHECK-NEXT: Branch Probability Analysis
63 ; CHECK-NEXT: Block Frequency Analysis
64 ; CHECK-NEXT: Constant Hoisting
65 ; CHECK-NEXT: Replace intrinsics with calls to vector library
66 ; CHECK-NEXT: Partially inline calls to library functions
67 ; CHECK-NEXT: Instrument function entry/exit with calls to e.g. mcount() (post inlining)
68 ; CHECK-NEXT: Scalarize Masked Memory Intrinsics
69 ; CHECK-NEXT: Expand reduction intrinsics
70 ; CHECK-NEXT: Natural Loop Information
71 ; CHECK-NEXT: Type Promotion
72 ; CHECK-NEXT: CodeGen Prepare
73 ; CHECK-NEXT: Dominator Tree Construction
74 ; CHECK-NEXT: Exception handling preparation
75 ; CHECK-NEXT: A No-Op Barrier Pass
76 ; CHECK-NEXT: FunctionPass Manager
77 ; CHECK-NEXT: Merge internal globals
78 ; CHECK-NEXT: Dominator Tree Construction
79 ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
80 ; CHECK-NEXT: Function Alias Analysis Results
81 ; CHECK-NEXT: ObjC ARC contraction
82 ; CHECK-NEXT: Prepare callbr
83 ; CHECK-NEXT: Safe Stack instrumentation pass
84 ; CHECK-NEXT: Insert stack protectors
85 ; CHECK-NEXT: Module Verifier
86 ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
87 ; CHECK-NEXT: Function Alias Analysis Results
88 ; CHECK-NEXT: Natural Loop Information
89 ; CHECK-NEXT: Post-Dominator Tree Construction
90 ; CHECK-NEXT: Branch Probability Analysis
91 ; CHECK-NEXT: Assignment Tracking Analysis
92 ; CHECK-NEXT: Lazy Branch Probability Analysis
93 ; CHECK-NEXT: Lazy Block Frequency Analysis
94 ; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection
95 ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
96 ; CHECK-NEXT: RISC-V Vector Peephole Optimization
97 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
98 ; CHECK-NEXT: Early Tail Duplication
99 ; CHECK-NEXT: Optimize machine instruction PHIs
100 ; CHECK-NEXT: Slot index numbering
101 ; CHECK-NEXT: Merge disjoint stack slots
102 ; CHECK-NEXT: Local Stack Slot Allocation
103 ; CHECK-NEXT: Remove dead machine instructions
104 ; CHECK-NEXT: MachineDominator Tree Construction
105 ; CHECK-NEXT: Machine Natural Loop Construction
106 ; CHECK-NEXT: Machine Block Frequency Analysis
107 ; CHECK-NEXT: Early Machine Loop Invariant Code Motion
108 ; CHECK-NEXT: MachineDominator Tree Construction
109 ; CHECK-NEXT: Machine Block Frequency Analysis
110 ; CHECK-NEXT: Machine Common Subexpression Elimination
111 ; CHECK-NEXT: MachinePostDominator Tree Construction
112 ; CHECK-NEXT: Machine Cycle Info Analysis
113 ; CHECK-NEXT: Machine code sinking
114 ; CHECK-NEXT: Peephole Optimizations
115 ; CHECK-NEXT: Remove dead machine instructions
116 ; CHECK-NEXT: Machine Trace Metrics
117 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
118 ; CHECK-NEXT: Machine InstCombiner
119 ; RV64-NEXT: RISC-V Optimize W Instructions
120 ; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
121 ; CHECK-NEXT: RISC-V Merge Base Offset
122 ; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
123 ; CHECK-NEXT: RISC-V Insert Write VXRM Pass
124 ; CHECK-NEXT: RISC-V Landing Pad Setup
125 ; CHECK-NEXT: Detect Dead Lanes
126 ; CHECK-NEXT: Init Undef Pass
127 ; CHECK-NEXT: Process Implicit Definitions
128 ; CHECK-NEXT: Remove unreachable machine basic blocks
129 ; CHECK-NEXT: Live Variable Analysis
130 ; CHECK-NEXT: Eliminate PHI nodes for register allocation
131 ; CHECK-NEXT: Two-Address instruction pass
132 ; CHECK-NEXT: MachineDominator Tree Construction
133 ; CHECK-NEXT: Slot index numbering
134 ; CHECK-NEXT: Live Interval Analysis
135 ; CHECK-NEXT: Register Coalescer
136 ; CHECK-NEXT: Rename Disconnected Subregister Components
137 ; CHECK-NEXT: Machine Instruction Scheduler
138 ; CHECK-NEXT: Machine Block Frequency Analysis
139 ; CHECK-NEXT: Debug Variable Analysis
140 ; CHECK-NEXT: Live Stack Slot Analysis
141 ; CHECK-NEXT: Virtual Register Map
142 ; CHECK-NEXT: Live Register Matrix
143 ; CHECK-NEXT: Bundle Machine CFG Edges
144 ; CHECK-NEXT: Spill Code Placement Analysis
145 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
146 ; CHECK-NEXT: Machine Optimization Remark Emitter
147 ; CHECK-NEXT: Greedy Register Allocator
148 ; CHECK-NEXT: Virtual Register Rewriter
149 ; CHECK-NEXT: RISC-V Insert VSETVLI pass
150 ; CHECK-NEXT: RISC-V Dead register definitions
151 ; CHECK-NEXT: Virtual Register Map
152 ; CHECK-NEXT: Live Register Matrix
153 ; CHECK-NEXT: Greedy Register Allocator
154 ; CHECK-NEXT: Virtual Register Rewriter
155 ; CHECK-NEXT: Register Allocation Pass Scoring
156 ; CHECK-NEXT: Stack Slot Coloring
157 ; CHECK-NEXT: Machine Copy Propagation Pass
158 ; CHECK-NEXT: Machine Loop Invariant Code Motion
159 ; CHECK-NEXT: RISC-V Redundant Copy Elimination
160 ; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis
161 ; CHECK-NEXT: Fixup Statepoint Caller Saved
162 ; CHECK-NEXT: PostRA Machine Sink
163 ; CHECK-NEXT: MachineDominator Tree Construction
164 ; CHECK-NEXT: Machine Natural Loop Construction
165 ; CHECK-NEXT: Machine Block Frequency Analysis
166 ; CHECK-NEXT: MachinePostDominator Tree Construction
167 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
168 ; CHECK-NEXT: Machine Optimization Remark Emitter
169 ; CHECK-NEXT: Shrink Wrapping analysis
170 ; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
171 ; CHECK-NEXT: Machine Late Instructions Cleanup Pass
172 ; CHECK-NEXT: Control Flow Optimizer
173 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
174 ; CHECK-NEXT: Tail Duplication
175 ; CHECK-NEXT: Machine Copy Propagation Pass
176 ; CHECK-NEXT: Post-RA pseudo instruction expansion pass
177 ; CHECK-NEXT: RISC-V post-regalloc pseudo instruction expansion pass
178 ; CHECK-NEXT: Insert KCFI indirect call checks
179 ; CHECK-NEXT: MachineDominator Tree Construction
180 ; CHECK-NEXT: Machine Natural Loop Construction
181 ; CHECK-NEXT: PostRA Machine Instruction Scheduler
182 ; CHECK-NEXT: Analyze Machine Code For Garbage Collection
183 ; CHECK-NEXT: Machine Block Frequency Analysis
184 ; CHECK-NEXT: MachinePostDominator Tree Construction
185 ; CHECK-NEXT: Branch Probability Basic Block Placement
186 ; CHECK-NEXT: Insert fentry calls
187 ; CHECK-NEXT: Insert XRay ops
188 ; CHECK-NEXT: Implement the 'patchable-function' attribute
189 ; CHECK-NEXT: Machine Copy Propagation Pass
190 ; CHECK-NEXT: Branch relaxation pass
191 ; CHECK-NEXT: RISC-V Make Compressible
192 ; CHECK-NEXT: Contiguously Lay Out Funclets
193 ; CHECK-NEXT: Remove Loads Into Fake Uses
194 ; CHECK-NEXT: StackMap Liveness Analysis
195 ; CHECK-NEXT: Live DEBUG_VALUE analysis
196 ; CHECK-NEXT: Machine Sanitizer Binary Metadata
197 ; CHECK-NEXT: Machine Outliner
198 ; CHECK-NEXT: FunctionPass Manager
199 ; CHECK-NEXT: Insert CFI remember/restore state instructions
200 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
201 ; CHECK-NEXT: Machine Optimization Remark Emitter
202 ; CHECK-NEXT: Stack Frame Layout Analysis
203 ; CHECK-NEXT: RISC-V Zcmp move merging pass
204 ; CHECK-NEXT: RISC-V Zcmp Push/Pop optimization pass
205 ; CHECK-NEXT: RISC-V Indirect Branch Tracking
206 ; CHECK-NEXT: RISC-V pseudo instruction expansion pass
207 ; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
208 ; CHECK-NEXT: Unpack machine instruction bundles
209 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
210 ; CHECK-NEXT: Machine Optimization Remark Emitter
211 ; CHECK-NEXT: RISC-V Assembly Printer
212 ; CHECK-NEXT: Free MachineFunction