| blob | 541c9b4d40c7e15d9ac57f6ece2d67261fa96c75 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32I
3 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64I
4 ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32IF
5 ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IF
6 ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32-ILP32F
7 ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64-LP64F
8 ; RUN: llc -mtriple=riscv32 -mattr=+f,+zfhmin -target-abi=ilp32f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32-ILP32ZFHMIN
9 ; RUN: llc -mtriple=riscv64 -mattr=+f,+zfhmin -target-abi=lp64f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64-LP64ZFHMIN
11 ; Tests passing half arguments and returns without Zfh.
12 ; Covers with and without F extension and ilp32f/ilp64f
13 ; calling conventions.
15 define i32 @callee_half_in_regs(i32 %a, half %b) nounwind {
16 ; RV32I-LABEL: callee_half_in_regs:
17 ; RV32I: # %bb.0:
18 ; RV32I-NEXT: addi sp, sp, -16
19 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
20 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
21 ; RV32I-NEXT: mv s0, a0
22 ; RV32I-NEXT: slli a0, a1, 16
23 ; RV32I-NEXT: srli a0, a0, 16
24 ; RV32I-NEXT: call __extendhfsf2
25 ; RV32I-NEXT: call __fixsfsi
26 ; RV32I-NEXT: add a0, s0, a0
27 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
28 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
29 ; RV32I-NEXT: addi sp, sp, 16
30 ; RV32I-NEXT: ret
31 ;
32 ; RV64I-LABEL: callee_half_in_regs:
33 ; RV64I: # %bb.0:
34 ; RV64I-NEXT: addi sp, sp, -16
35 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
36 ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
37 ; RV64I-NEXT: mv s0, a0
38 ; RV64I-NEXT: slli a0, a1, 48
39 ; RV64I-NEXT: srli a0, a0, 48
40 ; RV64I-NEXT: call __extendhfsf2
41 ; RV64I-NEXT: call __fixsfdi
42 ; RV64I-NEXT: addw a0, s0, a0
43 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
44 ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
45 ; RV64I-NEXT: addi sp, sp, 16
46 ; RV64I-NEXT: ret
47 ;
48 ; RV32IF-LABEL: callee_half_in_regs:
49 ; RV32IF: # %bb.0:
50 ; RV32IF-NEXT: addi sp, sp, -16
51 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
52 ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
53 ; RV32IF-NEXT: mv s0, a0
54 ; RV32IF-NEXT: mv a0, a1
55 ; RV32IF-NEXT: call __extendhfsf2
56 ; RV32IF-NEXT: fmv.w.x fa5, a0
57 ; RV32IF-NEXT: fcvt.w.s a0, fa5, rtz
58 ; RV32IF-NEXT: add a0, s0, a0
59 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
60 ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
61 ; RV32IF-NEXT: addi sp, sp, 16
62 ; RV32IF-NEXT: ret
63 ;
64 ; RV64IF-LABEL: callee_half_in_regs:
65 ; RV64IF: # %bb.0:
66 ; RV64IF-NEXT: addi sp, sp, -16
67 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
68 ; RV64IF-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
69 ; RV64IF-NEXT: mv s0, a0
70 ; RV64IF-NEXT: mv a0, a1
71 ; RV64IF-NEXT: call __extendhfsf2
72 ; RV64IF-NEXT: fmv.w.x fa5, a0
73 ; RV64IF-NEXT: fcvt.l.s a0, fa5, rtz
74 ; RV64IF-NEXT: addw a0, s0, a0
75 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
76 ; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
77 ; RV64IF-NEXT: addi sp, sp, 16
78 ; RV64IF-NEXT: ret
79 ;
80 ; RV32-ILP32F-LABEL: callee_half_in_regs:
81 ; RV32-ILP32F: # %bb.0:
82 ; RV32-ILP32F-NEXT: addi sp, sp, -16
83 ; RV32-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
84 ; RV32-ILP32F-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
85 ; RV32-ILP32F-NEXT: mv s0, a0
86 ; RV32-ILP32F-NEXT: call __extendhfsf2
87 ; RV32-ILP32F-NEXT: fcvt.w.s a0, fa0, rtz
88 ; RV32-ILP32F-NEXT: add a0, s0, a0
89 ; RV32-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
90 ; RV32-ILP32F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
91 ; RV32-ILP32F-NEXT: addi sp, sp, 16
92 ; RV32-ILP32F-NEXT: ret
93 ;
94 ; RV64-LP64F-LABEL: callee_half_in_regs:
95 ; RV64-LP64F: # %bb.0:
96 ; RV64-LP64F-NEXT: addi sp, sp, -16
97 ; RV64-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
98 ; RV64-LP64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
99 ; RV64-LP64F-NEXT: mv s0, a0
100 ; RV64-LP64F-NEXT: call __extendhfsf2
101 ; RV64-LP64F-NEXT: fcvt.l.s a0, fa0, rtz
102 ; RV64-LP64F-NEXT: addw a0, s0, a0
103 ; RV64-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
104 ; RV64-LP64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
105 ; RV64-LP64F-NEXT: addi sp, sp, 16
106 ; RV64-LP64F-NEXT: ret
107 ;
108 ; RV32-ILP32ZFHMIN-LABEL: callee_half_in_regs:
109 ; RV32-ILP32ZFHMIN: # %bb.0:
110 ; RV32-ILP32ZFHMIN-NEXT: fcvt.s.h fa5, fa0
111 ; RV32-ILP32ZFHMIN-NEXT: fcvt.w.s a1, fa5, rtz
112 ; RV32-ILP32ZFHMIN-NEXT: add a0, a0, a1
113 ; RV32-ILP32ZFHMIN-NEXT: ret
114 ;
115 ; RV64-LP64ZFHMIN-LABEL: callee_half_in_regs:
116 ; RV64-LP64ZFHMIN: # %bb.0:
117 ; RV64-LP64ZFHMIN-NEXT: fcvt.s.h fa5, fa0
118 ; RV64-LP64ZFHMIN-NEXT: fcvt.w.s a1, fa5, rtz
119 ; RV64-LP64ZFHMIN-NEXT: addw a0, a0, a1
120 ; RV64-LP64ZFHMIN-NEXT: ret
121 %b_fptosi = fptosi half %b to i32
122 %1 = add i32 %a, %b_fptosi
123 ret i32 %1
124 }
126 define i32 @caller_half_in_regs() nounwind {
127 ; RV32I-LABEL: caller_half_in_regs:
128 ; RV32I: # %bb.0:
129 ; RV32I-NEXT: addi sp, sp, -16
130 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
131 ; RV32I-NEXT: li a0, 1
132 ; RV32I-NEXT: lui a1, 4
133 ; RV32I-NEXT: call callee_half_in_regs
134 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
135 ; RV32I-NEXT: addi sp, sp, 16
136 ; RV32I-NEXT: ret
137 ;
138 ; RV64I-LABEL: caller_half_in_regs:
139 ; RV64I: # %bb.0:
140 ; RV64I-NEXT: addi sp, sp, -16
141 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
142 ; RV64I-NEXT: li a0, 1
143 ; RV64I-NEXT: lui a1, 4
144 ; RV64I-NEXT: call callee_half_in_regs
145 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
146 ; RV64I-NEXT: addi sp, sp, 16
147 ; RV64I-NEXT: ret
148 ;
149 ; RV32IF-LABEL: caller_half_in_regs:
150 ; RV32IF: # %bb.0:
151 ; RV32IF-NEXT: addi sp, sp, -16
152 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
153 ; RV32IF-NEXT: li a0, 1
154 ; RV32IF-NEXT: lui a1, 1048564
155 ; RV32IF-NEXT: call callee_half_in_regs
156 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
157 ; RV32IF-NEXT: addi sp, sp, 16
158 ; RV32IF-NEXT: ret
159 ;
160 ; RV64IF-LABEL: caller_half_in_regs:
161 ; RV64IF: # %bb.0:
162 ; RV64IF-NEXT: addi sp, sp, -16
163 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
164 ; RV64IF-NEXT: li a0, 1
165 ; RV64IF-NEXT: lui a1, 1048564
166 ; RV64IF-NEXT: call callee_half_in_regs
167 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
168 ; RV64IF-NEXT: addi sp, sp, 16
169 ; RV64IF-NEXT: ret
170 ;
171 ; RV32-ILP32F-LABEL: caller_half_in_regs:
172 ; RV32-ILP32F: # %bb.0:
173 ; RV32-ILP32F-NEXT: addi sp, sp, -16
174 ; RV32-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
175 ; RV32-ILP32F-NEXT: lui a0, 1048564
176 ; RV32-ILP32F-NEXT: fmv.w.x fa0, a0
177 ; RV32-ILP32F-NEXT: li a0, 1
178 ; RV32-ILP32F-NEXT: call callee_half_in_regs
179 ; RV32-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
180 ; RV32-ILP32F-NEXT: addi sp, sp, 16
181 ; RV32-ILP32F-NEXT: ret
182 ;
183 ; RV64-LP64F-LABEL: caller_half_in_regs:
184 ; RV64-LP64F: # %bb.0:
185 ; RV64-LP64F-NEXT: addi sp, sp, -16
186 ; RV64-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
187 ; RV64-LP64F-NEXT: lui a0, 1048564
188 ; RV64-LP64F-NEXT: fmv.w.x fa0, a0
189 ; RV64-LP64F-NEXT: li a0, 1
190 ; RV64-LP64F-NEXT: call callee_half_in_regs
191 ; RV64-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
192 ; RV64-LP64F-NEXT: addi sp, sp, 16
193 ; RV64-LP64F-NEXT: ret
194 ;
195 ; RV32-ILP32ZFHMIN-LABEL: caller_half_in_regs:
196 ; RV32-ILP32ZFHMIN: # %bb.0:
197 ; RV32-ILP32ZFHMIN-NEXT: addi sp, sp, -16
198 ; RV32-ILP32ZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
199 ; RV32-ILP32ZFHMIN-NEXT: lui a0, 4
200 ; RV32-ILP32ZFHMIN-NEXT: fmv.h.x fa0, a0
201 ; RV32-ILP32ZFHMIN-NEXT: li a0, 1
202 ; RV32-ILP32ZFHMIN-NEXT: call callee_half_in_regs
203 ; RV32-ILP32ZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
204 ; RV32-ILP32ZFHMIN-NEXT: addi sp, sp, 16
205 ; RV32-ILP32ZFHMIN-NEXT: ret
206 ;
207 ; RV64-LP64ZFHMIN-LABEL: caller_half_in_regs:
208 ; RV64-LP64ZFHMIN: # %bb.0:
209 ; RV64-LP64ZFHMIN-NEXT: addi sp, sp, -16
210 ; RV64-LP64ZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
211 ; RV64-LP64ZFHMIN-NEXT: lui a0, 4
212 ; RV64-LP64ZFHMIN-NEXT: fmv.h.x fa0, a0
213 ; RV64-LP64ZFHMIN-NEXT: li a0, 1
214 ; RV64-LP64ZFHMIN-NEXT: call callee_half_in_regs
215 ; RV64-LP64ZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
216 ; RV64-LP64ZFHMIN-NEXT: addi sp, sp, 16
217 ; RV64-LP64ZFHMIN-NEXT: ret
218 %1 = call i32 @callee_half_in_regs(i32 1, half 2.0)
219 ret i32 %1
220 }
222 define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, half %i) nounwind {
223 ; RV32I-LABEL: callee_half_on_stack:
224 ; RV32I: # %bb.0:
225 ; RV32I-NEXT: addi sp, sp, -16
226 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
227 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
228 ; RV32I-NEXT: lhu a0, 16(sp)
229 ; RV32I-NEXT: mv s0, a7
230 ; RV32I-NEXT: call __extendhfsf2
231 ; RV32I-NEXT: call __fixsfsi
232 ; RV32I-NEXT: add a0, s0, a0
233 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
234 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
235 ; RV32I-NEXT: addi sp, sp, 16
236 ; RV32I-NEXT: ret
237 ;
238 ; RV64I-LABEL: callee_half_on_stack:
239 ; RV64I: # %bb.0:
240 ; RV64I-NEXT: addi sp, sp, -16
241 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
242 ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
243 ; RV64I-NEXT: lhu a0, 16(sp)
244 ; RV64I-NEXT: mv s0, a7
245 ; RV64I-NEXT: call __extendhfsf2
246 ; RV64I-NEXT: call __fixsfdi
247 ; RV64I-NEXT: addw a0, s0, a0
248 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
249 ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
250 ; RV64I-NEXT: addi sp, sp, 16
251 ; RV64I-NEXT: ret
252 ;
253 ; RV32IF-LABEL: callee_half_on_stack:
254 ; RV32IF: # %bb.0:
255 ; RV32IF-NEXT: addi sp, sp, -16
256 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
257 ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
258 ; RV32IF-NEXT: lhu a0, 16(sp)
259 ; RV32IF-NEXT: mv s0, a7
260 ; RV32IF-NEXT: call __extendhfsf2
261 ; RV32IF-NEXT: fmv.w.x fa5, a0
262 ; RV32IF-NEXT: fcvt.w.s a0, fa5, rtz
263 ; RV32IF-NEXT: add a0, s0, a0
264 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
265 ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
266 ; RV32IF-NEXT: addi sp, sp, 16
267 ; RV32IF-NEXT: ret
268 ;
269 ; RV64IF-LABEL: callee_half_on_stack:
270 ; RV64IF: # %bb.0:
271 ; RV64IF-NEXT: addi sp, sp, -16
272 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
273 ; RV64IF-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
274 ; RV64IF-NEXT: lhu a0, 16(sp)
275 ; RV64IF-NEXT: mv s0, a7
276 ; RV64IF-NEXT: call __extendhfsf2
277 ; RV64IF-NEXT: fmv.w.x fa5, a0
278 ; RV64IF-NEXT: fcvt.l.s a0, fa5, rtz
279 ; RV64IF-NEXT: addw a0, s0, a0
280 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
281 ; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
282 ; RV64IF-NEXT: addi sp, sp, 16
283 ; RV64IF-NEXT: ret
284 ;
285 ; RV32-ILP32F-LABEL: callee_half_on_stack:
286 ; RV32-ILP32F: # %bb.0:
287 ; RV32-ILP32F-NEXT: addi sp, sp, -16
288 ; RV32-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
289 ; RV32-ILP32F-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
290 ; RV32-ILP32F-NEXT: mv s0, a7
291 ; RV32-ILP32F-NEXT: call __extendhfsf2
292 ; RV32-ILP32F-NEXT: fcvt.w.s a0, fa0, rtz
293 ; RV32-ILP32F-NEXT: add a0, s0, a0
294 ; RV32-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
295 ; RV32-ILP32F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
296 ; RV32-ILP32F-NEXT: addi sp, sp, 16
297 ; RV32-ILP32F-NEXT: ret
298 ;
299 ; RV64-LP64F-LABEL: callee_half_on_stack:
300 ; RV64-LP64F: # %bb.0:
301 ; RV64-LP64F-NEXT: addi sp, sp, -16
302 ; RV64-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
303 ; RV64-LP64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
304 ; RV64-LP64F-NEXT: mv s0, a7
305 ; RV64-LP64F-NEXT: call __extendhfsf2
306 ; RV64-LP64F-NEXT: fcvt.l.s a0, fa0, rtz
307 ; RV64-LP64F-NEXT: addw a0, s0, a0
308 ; RV64-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
309 ; RV64-LP64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
310 ; RV64-LP64F-NEXT: addi sp, sp, 16
311 ; RV64-LP64F-NEXT: ret
312 ;
313 ; RV32-ILP32ZFHMIN-LABEL: callee_half_on_stack:
314 ; RV32-ILP32ZFHMIN: # %bb.0:
315 ; RV32-ILP32ZFHMIN-NEXT: fcvt.s.h fa5, fa0
316 ; RV32-ILP32ZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
317 ; RV32-ILP32ZFHMIN-NEXT: add a0, a7, a0
318 ; RV32-ILP32ZFHMIN-NEXT: ret
319 ;
320 ; RV64-LP64ZFHMIN-LABEL: callee_half_on_stack:
321 ; RV64-LP64ZFHMIN: # %bb.0:
322 ; RV64-LP64ZFHMIN-NEXT: fcvt.s.h fa5, fa0
323 ; RV64-LP64ZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
324 ; RV64-LP64ZFHMIN-NEXT: addw a0, a7, a0
325 ; RV64-LP64ZFHMIN-NEXT: ret
326 %1 = fptosi half %i to i32
327 %2 = add i32 %h, %1
328 ret i32 %2
329 }
331 define i32 @caller_half_on_stack() nounwind {
332 ; RV32I-LABEL: caller_half_on_stack:
333 ; RV32I: # %bb.0:
334 ; RV32I-NEXT: addi sp, sp, -16
335 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
336 ; RV32I-NEXT: lui a7, 5
337 ; RV32I-NEXT: li a0, 1
338 ; RV32I-NEXT: li a1, 2
339 ; RV32I-NEXT: li a2, 3
340 ; RV32I-NEXT: li a3, 4
341 ; RV32I-NEXT: li a4, 5
342 ; RV32I-NEXT: li a5, 6
343 ; RV32I-NEXT: li a6, 7
344 ; RV32I-NEXT: addi t0, a7, -1792
345 ; RV32I-NEXT: li a7, 8
346 ; RV32I-NEXT: sw t0, 0(sp)
347 ; RV32I-NEXT: call callee_half_on_stack
348 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
349 ; RV32I-NEXT: addi sp, sp, 16
350 ; RV32I-NEXT: ret
351 ;
352 ; RV64I-LABEL: caller_half_on_stack:
353 ; RV64I: # %bb.0:
354 ; RV64I-NEXT: addi sp, sp, -16
355 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
356 ; RV64I-NEXT: lui a7, 5
357 ; RV64I-NEXT: li a0, 1
358 ; RV64I-NEXT: li a1, 2
359 ; RV64I-NEXT: li a2, 3
360 ; RV64I-NEXT: li a3, 4
361 ; RV64I-NEXT: li a4, 5
362 ; RV64I-NEXT: li a5, 6
363 ; RV64I-NEXT: li a6, 7
364 ; RV64I-NEXT: addiw t0, a7, -1792
365 ; RV64I-NEXT: li a7, 8
366 ; RV64I-NEXT: sd t0, 0(sp)
367 ; RV64I-NEXT: call callee_half_on_stack
368 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
369 ; RV64I-NEXT: addi sp, sp, 16
370 ; RV64I-NEXT: ret
371 ;
372 ; RV32IF-LABEL: caller_half_on_stack:
373 ; RV32IF: # %bb.0:
374 ; RV32IF-NEXT: addi sp, sp, -16
375 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
376 ; RV32IF-NEXT: lui a7, 1048565
377 ; RV32IF-NEXT: li a0, 1
378 ; RV32IF-NEXT: li a1, 2
379 ; RV32IF-NEXT: li a2, 3
380 ; RV32IF-NEXT: li a3, 4
381 ; RV32IF-NEXT: li a4, 5
382 ; RV32IF-NEXT: li a5, 6
383 ; RV32IF-NEXT: li a6, 7
384 ; RV32IF-NEXT: addi t0, a7, -1792
385 ; RV32IF-NEXT: li a7, 8
386 ; RV32IF-NEXT: sw t0, 0(sp)
387 ; RV32IF-NEXT: call callee_half_on_stack
388 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
389 ; RV32IF-NEXT: addi sp, sp, 16
390 ; RV32IF-NEXT: ret
391 ;
392 ; RV64IF-LABEL: caller_half_on_stack:
393 ; RV64IF: # %bb.0:
394 ; RV64IF-NEXT: addi sp, sp, -16
395 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
396 ; RV64IF-NEXT: lui a7, 1048565
397 ; RV64IF-NEXT: li a0, 1
398 ; RV64IF-NEXT: li a1, 2
399 ; RV64IF-NEXT: li a2, 3
400 ; RV64IF-NEXT: li a3, 4
401 ; RV64IF-NEXT: li a4, 5
402 ; RV64IF-NEXT: li a5, 6
403 ; RV64IF-NEXT: li a6, 7
404 ; RV64IF-NEXT: addi t0, a7, -1792
405 ; RV64IF-NEXT: li a7, 8
406 ; RV64IF-NEXT: sw t0, 0(sp)
407 ; RV64IF-NEXT: call callee_half_on_stack
408 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
409 ; RV64IF-NEXT: addi sp, sp, 16
410 ; RV64IF-NEXT: ret
411 ;
412 ; RV32-ILP32F-LABEL: caller_half_on_stack:
413 ; RV32-ILP32F: # %bb.0:
414 ; RV32-ILP32F-NEXT: addi sp, sp, -16
415 ; RV32-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
416 ; RV32-ILP32F-NEXT: lui a4, %hi(.LCPI3_0)
417 ; RV32-ILP32F-NEXT: li a0, 1
418 ; RV32-ILP32F-NEXT: li a1, 2
419 ; RV32-ILP32F-NEXT: li a2, 3
420 ; RV32-ILP32F-NEXT: li a3, 4
421 ; RV32-ILP32F-NEXT: flw fa0, %lo(.LCPI3_0)(a4)
422 ; RV32-ILP32F-NEXT: li a4, 5
423 ; RV32-ILP32F-NEXT: li a5, 6
424 ; RV32-ILP32F-NEXT: li a6, 7
425 ; RV32-ILP32F-NEXT: li a7, 8
426 ; RV32-ILP32F-NEXT: call callee_half_on_stack
427 ; RV32-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
428 ; RV32-ILP32F-NEXT: addi sp, sp, 16
429 ; RV32-ILP32F-NEXT: ret
430 ;
431 ; RV64-LP64F-LABEL: caller_half_on_stack:
432 ; RV64-LP64F: # %bb.0:
433 ; RV64-LP64F-NEXT: addi sp, sp, -16
434 ; RV64-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
435 ; RV64-LP64F-NEXT: lui a4, %hi(.LCPI3_0)
436 ; RV64-LP64F-NEXT: li a0, 1
437 ; RV64-LP64F-NEXT: li a1, 2
438 ; RV64-LP64F-NEXT: li a2, 3
439 ; RV64-LP64F-NEXT: li a3, 4
440 ; RV64-LP64F-NEXT: flw fa0, %lo(.LCPI3_0)(a4)
441 ; RV64-LP64F-NEXT: li a4, 5
442 ; RV64-LP64F-NEXT: li a5, 6
443 ; RV64-LP64F-NEXT: li a6, 7
444 ; RV64-LP64F-NEXT: li a7, 8
445 ; RV64-LP64F-NEXT: call callee_half_on_stack
446 ; RV64-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
447 ; RV64-LP64F-NEXT: addi sp, sp, 16
448 ; RV64-LP64F-NEXT: ret
449 ;
450 ; RV32-ILP32ZFHMIN-LABEL: caller_half_on_stack:
451 ; RV32-ILP32ZFHMIN: # %bb.0:
452 ; RV32-ILP32ZFHMIN-NEXT: addi sp, sp, -16
453 ; RV32-ILP32ZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
454 ; RV32-ILP32ZFHMIN-NEXT: lui a4, %hi(.LCPI3_0)
455 ; RV32-ILP32ZFHMIN-NEXT: li a0, 1
456 ; RV32-ILP32ZFHMIN-NEXT: li a1, 2
457 ; RV32-ILP32ZFHMIN-NEXT: li a2, 3
458 ; RV32-ILP32ZFHMIN-NEXT: li a3, 4
459 ; RV32-ILP32ZFHMIN-NEXT: flh fa0, %lo(.LCPI3_0)(a4)
460 ; RV32-ILP32ZFHMIN-NEXT: li a4, 5
461 ; RV32-ILP32ZFHMIN-NEXT: li a5, 6
462 ; RV32-ILP32ZFHMIN-NEXT: li a6, 7
463 ; RV32-ILP32ZFHMIN-NEXT: li a7, 8
464 ; RV32-ILP32ZFHMIN-NEXT: call callee_half_on_stack
465 ; RV32-ILP32ZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
466 ; RV32-ILP32ZFHMIN-NEXT: addi sp, sp, 16
467 ; RV32-ILP32ZFHMIN-NEXT: ret
468 ;
469 ; RV64-LP64ZFHMIN-LABEL: caller_half_on_stack:
470 ; RV64-LP64ZFHMIN: # %bb.0:
471 ; RV64-LP64ZFHMIN-NEXT: addi sp, sp, -16
472 ; RV64-LP64ZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
473 ; RV64-LP64ZFHMIN-NEXT: lui a4, %hi(.LCPI3_0)
474 ; RV64-LP64ZFHMIN-NEXT: li a0, 1
475 ; RV64-LP64ZFHMIN-NEXT: li a1, 2
476 ; RV64-LP64ZFHMIN-NEXT: li a2, 3
477 ; RV64-LP64ZFHMIN-NEXT: li a3, 4
478 ; RV64-LP64ZFHMIN-NEXT: flh fa0, %lo(.LCPI3_0)(a4)
479 ; RV64-LP64ZFHMIN-NEXT: li a4, 5
480 ; RV64-LP64ZFHMIN-NEXT: li a5, 6
481 ; RV64-LP64ZFHMIN-NEXT: li a6, 7
482 ; RV64-LP64ZFHMIN-NEXT: li a7, 8
483 ; RV64-LP64ZFHMIN-NEXT: call callee_half_on_stack
484 ; RV64-LP64ZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
485 ; RV64-LP64ZFHMIN-NEXT: addi sp, sp, 16
486 ; RV64-LP64ZFHMIN-NEXT: ret
487 %1 = call i32 @callee_half_on_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, half 10.0)
488 ret i32 %1
489 }
491 define half @callee_half_ret() nounwind {
492 ; RV32I-LABEL: callee_half_ret:
493 ; RV32I: # %bb.0:
494 ; RV32I-NEXT: li a0, 15
495 ; RV32I-NEXT: slli a0, a0, 10
496 ; RV32I-NEXT: ret
497 ;
498 ; RV64I-LABEL: callee_half_ret:
499 ; RV64I: # %bb.0:
500 ; RV64I-NEXT: li a0, 15
501 ; RV64I-NEXT: slli a0, a0, 10
502 ; RV64I-NEXT: ret
503 ;
504 ; RV32IF-LABEL: callee_half_ret:
505 ; RV32IF: # %bb.0:
506 ; RV32IF-NEXT: lui a0, 1048564
507 ; RV32IF-NEXT: addi a0, a0, -1024
508 ; RV32IF-NEXT: ret
509 ;
510 ; RV64IF-LABEL: callee_half_ret:
511 ; RV64IF: # %bb.0:
512 ; RV64IF-NEXT: lui a0, 1048564
513 ; RV64IF-NEXT: addiw a0, a0, -1024
514 ; RV64IF-NEXT: ret
515 ;
516 ; RV32-ILP32F-LABEL: callee_half_ret:
517 ; RV32-ILP32F: # %bb.0:
518 ; RV32-ILP32F-NEXT: lui a0, %hi(.LCPI4_0)
519 ; RV32-ILP32F-NEXT: flw fa0, %lo(.LCPI4_0)(a0)
520 ; RV32-ILP32F-NEXT: ret
521 ;
522 ; RV64-LP64F-LABEL: callee_half_ret:
523 ; RV64-LP64F: # %bb.0:
524 ; RV64-LP64F-NEXT: lui a0, %hi(.LCPI4_0)
525 ; RV64-LP64F-NEXT: flw fa0, %lo(.LCPI4_0)(a0)
526 ; RV64-LP64F-NEXT: ret
527 ;
528 ; RV32-ILP32ZFHMIN-LABEL: callee_half_ret:
529 ; RV32-ILP32ZFHMIN: # %bb.0:
530 ; RV32-ILP32ZFHMIN-NEXT: lui a0, %hi(.LCPI4_0)
531 ; RV32-ILP32ZFHMIN-NEXT: flh fa0, %lo(.LCPI4_0)(a0)
532 ; RV32-ILP32ZFHMIN-NEXT: ret
533 ;
534 ; RV64-LP64ZFHMIN-LABEL: callee_half_ret:
535 ; RV64-LP64ZFHMIN: # %bb.0:
536 ; RV64-LP64ZFHMIN-NEXT: lui a0, %hi(.LCPI4_0)
537 ; RV64-LP64ZFHMIN-NEXT: flh fa0, %lo(.LCPI4_0)(a0)
538 ; RV64-LP64ZFHMIN-NEXT: ret
539 ret half 1.0
540 }
542 define i32 @caller_half_ret() nounwind {
543 ; RV32I-LABEL: caller_half_ret:
544 ; RV32I: # %bb.0:
545 ; RV32I-NEXT: addi sp, sp, -16
546 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
547 ; RV32I-NEXT: call callee_half_ret
548 ; RV32I-NEXT: slli a0, a0, 16
549 ; RV32I-NEXT: srli a0, a0, 16
550 ; RV32I-NEXT: call __extendhfsf2
551 ; RV32I-NEXT: call __fixsfsi
552 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
553 ; RV32I-NEXT: addi sp, sp, 16
554 ; RV32I-NEXT: ret
555 ;
556 ; RV64I-LABEL: caller_half_ret:
557 ; RV64I: # %bb.0:
558 ; RV64I-NEXT: addi sp, sp, -16
559 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
560 ; RV64I-NEXT: call callee_half_ret
561 ; RV64I-NEXT: slli a0, a0, 48
562 ; RV64I-NEXT: srli a0, a0, 48
563 ; RV64I-NEXT: call __extendhfsf2
564 ; RV64I-NEXT: call __fixsfdi
565 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
566 ; RV64I-NEXT: addi sp, sp, 16
567 ; RV64I-NEXT: ret
568 ;
569 ; RV32IF-LABEL: caller_half_ret:
570 ; RV32IF: # %bb.0:
571 ; RV32IF-NEXT: addi sp, sp, -16
572 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
573 ; RV32IF-NEXT: call callee_half_ret
574 ; RV32IF-NEXT: call __extendhfsf2
575 ; RV32IF-NEXT: fmv.w.x fa5, a0
576 ; RV32IF-NEXT: fcvt.w.s a0, fa5, rtz
577 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
578 ; RV32IF-NEXT: addi sp, sp, 16
579 ; RV32IF-NEXT: ret
580 ;
581 ; RV64IF-LABEL: caller_half_ret:
582 ; RV64IF: # %bb.0:
583 ; RV64IF-NEXT: addi sp, sp, -16
584 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
585 ; RV64IF-NEXT: call callee_half_ret
586 ; RV64IF-NEXT: call __extendhfsf2
587 ; RV64IF-NEXT: fmv.w.x fa5, a0
588 ; RV64IF-NEXT: fcvt.l.s a0, fa5, rtz
589 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
590 ; RV64IF-NEXT: addi sp, sp, 16
591 ; RV64IF-NEXT: ret
592 ;
593 ; RV32-ILP32F-LABEL: caller_half_ret:
594 ; RV32-ILP32F: # %bb.0:
595 ; RV32-ILP32F-NEXT: addi sp, sp, -16
596 ; RV32-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
597 ; RV32-ILP32F-NEXT: call callee_half_ret
598 ; RV32-ILP32F-NEXT: call __extendhfsf2
599 ; RV32-ILP32F-NEXT: fcvt.w.s a0, fa0, rtz
600 ; RV32-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
601 ; RV32-ILP32F-NEXT: addi sp, sp, 16
602 ; RV32-ILP32F-NEXT: ret
603 ;
604 ; RV64-LP64F-LABEL: caller_half_ret:
605 ; RV64-LP64F: # %bb.0:
606 ; RV64-LP64F-NEXT: addi sp, sp, -16
607 ; RV64-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
608 ; RV64-LP64F-NEXT: call callee_half_ret
609 ; RV64-LP64F-NEXT: call __extendhfsf2
610 ; RV64-LP64F-NEXT: fcvt.l.s a0, fa0, rtz
611 ; RV64-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
612 ; RV64-LP64F-NEXT: addi sp, sp, 16
613 ; RV64-LP64F-NEXT: ret
614 ;
615 ; RV32-ILP32ZFHMIN-LABEL: caller_half_ret:
616 ; RV32-ILP32ZFHMIN: # %bb.0:
617 ; RV32-ILP32ZFHMIN-NEXT: addi sp, sp, -16
618 ; RV32-ILP32ZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
619 ; RV32-ILP32ZFHMIN-NEXT: call callee_half_ret
620 ; RV32-ILP32ZFHMIN-NEXT: fcvt.s.h fa5, fa0
621 ; RV32-ILP32ZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
622 ; RV32-ILP32ZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
623 ; RV32-ILP32ZFHMIN-NEXT: addi sp, sp, 16
624 ; RV32-ILP32ZFHMIN-NEXT: ret
625 ;
626 ; RV64-LP64ZFHMIN-LABEL: caller_half_ret:
627 ; RV64-LP64ZFHMIN: # %bb.0:
628 ; RV64-LP64ZFHMIN-NEXT: addi sp, sp, -16
629 ; RV64-LP64ZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
630 ; RV64-LP64ZFHMIN-NEXT: call callee_half_ret
631 ; RV64-LP64ZFHMIN-NEXT: fcvt.s.h fa5, fa0
632 ; RV64-LP64ZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
633 ; RV64-LP64ZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
634 ; RV64-LP64ZFHMIN-NEXT: addi sp, sp, 16
635 ; RV64-LP64ZFHMIN-NEXT: ret
636 %1 = call half @callee_half_ret()
637 %2 = fptosi half %1 to i32
638 ret i32 %2
639 }