| blob | 3adc46143f9f20a46ae1819b5bf4317779d2e077 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
3 ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32d \
4 ; RUN: | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
5 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
6 ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64d \
7 ; RUN: | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
8 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \
9 ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32 \
10 ; RUN: | FileCheck -check-prefix=RV32IZFINXZDINX %s
11 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \
12 ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64 \
13 ; RUN: | FileCheck -check-prefix=RV64IZFINXZDINX %s
14 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
15 ; RUN: -verify-machineinstrs -disable-strictnode-mutation \
16 ; RUN: | FileCheck -check-prefix=RV32I %s
17 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
18 ; RUN: -verify-machineinstrs -disable-strictnode-mutation \
19 ; RUN: | FileCheck -check-prefix=RV64I %s
21 declare double @llvm.experimental.constrained.sqrt.f64(double, metadata, metadata)
23 define double @sqrt_f64(double %a) nounwind strictfp {
24 ; CHECKIFD-LABEL: sqrt_f64:
25 ; CHECKIFD: # %bb.0:
26 ; CHECKIFD-NEXT: fsqrt.d fa0, fa0
27 ; CHECKIFD-NEXT: ret
28 ;
29 ; RV32IZFINXZDINX-LABEL: sqrt_f64:
30 ; RV32IZFINXZDINX: # %bb.0:
31 ; RV32IZFINXZDINX-NEXT: fsqrt.d a0, a0
32 ; RV32IZFINXZDINX-NEXT: ret
33 ;
34 ; RV64IZFINXZDINX-LABEL: sqrt_f64:
35 ; RV64IZFINXZDINX: # %bb.0:
36 ; RV64IZFINXZDINX-NEXT: fsqrt.d a0, a0
37 ; RV64IZFINXZDINX-NEXT: ret
38 ;
39 ; RV32I-LABEL: sqrt_f64:
40 ; RV32I: # %bb.0:
41 ; RV32I-NEXT: addi sp, sp, -16
42 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
43 ; RV32I-NEXT: call sqrt
44 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
45 ; RV32I-NEXT: addi sp, sp, 16
46 ; RV32I-NEXT: ret
47 ;
48 ; RV64I-LABEL: sqrt_f64:
49 ; RV64I: # %bb.0:
50 ; RV64I-NEXT: addi sp, sp, -16
51 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
52 ; RV64I-NEXT: call sqrt
53 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
54 ; RV64I-NEXT: addi sp, sp, 16
55 ; RV64I-NEXT: ret
56 %1 = call double @llvm.experimental.constrained.sqrt.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
57 ret double %1
58 }
60 declare double @llvm.experimental.constrained.powi.f64(double, i32, metadata, metadata)
62 define double @powi_f64(double %a, i32 %b) nounwind strictfp {
63 ; RV32IFD-LABEL: powi_f64:
64 ; RV32IFD: # %bb.0:
65 ; RV32IFD-NEXT: addi sp, sp, -16
66 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
67 ; RV32IFD-NEXT: call __powidf2
68 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
69 ; RV32IFD-NEXT: addi sp, sp, 16
70 ; RV32IFD-NEXT: ret
71 ;
72 ; RV64IFD-LABEL: powi_f64:
73 ; RV64IFD: # %bb.0:
74 ; RV64IFD-NEXT: addi sp, sp, -16
75 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
76 ; RV64IFD-NEXT: sext.w a0, a0
77 ; RV64IFD-NEXT: call __powidf2
78 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
79 ; RV64IFD-NEXT: addi sp, sp, 16
80 ; RV64IFD-NEXT: ret
81 ;
82 ; RV32IZFINXZDINX-LABEL: powi_f64:
83 ; RV32IZFINXZDINX: # %bb.0:
84 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
85 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
86 ; RV32IZFINXZDINX-NEXT: call __powidf2
87 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
88 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
89 ; RV32IZFINXZDINX-NEXT: ret
90 ;
91 ; RV64IZFINXZDINX-LABEL: powi_f64:
92 ; RV64IZFINXZDINX: # %bb.0:
93 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
94 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
95 ; RV64IZFINXZDINX-NEXT: sext.w a1, a1
96 ; RV64IZFINXZDINX-NEXT: call __powidf2
97 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
98 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
99 ; RV64IZFINXZDINX-NEXT: ret
100 ;
101 ; RV32I-LABEL: powi_f64:
102 ; RV32I: # %bb.0:
103 ; RV32I-NEXT: addi sp, sp, -16
104 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
105 ; RV32I-NEXT: call __powidf2
106 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
107 ; RV32I-NEXT: addi sp, sp, 16
108 ; RV32I-NEXT: ret
109 ;
110 ; RV64I-LABEL: powi_f64:
111 ; RV64I: # %bb.0:
112 ; RV64I-NEXT: addi sp, sp, -16
113 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
114 ; RV64I-NEXT: sext.w a1, a1
115 ; RV64I-NEXT: call __powidf2
116 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
117 ; RV64I-NEXT: addi sp, sp, 16
118 ; RV64I-NEXT: ret
119 %1 = call double @llvm.experimental.constrained.powi.f64(double %a, i32 %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
120 ret double %1
121 }
123 declare double @llvm.experimental.constrained.sin.f64(double, metadata, metadata)
125 define double @sin_f64(double %a) nounwind strictfp {
126 ; RV32IFD-LABEL: sin_f64:
127 ; RV32IFD: # %bb.0:
128 ; RV32IFD-NEXT: addi sp, sp, -16
129 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
130 ; RV32IFD-NEXT: call sin
131 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
132 ; RV32IFD-NEXT: addi sp, sp, 16
133 ; RV32IFD-NEXT: ret
134 ;
135 ; RV64IFD-LABEL: sin_f64:
136 ; RV64IFD: # %bb.0:
137 ; RV64IFD-NEXT: addi sp, sp, -16
138 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
139 ; RV64IFD-NEXT: call sin
140 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
141 ; RV64IFD-NEXT: addi sp, sp, 16
142 ; RV64IFD-NEXT: ret
143 ;
144 ; RV32IZFINXZDINX-LABEL: sin_f64:
145 ; RV32IZFINXZDINX: # %bb.0:
146 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
147 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
148 ; RV32IZFINXZDINX-NEXT: call sin
149 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
150 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
151 ; RV32IZFINXZDINX-NEXT: ret
152 ;
153 ; RV64IZFINXZDINX-LABEL: sin_f64:
154 ; RV64IZFINXZDINX: # %bb.0:
155 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
156 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
157 ; RV64IZFINXZDINX-NEXT: call sin
158 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
159 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
160 ; RV64IZFINXZDINX-NEXT: ret
161 ;
162 ; RV32I-LABEL: sin_f64:
163 ; RV32I: # %bb.0:
164 ; RV32I-NEXT: addi sp, sp, -16
165 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
166 ; RV32I-NEXT: call sin
167 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
168 ; RV32I-NEXT: addi sp, sp, 16
169 ; RV32I-NEXT: ret
170 ;
171 ; RV64I-LABEL: sin_f64:
172 ; RV64I: # %bb.0:
173 ; RV64I-NEXT: addi sp, sp, -16
174 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
175 ; RV64I-NEXT: call sin
176 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
177 ; RV64I-NEXT: addi sp, sp, 16
178 ; RV64I-NEXT: ret
179 %1 = call double @llvm.experimental.constrained.sin.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
180 ret double %1
181 }
183 declare double @llvm.experimental.constrained.cos.f64(double, metadata, metadata)
185 define double @cos_f64(double %a) nounwind strictfp {
186 ; RV32IFD-LABEL: cos_f64:
187 ; RV32IFD: # %bb.0:
188 ; RV32IFD-NEXT: addi sp, sp, -16
189 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
190 ; RV32IFD-NEXT: call cos
191 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
192 ; RV32IFD-NEXT: addi sp, sp, 16
193 ; RV32IFD-NEXT: ret
194 ;
195 ; RV64IFD-LABEL: cos_f64:
196 ; RV64IFD: # %bb.0:
197 ; RV64IFD-NEXT: addi sp, sp, -16
198 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
199 ; RV64IFD-NEXT: call cos
200 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
201 ; RV64IFD-NEXT: addi sp, sp, 16
202 ; RV64IFD-NEXT: ret
203 ;
204 ; RV32IZFINXZDINX-LABEL: cos_f64:
205 ; RV32IZFINXZDINX: # %bb.0:
206 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
207 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
208 ; RV32IZFINXZDINX-NEXT: call cos
209 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
210 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
211 ; RV32IZFINXZDINX-NEXT: ret
212 ;
213 ; RV64IZFINXZDINX-LABEL: cos_f64:
214 ; RV64IZFINXZDINX: # %bb.0:
215 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
216 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
217 ; RV64IZFINXZDINX-NEXT: call cos
218 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
219 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
220 ; RV64IZFINXZDINX-NEXT: ret
221 ;
222 ; RV32I-LABEL: cos_f64:
223 ; RV32I: # %bb.0:
224 ; RV32I-NEXT: addi sp, sp, -16
225 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
226 ; RV32I-NEXT: call cos
227 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
228 ; RV32I-NEXT: addi sp, sp, 16
229 ; RV32I-NEXT: ret
230 ;
231 ; RV64I-LABEL: cos_f64:
232 ; RV64I: # %bb.0:
233 ; RV64I-NEXT: addi sp, sp, -16
234 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
235 ; RV64I-NEXT: call cos
236 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
237 ; RV64I-NEXT: addi sp, sp, 16
238 ; RV64I-NEXT: ret
239 %1 = call double @llvm.experimental.constrained.cos.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
240 ret double %1
241 }
243 ; The sin+cos combination results in an FSINCOS SelectionDAG node.
244 define double @sincos_f64(double %a) nounwind strictfp {
245 ; RV32IFD-LABEL: sincos_f64:
246 ; RV32IFD: # %bb.0:
247 ; RV32IFD-NEXT: addi sp, sp, -32
248 ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
249 ; RV32IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
250 ; RV32IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
251 ; RV32IFD-NEXT: fmv.d fs0, fa0
252 ; RV32IFD-NEXT: call sin
253 ; RV32IFD-NEXT: fmv.d fs1, fa0
254 ; RV32IFD-NEXT: fmv.d fa0, fs0
255 ; RV32IFD-NEXT: call cos
256 ; RV32IFD-NEXT: fadd.d fa0, fs1, fa0
257 ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
258 ; RV32IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
259 ; RV32IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
260 ; RV32IFD-NEXT: addi sp, sp, 32
261 ; RV32IFD-NEXT: ret
262 ;
263 ; RV64IFD-LABEL: sincos_f64:
264 ; RV64IFD: # %bb.0:
265 ; RV64IFD-NEXT: addi sp, sp, -32
266 ; RV64IFD-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
267 ; RV64IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
268 ; RV64IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
269 ; RV64IFD-NEXT: fmv.d fs0, fa0
270 ; RV64IFD-NEXT: call sin
271 ; RV64IFD-NEXT: fmv.d fs1, fa0
272 ; RV64IFD-NEXT: fmv.d fa0, fs0
273 ; RV64IFD-NEXT: call cos
274 ; RV64IFD-NEXT: fadd.d fa0, fs1, fa0
275 ; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
276 ; RV64IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
277 ; RV64IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
278 ; RV64IFD-NEXT: addi sp, sp, 32
279 ; RV64IFD-NEXT: ret
280 ;
281 ; RV32IZFINXZDINX-LABEL: sincos_f64:
282 ; RV32IZFINXZDINX: # %bb.0:
283 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
284 ; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
285 ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
286 ; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
287 ; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
288 ; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
289 ; RV32IZFINXZDINX-NEXT: mv s0, a1
290 ; RV32IZFINXZDINX-NEXT: mv s1, a0
291 ; RV32IZFINXZDINX-NEXT: call sin
292 ; RV32IZFINXZDINX-NEXT: mv s2, a0
293 ; RV32IZFINXZDINX-NEXT: mv s3, a1
294 ; RV32IZFINXZDINX-NEXT: mv a0, s1
295 ; RV32IZFINXZDINX-NEXT: mv a1, s0
296 ; RV32IZFINXZDINX-NEXT: call cos
297 ; RV32IZFINXZDINX-NEXT: fadd.d a0, s2, a0
298 ; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
299 ; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
300 ; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
301 ; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
302 ; RV32IZFINXZDINX-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
303 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
304 ; RV32IZFINXZDINX-NEXT: ret
305 ;
306 ; RV64IZFINXZDINX-LABEL: sincos_f64:
307 ; RV64IZFINXZDINX: # %bb.0:
308 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -32
309 ; RV64IZFINXZDINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
310 ; RV64IZFINXZDINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
311 ; RV64IZFINXZDINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
312 ; RV64IZFINXZDINX-NEXT: mv s0, a0
313 ; RV64IZFINXZDINX-NEXT: call sin
314 ; RV64IZFINXZDINX-NEXT: mv s1, a0
315 ; RV64IZFINXZDINX-NEXT: mv a0, s0
316 ; RV64IZFINXZDINX-NEXT: call cos
317 ; RV64IZFINXZDINX-NEXT: fadd.d a0, s1, a0
318 ; RV64IZFINXZDINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
319 ; RV64IZFINXZDINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
320 ; RV64IZFINXZDINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
321 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 32
322 ; RV64IZFINXZDINX-NEXT: ret
323 ;
324 ; RV32I-LABEL: sincos_f64:
325 ; RV32I: # %bb.0:
326 ; RV32I-NEXT: addi sp, sp, -32
327 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
328 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
329 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
330 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
331 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
332 ; RV32I-NEXT: mv s0, a1
333 ; RV32I-NEXT: mv s1, a0
334 ; RV32I-NEXT: call sin
335 ; RV32I-NEXT: mv s2, a0
336 ; RV32I-NEXT: mv s3, a1
337 ; RV32I-NEXT: mv a0, s1
338 ; RV32I-NEXT: mv a1, s0
339 ; RV32I-NEXT: call cos
340 ; RV32I-NEXT: mv a2, a0
341 ; RV32I-NEXT: mv a3, a1
342 ; RV32I-NEXT: mv a0, s2
343 ; RV32I-NEXT: mv a1, s3
344 ; RV32I-NEXT: call __adddf3
345 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
346 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
347 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
348 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
349 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
350 ; RV32I-NEXT: addi sp, sp, 32
351 ; RV32I-NEXT: ret
352 ;
353 ; RV64I-LABEL: sincos_f64:
354 ; RV64I: # %bb.0:
355 ; RV64I-NEXT: addi sp, sp, -32
356 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
357 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
358 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
359 ; RV64I-NEXT: mv s0, a0
360 ; RV64I-NEXT: call sin
361 ; RV64I-NEXT: mv s1, a0
362 ; RV64I-NEXT: mv a0, s0
363 ; RV64I-NEXT: call cos
364 ; RV64I-NEXT: mv a1, a0
365 ; RV64I-NEXT: mv a0, s1
366 ; RV64I-NEXT: call __adddf3
367 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
368 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
369 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
370 ; RV64I-NEXT: addi sp, sp, 32
371 ; RV64I-NEXT: ret
372 %1 = call double @llvm.experimental.constrained.sin.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
373 %2 = call double @llvm.experimental.constrained.cos.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
374 %3 = fadd double %1, %2
375 ret double %3
376 }
378 declare double @llvm.experimental.constrained.tan.f64(double, metadata, metadata)
380 define double @tan_f64(double %a) nounwind strictfp {
381 ; RV32IFD-LABEL: tan_f64:
382 ; RV32IFD: # %bb.0:
383 ; RV32IFD-NEXT: addi sp, sp, -16
384 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
385 ; RV32IFD-NEXT: call tan
386 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
387 ; RV32IFD-NEXT: addi sp, sp, 16
388 ; RV32IFD-NEXT: ret
389 ;
390 ; RV64IFD-LABEL: tan_f64:
391 ; RV64IFD: # %bb.0:
392 ; RV64IFD-NEXT: addi sp, sp, -16
393 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
394 ; RV64IFD-NEXT: call tan
395 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
396 ; RV64IFD-NEXT: addi sp, sp, 16
397 ; RV64IFD-NEXT: ret
398 ;
399 ; RV32IZFINXZDINX-LABEL: tan_f64:
400 ; RV32IZFINXZDINX: # %bb.0:
401 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
402 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
403 ; RV32IZFINXZDINX-NEXT: call tan
404 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
405 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
406 ; RV32IZFINXZDINX-NEXT: ret
407 ;
408 ; RV64IZFINXZDINX-LABEL: tan_f64:
409 ; RV64IZFINXZDINX: # %bb.0:
410 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
411 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
412 ; RV64IZFINXZDINX-NEXT: call tan
413 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
414 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
415 ; RV64IZFINXZDINX-NEXT: ret
416 ;
417 ; RV32I-LABEL: tan_f64:
418 ; RV32I: # %bb.0:
419 ; RV32I-NEXT: addi sp, sp, -16
420 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
421 ; RV32I-NEXT: call tan
422 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
423 ; RV32I-NEXT: addi sp, sp, 16
424 ; RV32I-NEXT: ret
425 ;
426 ; RV64I-LABEL: tan_f64:
427 ; RV64I: # %bb.0:
428 ; RV64I-NEXT: addi sp, sp, -16
429 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
430 ; RV64I-NEXT: call tan
431 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
432 ; RV64I-NEXT: addi sp, sp, 16
433 ; RV64I-NEXT: ret
434 %1 = call double @llvm.experimental.constrained.tan.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
435 ret double %1
436 }
438 declare double @llvm.experimental.constrained.pow.f64(double, double, metadata, metadata)
440 define double @pow_f64(double %a, double %b) nounwind strictfp {
441 ; RV32IFD-LABEL: pow_f64:
442 ; RV32IFD: # %bb.0:
443 ; RV32IFD-NEXT: addi sp, sp, -16
444 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
445 ; RV32IFD-NEXT: call pow
446 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
447 ; RV32IFD-NEXT: addi sp, sp, 16
448 ; RV32IFD-NEXT: ret
449 ;
450 ; RV64IFD-LABEL: pow_f64:
451 ; RV64IFD: # %bb.0:
452 ; RV64IFD-NEXT: addi sp, sp, -16
453 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
454 ; RV64IFD-NEXT: call pow
455 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
456 ; RV64IFD-NEXT: addi sp, sp, 16
457 ; RV64IFD-NEXT: ret
458 ;
459 ; RV32IZFINXZDINX-LABEL: pow_f64:
460 ; RV32IZFINXZDINX: # %bb.0:
461 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
462 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
463 ; RV32IZFINXZDINX-NEXT: call pow
464 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
465 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
466 ; RV32IZFINXZDINX-NEXT: ret
467 ;
468 ; RV64IZFINXZDINX-LABEL: pow_f64:
469 ; RV64IZFINXZDINX: # %bb.0:
470 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
471 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
472 ; RV64IZFINXZDINX-NEXT: call pow
473 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
474 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
475 ; RV64IZFINXZDINX-NEXT: ret
476 ;
477 ; RV32I-LABEL: pow_f64:
478 ; RV32I: # %bb.0:
479 ; RV32I-NEXT: addi sp, sp, -16
480 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
481 ; RV32I-NEXT: call pow
482 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
483 ; RV32I-NEXT: addi sp, sp, 16
484 ; RV32I-NEXT: ret
485 ;
486 ; RV64I-LABEL: pow_f64:
487 ; RV64I: # %bb.0:
488 ; RV64I-NEXT: addi sp, sp, -16
489 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
490 ; RV64I-NEXT: call pow
491 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
492 ; RV64I-NEXT: addi sp, sp, 16
493 ; RV64I-NEXT: ret
494 %1 = call double @llvm.experimental.constrained.pow.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
495 ret double %1
496 }
498 declare double @llvm.experimental.constrained.exp.f64(double, metadata, metadata)
500 define double @exp_f64(double %a) nounwind strictfp {
501 ; RV32IFD-LABEL: exp_f64:
502 ; RV32IFD: # %bb.0:
503 ; RV32IFD-NEXT: addi sp, sp, -16
504 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
505 ; RV32IFD-NEXT: call exp
506 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
507 ; RV32IFD-NEXT: addi sp, sp, 16
508 ; RV32IFD-NEXT: ret
509 ;
510 ; RV64IFD-LABEL: exp_f64:
511 ; RV64IFD: # %bb.0:
512 ; RV64IFD-NEXT: addi sp, sp, -16
513 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
514 ; RV64IFD-NEXT: call exp
515 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
516 ; RV64IFD-NEXT: addi sp, sp, 16
517 ; RV64IFD-NEXT: ret
518 ;
519 ; RV32IZFINXZDINX-LABEL: exp_f64:
520 ; RV32IZFINXZDINX: # %bb.0:
521 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
522 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
523 ; RV32IZFINXZDINX-NEXT: call exp
524 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
525 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
526 ; RV32IZFINXZDINX-NEXT: ret
527 ;
528 ; RV64IZFINXZDINX-LABEL: exp_f64:
529 ; RV64IZFINXZDINX: # %bb.0:
530 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
531 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
532 ; RV64IZFINXZDINX-NEXT: call exp
533 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
534 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
535 ; RV64IZFINXZDINX-NEXT: ret
536 ;
537 ; RV32I-LABEL: exp_f64:
538 ; RV32I: # %bb.0:
539 ; RV32I-NEXT: addi sp, sp, -16
540 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
541 ; RV32I-NEXT: call exp
542 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
543 ; RV32I-NEXT: addi sp, sp, 16
544 ; RV32I-NEXT: ret
545 ;
546 ; RV64I-LABEL: exp_f64:
547 ; RV64I: # %bb.0:
548 ; RV64I-NEXT: addi sp, sp, -16
549 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
550 ; RV64I-NEXT: call exp
551 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
552 ; RV64I-NEXT: addi sp, sp, 16
553 ; RV64I-NEXT: ret
554 %1 = call double @llvm.experimental.constrained.exp.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
555 ret double %1
556 }
558 declare double @llvm.experimental.constrained.exp2.f64(double, metadata, metadata)
560 define double @exp2_f64(double %a) nounwind strictfp {
561 ; RV32IFD-LABEL: exp2_f64:
562 ; RV32IFD: # %bb.0:
563 ; RV32IFD-NEXT: addi sp, sp, -16
564 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
565 ; RV32IFD-NEXT: call exp2
566 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
567 ; RV32IFD-NEXT: addi sp, sp, 16
568 ; RV32IFD-NEXT: ret
569 ;
570 ; RV64IFD-LABEL: exp2_f64:
571 ; RV64IFD: # %bb.0:
572 ; RV64IFD-NEXT: addi sp, sp, -16
573 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
574 ; RV64IFD-NEXT: call exp2
575 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
576 ; RV64IFD-NEXT: addi sp, sp, 16
577 ; RV64IFD-NEXT: ret
578 ;
579 ; RV32IZFINXZDINX-LABEL: exp2_f64:
580 ; RV32IZFINXZDINX: # %bb.0:
581 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
582 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
583 ; RV32IZFINXZDINX-NEXT: call exp2
584 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
585 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
586 ; RV32IZFINXZDINX-NEXT: ret
587 ;
588 ; RV64IZFINXZDINX-LABEL: exp2_f64:
589 ; RV64IZFINXZDINX: # %bb.0:
590 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
591 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
592 ; RV64IZFINXZDINX-NEXT: call exp2
593 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
594 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
595 ; RV64IZFINXZDINX-NEXT: ret
596 ;
597 ; RV32I-LABEL: exp2_f64:
598 ; RV32I: # %bb.0:
599 ; RV32I-NEXT: addi sp, sp, -16
600 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
601 ; RV32I-NEXT: call exp2
602 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
603 ; RV32I-NEXT: addi sp, sp, 16
604 ; RV32I-NEXT: ret
605 ;
606 ; RV64I-LABEL: exp2_f64:
607 ; RV64I: # %bb.0:
608 ; RV64I-NEXT: addi sp, sp, -16
609 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
610 ; RV64I-NEXT: call exp2
611 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
612 ; RV64I-NEXT: addi sp, sp, 16
613 ; RV64I-NEXT: ret
614 %1 = call double @llvm.experimental.constrained.exp2.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
615 ret double %1
616 }
618 declare double @llvm.experimental.constrained.log.f64(double, metadata, metadata)
620 define double @log_f64(double %a) nounwind strictfp {
621 ; RV32IFD-LABEL: log_f64:
622 ; RV32IFD: # %bb.0:
623 ; RV32IFD-NEXT: addi sp, sp, -16
624 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
625 ; RV32IFD-NEXT: call log
626 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
627 ; RV32IFD-NEXT: addi sp, sp, 16
628 ; RV32IFD-NEXT: ret
629 ;
630 ; RV64IFD-LABEL: log_f64:
631 ; RV64IFD: # %bb.0:
632 ; RV64IFD-NEXT: addi sp, sp, -16
633 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
634 ; RV64IFD-NEXT: call log
635 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
636 ; RV64IFD-NEXT: addi sp, sp, 16
637 ; RV64IFD-NEXT: ret
638 ;
639 ; RV32IZFINXZDINX-LABEL: log_f64:
640 ; RV32IZFINXZDINX: # %bb.0:
641 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
642 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
643 ; RV32IZFINXZDINX-NEXT: call log
644 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
645 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
646 ; RV32IZFINXZDINX-NEXT: ret
647 ;
648 ; RV64IZFINXZDINX-LABEL: log_f64:
649 ; RV64IZFINXZDINX: # %bb.0:
650 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
651 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
652 ; RV64IZFINXZDINX-NEXT: call log
653 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
654 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
655 ; RV64IZFINXZDINX-NEXT: ret
656 ;
657 ; RV32I-LABEL: log_f64:
658 ; RV32I: # %bb.0:
659 ; RV32I-NEXT: addi sp, sp, -16
660 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
661 ; RV32I-NEXT: call log
662 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
663 ; RV32I-NEXT: addi sp, sp, 16
664 ; RV32I-NEXT: ret
665 ;
666 ; RV64I-LABEL: log_f64:
667 ; RV64I: # %bb.0:
668 ; RV64I-NEXT: addi sp, sp, -16
669 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
670 ; RV64I-NEXT: call log
671 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
672 ; RV64I-NEXT: addi sp, sp, 16
673 ; RV64I-NEXT: ret
674 %1 = call double @llvm.experimental.constrained.log.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
675 ret double %1
676 }
678 declare double @llvm.experimental.constrained.log10.f64(double, metadata, metadata)
680 define double @log10_f64(double %a) nounwind strictfp {
681 ; RV32IFD-LABEL: log10_f64:
682 ; RV32IFD: # %bb.0:
683 ; RV32IFD-NEXT: addi sp, sp, -16
684 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
685 ; RV32IFD-NEXT: call log10
686 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
687 ; RV32IFD-NEXT: addi sp, sp, 16
688 ; RV32IFD-NEXT: ret
689 ;
690 ; RV64IFD-LABEL: log10_f64:
691 ; RV64IFD: # %bb.0:
692 ; RV64IFD-NEXT: addi sp, sp, -16
693 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
694 ; RV64IFD-NEXT: call log10
695 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
696 ; RV64IFD-NEXT: addi sp, sp, 16
697 ; RV64IFD-NEXT: ret
698 ;
699 ; RV32IZFINXZDINX-LABEL: log10_f64:
700 ; RV32IZFINXZDINX: # %bb.0:
701 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
702 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
703 ; RV32IZFINXZDINX-NEXT: call log10
704 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
705 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
706 ; RV32IZFINXZDINX-NEXT: ret
707 ;
708 ; RV64IZFINXZDINX-LABEL: log10_f64:
709 ; RV64IZFINXZDINX: # %bb.0:
710 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
711 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
712 ; RV64IZFINXZDINX-NEXT: call log10
713 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
714 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
715 ; RV64IZFINXZDINX-NEXT: ret
716 ;
717 ; RV32I-LABEL: log10_f64:
718 ; RV32I: # %bb.0:
719 ; RV32I-NEXT: addi sp, sp, -16
720 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
721 ; RV32I-NEXT: call log10
722 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
723 ; RV32I-NEXT: addi sp, sp, 16
724 ; RV32I-NEXT: ret
725 ;
726 ; RV64I-LABEL: log10_f64:
727 ; RV64I: # %bb.0:
728 ; RV64I-NEXT: addi sp, sp, -16
729 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
730 ; RV64I-NEXT: call log10
731 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
732 ; RV64I-NEXT: addi sp, sp, 16
733 ; RV64I-NEXT: ret
734 %1 = call double @llvm.experimental.constrained.log10.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
735 ret double %1
736 }
738 declare double @llvm.experimental.constrained.log2.f64(double, metadata, metadata)
740 define double @log2_f64(double %a) nounwind strictfp {
741 ; RV32IFD-LABEL: log2_f64:
742 ; RV32IFD: # %bb.0:
743 ; RV32IFD-NEXT: addi sp, sp, -16
744 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
745 ; RV32IFD-NEXT: call log2
746 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
747 ; RV32IFD-NEXT: addi sp, sp, 16
748 ; RV32IFD-NEXT: ret
749 ;
750 ; RV64IFD-LABEL: log2_f64:
751 ; RV64IFD: # %bb.0:
752 ; RV64IFD-NEXT: addi sp, sp, -16
753 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
754 ; RV64IFD-NEXT: call log2
755 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
756 ; RV64IFD-NEXT: addi sp, sp, 16
757 ; RV64IFD-NEXT: ret
758 ;
759 ; RV32IZFINXZDINX-LABEL: log2_f64:
760 ; RV32IZFINXZDINX: # %bb.0:
761 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
762 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
763 ; RV32IZFINXZDINX-NEXT: call log2
764 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
765 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
766 ; RV32IZFINXZDINX-NEXT: ret
767 ;
768 ; RV64IZFINXZDINX-LABEL: log2_f64:
769 ; RV64IZFINXZDINX: # %bb.0:
770 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
771 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
772 ; RV64IZFINXZDINX-NEXT: call log2
773 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
774 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
775 ; RV64IZFINXZDINX-NEXT: ret
776 ;
777 ; RV32I-LABEL: log2_f64:
778 ; RV32I: # %bb.0:
779 ; RV32I-NEXT: addi sp, sp, -16
780 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
781 ; RV32I-NEXT: call log2
782 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
783 ; RV32I-NEXT: addi sp, sp, 16
784 ; RV32I-NEXT: ret
785 ;
786 ; RV64I-LABEL: log2_f64:
787 ; RV64I: # %bb.0:
788 ; RV64I-NEXT: addi sp, sp, -16
789 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
790 ; RV64I-NEXT: call log2
791 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
792 ; RV64I-NEXT: addi sp, sp, 16
793 ; RV64I-NEXT: ret
794 %1 = call double @llvm.experimental.constrained.log2.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
795 ret double %1
796 }
798 declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata)
800 define double @fma_f64(double %a, double %b, double %c) nounwind strictfp {
801 ; CHECKIFD-LABEL: fma_f64:
802 ; CHECKIFD: # %bb.0:
803 ; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
804 ; CHECKIFD-NEXT: ret
805 ;
806 ; RV32IZFINXZDINX-LABEL: fma_f64:
807 ; RV32IZFINXZDINX: # %bb.0:
808 ; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4
809 ; RV32IZFINXZDINX-NEXT: ret
810 ;
811 ; RV64IZFINXZDINX-LABEL: fma_f64:
812 ; RV64IZFINXZDINX: # %bb.0:
813 ; RV64IZFINXZDINX-NEXT: fmadd.d a0, a0, a1, a2
814 ; RV64IZFINXZDINX-NEXT: ret
815 ;
816 ; RV32I-LABEL: fma_f64:
817 ; RV32I: # %bb.0:
818 ; RV32I-NEXT: addi sp, sp, -16
819 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
820 ; RV32I-NEXT: call fma
821 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
822 ; RV32I-NEXT: addi sp, sp, 16
823 ; RV32I-NEXT: ret
824 ;
825 ; RV64I-LABEL: fma_f64:
826 ; RV64I: # %bb.0:
827 ; RV64I-NEXT: addi sp, sp, -16
828 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
829 ; RV64I-NEXT: call fma
830 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
831 ; RV64I-NEXT: addi sp, sp, 16
832 ; RV64I-NEXT: ret
833 %1 = call double @llvm.experimental.constrained.fma.f64(double %a, double %b, double %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
834 ret double %1
835 }
837 declare double @llvm.experimental.constrained.fmuladd.f64(double, double, double, metadata, metadata)
839 define double @fmuladd_f64(double %a, double %b, double %c) nounwind strictfp {
840 ; CHECKIFD-LABEL: fmuladd_f64:
841 ; CHECKIFD: # %bb.0:
842 ; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
843 ; CHECKIFD-NEXT: ret
844 ;
845 ; RV32IZFINXZDINX-LABEL: fmuladd_f64:
846 ; RV32IZFINXZDINX: # %bb.0:
847 ; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4
848 ; RV32IZFINXZDINX-NEXT: ret
849 ;
850 ; RV64IZFINXZDINX-LABEL: fmuladd_f64:
851 ; RV64IZFINXZDINX: # %bb.0:
852 ; RV64IZFINXZDINX-NEXT: fmadd.d a0, a0, a1, a2
853 ; RV64IZFINXZDINX-NEXT: ret
854 ;
855 ; RV32I-LABEL: fmuladd_f64:
856 ; RV32I: # %bb.0:
857 ; RV32I-NEXT: addi sp, sp, -16
858 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
859 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
860 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
861 ; RV32I-NEXT: mv s0, a5
862 ; RV32I-NEXT: mv s1, a4
863 ; RV32I-NEXT: call __muldf3
864 ; RV32I-NEXT: mv a2, s1
865 ; RV32I-NEXT: mv a3, s0
866 ; RV32I-NEXT: call __adddf3
867 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
868 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
869 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
870 ; RV32I-NEXT: addi sp, sp, 16
871 ; RV32I-NEXT: ret
872 ;
873 ; RV64I-LABEL: fmuladd_f64:
874 ; RV64I: # %bb.0:
875 ; RV64I-NEXT: addi sp, sp, -16
876 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
877 ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
878 ; RV64I-NEXT: mv s0, a2
879 ; RV64I-NEXT: call __muldf3
880 ; RV64I-NEXT: mv a1, s0
881 ; RV64I-NEXT: call __adddf3
882 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
883 ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
884 ; RV64I-NEXT: addi sp, sp, 16
885 ; RV64I-NEXT: ret
886 %1 = call double @llvm.experimental.constrained.fmuladd.f64(double %a, double %b, double %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
887 ret double %1
888 }
890 declare double @llvm.experimental.constrained.minnum.f64(double, double, metadata)
892 define double @minnum_f64(double %a, double %b) nounwind strictfp {
893 ; RV32IFD-LABEL: minnum_f64:
894 ; RV32IFD: # %bb.0:
895 ; RV32IFD-NEXT: addi sp, sp, -16
896 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
897 ; RV32IFD-NEXT: call fmin
898 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
899 ; RV32IFD-NEXT: addi sp, sp, 16
900 ; RV32IFD-NEXT: ret
901 ;
902 ; RV64IFD-LABEL: minnum_f64:
903 ; RV64IFD: # %bb.0:
904 ; RV64IFD-NEXT: addi sp, sp, -16
905 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
906 ; RV64IFD-NEXT: call fmin
907 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
908 ; RV64IFD-NEXT: addi sp, sp, 16
909 ; RV64IFD-NEXT: ret
910 ;
911 ; RV32IZFINXZDINX-LABEL: minnum_f64:
912 ; RV32IZFINXZDINX: # %bb.0:
913 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
914 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
915 ; RV32IZFINXZDINX-NEXT: call fmin
916 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
917 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
918 ; RV32IZFINXZDINX-NEXT: ret
919 ;
920 ; RV64IZFINXZDINX-LABEL: minnum_f64:
921 ; RV64IZFINXZDINX: # %bb.0:
922 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
923 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
924 ; RV64IZFINXZDINX-NEXT: call fmin
925 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
926 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
927 ; RV64IZFINXZDINX-NEXT: ret
928 ;
929 ; RV32I-LABEL: minnum_f64:
930 ; RV32I: # %bb.0:
931 ; RV32I-NEXT: addi sp, sp, -16
932 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
933 ; RV32I-NEXT: call fmin
934 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
935 ; RV32I-NEXT: addi sp, sp, 16
936 ; RV32I-NEXT: ret
937 ;
938 ; RV64I-LABEL: minnum_f64:
939 ; RV64I: # %bb.0:
940 ; RV64I-NEXT: addi sp, sp, -16
941 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
942 ; RV64I-NEXT: call fmin
943 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
944 ; RV64I-NEXT: addi sp, sp, 16
945 ; RV64I-NEXT: ret
946 %1 = call double @llvm.experimental.constrained.minnum.f64(double %a, double %b, metadata !"fpexcept.strict") strictfp
947 ret double %1
948 }
950 declare double @llvm.experimental.constrained.maxnum.f64(double, double, metadata)
952 define double @maxnum_f64(double %a, double %b) nounwind strictfp {
953 ; RV32IFD-LABEL: maxnum_f64:
954 ; RV32IFD: # %bb.0:
955 ; RV32IFD-NEXT: addi sp, sp, -16
956 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
957 ; RV32IFD-NEXT: call fmax
958 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
959 ; RV32IFD-NEXT: addi sp, sp, 16
960 ; RV32IFD-NEXT: ret
961 ;
962 ; RV64IFD-LABEL: maxnum_f64:
963 ; RV64IFD: # %bb.0:
964 ; RV64IFD-NEXT: addi sp, sp, -16
965 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
966 ; RV64IFD-NEXT: call fmax
967 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
968 ; RV64IFD-NEXT: addi sp, sp, 16
969 ; RV64IFD-NEXT: ret
970 ;
971 ; RV32IZFINXZDINX-LABEL: maxnum_f64:
972 ; RV32IZFINXZDINX: # %bb.0:
973 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
974 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
975 ; RV32IZFINXZDINX-NEXT: call fmax
976 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
977 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
978 ; RV32IZFINXZDINX-NEXT: ret
979 ;
980 ; RV64IZFINXZDINX-LABEL: maxnum_f64:
981 ; RV64IZFINXZDINX: # %bb.0:
982 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
983 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
984 ; RV64IZFINXZDINX-NEXT: call fmax
985 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
986 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
987 ; RV64IZFINXZDINX-NEXT: ret
988 ;
989 ; RV32I-LABEL: maxnum_f64:
990 ; RV32I: # %bb.0:
991 ; RV32I-NEXT: addi sp, sp, -16
992 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
993 ; RV32I-NEXT: call fmax
994 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
995 ; RV32I-NEXT: addi sp, sp, 16
996 ; RV32I-NEXT: ret
997 ;
998 ; RV64I-LABEL: maxnum_f64:
999 ; RV64I: # %bb.0:
1000 ; RV64I-NEXT: addi sp, sp, -16
1001 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1002 ; RV64I-NEXT: call fmax
1003 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1004 ; RV64I-NEXT: addi sp, sp, 16
1005 ; RV64I-NEXT: ret
1006 %1 = call double @llvm.experimental.constrained.maxnum.f64(double %a, double %b, metadata !"fpexcept.strict") strictfp
1007 ret double %1
1008 }
1010 ; TODO: FMINNAN and FMAXNAN aren't handled in
1011 ; SelectionDAGLegalize::ExpandNode.
1013 ; declare double @llvm.experimental.constrained.minimum.f64(double, double, metadata)
1015 ; define double @fminimum_f64(double %a, double %b) nounwind strictfp {
1016 ; %1 = call double @llvm.experimental.constrained.minimum.f64(double %a, double %b, metadata !"fpexcept.strict") strictfp
1017 ; ret double %1
1018 ; }
1020 ; declare double @llvm.experimental.constrained.maximum.f64(double, double, metadata)
1022 ; define double @fmaximum_f64(double %a, double %b) nounwind strictfp {
1023 ; %1 = call double @llvm.experimental.constrained.maximum.f64(double %a, double %b, metadata !"fpexcept.strict") strictfp
1024 ; ret double %1
1025 ; }
1027 declare double @llvm.experimental.constrained.floor.f64(double, metadata)
1029 define double @floor_f64(double %a) nounwind strictfp {
1030 ; RV32IFD-LABEL: floor_f64:
1031 ; RV32IFD: # %bb.0:
1032 ; RV32IFD-NEXT: addi sp, sp, -16
1033 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1034 ; RV32IFD-NEXT: call floor
1035 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1036 ; RV32IFD-NEXT: addi sp, sp, 16
1037 ; RV32IFD-NEXT: ret
1038 ;
1039 ; RV64IFD-LABEL: floor_f64:
1040 ; RV64IFD: # %bb.0:
1041 ; RV64IFD-NEXT: addi sp, sp, -16
1042 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1043 ; RV64IFD-NEXT: call floor
1044 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1045 ; RV64IFD-NEXT: addi sp, sp, 16
1046 ; RV64IFD-NEXT: ret
1047 ;
1048 ; RV32IZFINXZDINX-LABEL: floor_f64:
1049 ; RV32IZFINXZDINX: # %bb.0:
1050 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1051 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1052 ; RV32IZFINXZDINX-NEXT: call floor
1053 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1054 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1055 ; RV32IZFINXZDINX-NEXT: ret
1056 ;
1057 ; RV64IZFINXZDINX-LABEL: floor_f64:
1058 ; RV64IZFINXZDINX: # %bb.0:
1059 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
1060 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1061 ; RV64IZFINXZDINX-NEXT: call floor
1062 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1063 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
1064 ; RV64IZFINXZDINX-NEXT: ret
1065 ;
1066 ; RV32I-LABEL: floor_f64:
1067 ; RV32I: # %bb.0:
1068 ; RV32I-NEXT: addi sp, sp, -16
1069 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1070 ; RV32I-NEXT: call floor
1071 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1072 ; RV32I-NEXT: addi sp, sp, 16
1073 ; RV32I-NEXT: ret
1074 ;
1075 ; RV64I-LABEL: floor_f64:
1076 ; RV64I: # %bb.0:
1077 ; RV64I-NEXT: addi sp, sp, -16
1078 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1079 ; RV64I-NEXT: call floor
1080 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1081 ; RV64I-NEXT: addi sp, sp, 16
1082 ; RV64I-NEXT: ret
1083 %1 = call double @llvm.experimental.constrained.floor.f64(double %a, metadata !"fpexcept.strict") strictfp
1084 ret double %1
1085 }
1087 declare double @llvm.experimental.constrained.ceil.f64(double, metadata)
1089 define double @ceil_f64(double %a) nounwind strictfp {
1090 ; RV32IFD-LABEL: ceil_f64:
1091 ; RV32IFD: # %bb.0:
1092 ; RV32IFD-NEXT: addi sp, sp, -16
1093 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1094 ; RV32IFD-NEXT: call ceil
1095 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1096 ; RV32IFD-NEXT: addi sp, sp, 16
1097 ; RV32IFD-NEXT: ret
1098 ;
1099 ; RV64IFD-LABEL: ceil_f64:
1100 ; RV64IFD: # %bb.0:
1101 ; RV64IFD-NEXT: addi sp, sp, -16
1102 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1103 ; RV64IFD-NEXT: call ceil
1104 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1105 ; RV64IFD-NEXT: addi sp, sp, 16
1106 ; RV64IFD-NEXT: ret
1107 ;
1108 ; RV32IZFINXZDINX-LABEL: ceil_f64:
1109 ; RV32IZFINXZDINX: # %bb.0:
1110 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1111 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1112 ; RV32IZFINXZDINX-NEXT: call ceil
1113 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1114 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1115 ; RV32IZFINXZDINX-NEXT: ret
1116 ;
1117 ; RV64IZFINXZDINX-LABEL: ceil_f64:
1118 ; RV64IZFINXZDINX: # %bb.0:
1119 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
1120 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1121 ; RV64IZFINXZDINX-NEXT: call ceil
1122 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1123 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
1124 ; RV64IZFINXZDINX-NEXT: ret
1125 ;
1126 ; RV32I-LABEL: ceil_f64:
1127 ; RV32I: # %bb.0:
1128 ; RV32I-NEXT: addi sp, sp, -16
1129 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1130 ; RV32I-NEXT: call ceil
1131 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1132 ; RV32I-NEXT: addi sp, sp, 16
1133 ; RV32I-NEXT: ret
1134 ;
1135 ; RV64I-LABEL: ceil_f64:
1136 ; RV64I: # %bb.0:
1137 ; RV64I-NEXT: addi sp, sp, -16
1138 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1139 ; RV64I-NEXT: call ceil
1140 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1141 ; RV64I-NEXT: addi sp, sp, 16
1142 ; RV64I-NEXT: ret
1143 %1 = call double @llvm.experimental.constrained.ceil.f64(double %a, metadata !"fpexcept.strict") strictfp
1144 ret double %1
1145 }
1147 declare double @llvm.experimental.constrained.trunc.f64(double, metadata)
1149 define double @trunc_f64(double %a) nounwind strictfp {
1150 ; RV32IFD-LABEL: trunc_f64:
1151 ; RV32IFD: # %bb.0:
1152 ; RV32IFD-NEXT: addi sp, sp, -16
1153 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1154 ; RV32IFD-NEXT: call trunc
1155 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1156 ; RV32IFD-NEXT: addi sp, sp, 16
1157 ; RV32IFD-NEXT: ret
1158 ;
1159 ; RV64IFD-LABEL: trunc_f64:
1160 ; RV64IFD: # %bb.0:
1161 ; RV64IFD-NEXT: addi sp, sp, -16
1162 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1163 ; RV64IFD-NEXT: call trunc
1164 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1165 ; RV64IFD-NEXT: addi sp, sp, 16
1166 ; RV64IFD-NEXT: ret
1167 ;
1168 ; RV32IZFINXZDINX-LABEL: trunc_f64:
1169 ; RV32IZFINXZDINX: # %bb.0:
1170 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1171 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1172 ; RV32IZFINXZDINX-NEXT: call trunc
1173 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1174 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1175 ; RV32IZFINXZDINX-NEXT: ret
1176 ;
1177 ; RV64IZFINXZDINX-LABEL: trunc_f64:
1178 ; RV64IZFINXZDINX: # %bb.0:
1179 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
1180 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1181 ; RV64IZFINXZDINX-NEXT: call trunc
1182 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1183 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
1184 ; RV64IZFINXZDINX-NEXT: ret
1185 ;
1186 ; RV32I-LABEL: trunc_f64:
1187 ; RV32I: # %bb.0:
1188 ; RV32I-NEXT: addi sp, sp, -16
1189 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1190 ; RV32I-NEXT: call trunc
1191 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1192 ; RV32I-NEXT: addi sp, sp, 16
1193 ; RV32I-NEXT: ret
1194 ;
1195 ; RV64I-LABEL: trunc_f64:
1196 ; RV64I: # %bb.0:
1197 ; RV64I-NEXT: addi sp, sp, -16
1198 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1199 ; RV64I-NEXT: call trunc
1200 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1201 ; RV64I-NEXT: addi sp, sp, 16
1202 ; RV64I-NEXT: ret
1203 %1 = call double @llvm.experimental.constrained.trunc.f64(double %a, metadata !"fpexcept.strict") strictfp
1204 ret double %1
1205 }
1207 declare double @llvm.experimental.constrained.rint.f64(double, metadata, metadata)
1209 define double @rint_f64(double %a) nounwind strictfp {
1210 ; RV32IFD-LABEL: rint_f64:
1211 ; RV32IFD: # %bb.0:
1212 ; RV32IFD-NEXT: addi sp, sp, -16
1213 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1214 ; RV32IFD-NEXT: call rint
1215 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1216 ; RV32IFD-NEXT: addi sp, sp, 16
1217 ; RV32IFD-NEXT: ret
1218 ;
1219 ; RV64IFD-LABEL: rint_f64:
1220 ; RV64IFD: # %bb.0:
1221 ; RV64IFD-NEXT: addi sp, sp, -16
1222 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1223 ; RV64IFD-NEXT: call rint
1224 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1225 ; RV64IFD-NEXT: addi sp, sp, 16
1226 ; RV64IFD-NEXT: ret
1227 ;
1228 ; RV32IZFINXZDINX-LABEL: rint_f64:
1229 ; RV32IZFINXZDINX: # %bb.0:
1230 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1231 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1232 ; RV32IZFINXZDINX-NEXT: call rint
1233 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1234 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1235 ; RV32IZFINXZDINX-NEXT: ret
1236 ;
1237 ; RV64IZFINXZDINX-LABEL: rint_f64:
1238 ; RV64IZFINXZDINX: # %bb.0:
1239 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
1240 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1241 ; RV64IZFINXZDINX-NEXT: call rint
1242 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1243 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
1244 ; RV64IZFINXZDINX-NEXT: ret
1245 ;
1246 ; RV32I-LABEL: rint_f64:
1247 ; RV32I: # %bb.0:
1248 ; RV32I-NEXT: addi sp, sp, -16
1249 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1250 ; RV32I-NEXT: call rint
1251 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1252 ; RV32I-NEXT: addi sp, sp, 16
1253 ; RV32I-NEXT: ret
1254 ;
1255 ; RV64I-LABEL: rint_f64:
1256 ; RV64I: # %bb.0:
1257 ; RV64I-NEXT: addi sp, sp, -16
1258 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1259 ; RV64I-NEXT: call rint
1260 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1261 ; RV64I-NEXT: addi sp, sp, 16
1262 ; RV64I-NEXT: ret
1263 %1 = call double @llvm.experimental.constrained.rint.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
1264 ret double %1
1265 }
1267 declare double @llvm.experimental.constrained.nearbyint.f64(double, metadata, metadata)
1269 define double @nearbyint_f64(double %a) nounwind strictfp {
1270 ; RV32IFD-LABEL: nearbyint_f64:
1271 ; RV32IFD: # %bb.0:
1272 ; RV32IFD-NEXT: addi sp, sp, -16
1273 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1274 ; RV32IFD-NEXT: call nearbyint
1275 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1276 ; RV32IFD-NEXT: addi sp, sp, 16
1277 ; RV32IFD-NEXT: ret
1278 ;
1279 ; RV64IFD-LABEL: nearbyint_f64:
1280 ; RV64IFD: # %bb.0:
1281 ; RV64IFD-NEXT: addi sp, sp, -16
1282 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1283 ; RV64IFD-NEXT: call nearbyint
1284 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1285 ; RV64IFD-NEXT: addi sp, sp, 16
1286 ; RV64IFD-NEXT: ret
1287 ;
1288 ; RV32IZFINXZDINX-LABEL: nearbyint_f64:
1289 ; RV32IZFINXZDINX: # %bb.0:
1290 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1291 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1292 ; RV32IZFINXZDINX-NEXT: call nearbyint
1293 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1294 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1295 ; RV32IZFINXZDINX-NEXT: ret
1296 ;
1297 ; RV64IZFINXZDINX-LABEL: nearbyint_f64:
1298 ; RV64IZFINXZDINX: # %bb.0:
1299 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
1300 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1301 ; RV64IZFINXZDINX-NEXT: call nearbyint
1302 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1303 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
1304 ; RV64IZFINXZDINX-NEXT: ret
1305 ;
1306 ; RV32I-LABEL: nearbyint_f64:
1307 ; RV32I: # %bb.0:
1308 ; RV32I-NEXT: addi sp, sp, -16
1309 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1310 ; RV32I-NEXT: call nearbyint
1311 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1312 ; RV32I-NEXT: addi sp, sp, 16
1313 ; RV32I-NEXT: ret
1314 ;
1315 ; RV64I-LABEL: nearbyint_f64:
1316 ; RV64I: # %bb.0:
1317 ; RV64I-NEXT: addi sp, sp, -16
1318 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1319 ; RV64I-NEXT: call nearbyint
1320 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1321 ; RV64I-NEXT: addi sp, sp, 16
1322 ; RV64I-NEXT: ret
1323 %1 = call double @llvm.experimental.constrained.nearbyint.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
1324 ret double %1
1325 }
1327 declare double @llvm.experimental.constrained.round.f64(double, metadata)
1329 define double @round_f64(double %a) nounwind strictfp {
1330 ; RV32IFD-LABEL: round_f64:
1331 ; RV32IFD: # %bb.0:
1332 ; RV32IFD-NEXT: addi sp, sp, -16
1333 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1334 ; RV32IFD-NEXT: call round
1335 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1336 ; RV32IFD-NEXT: addi sp, sp, 16
1337 ; RV32IFD-NEXT: ret
1338 ;
1339 ; RV64IFD-LABEL: round_f64:
1340 ; RV64IFD: # %bb.0:
1341 ; RV64IFD-NEXT: addi sp, sp, -16
1342 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1343 ; RV64IFD-NEXT: call round
1344 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1345 ; RV64IFD-NEXT: addi sp, sp, 16
1346 ; RV64IFD-NEXT: ret
1347 ;
1348 ; RV32IZFINXZDINX-LABEL: round_f64:
1349 ; RV32IZFINXZDINX: # %bb.0:
1350 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1351 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1352 ; RV32IZFINXZDINX-NEXT: call round
1353 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1354 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1355 ; RV32IZFINXZDINX-NEXT: ret
1356 ;
1357 ; RV64IZFINXZDINX-LABEL: round_f64:
1358 ; RV64IZFINXZDINX: # %bb.0:
1359 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
1360 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1361 ; RV64IZFINXZDINX-NEXT: call round
1362 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1363 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
1364 ; RV64IZFINXZDINX-NEXT: ret
1365 ;
1366 ; RV32I-LABEL: round_f64:
1367 ; RV32I: # %bb.0:
1368 ; RV32I-NEXT: addi sp, sp, -16
1369 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1370 ; RV32I-NEXT: call round
1371 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1372 ; RV32I-NEXT: addi sp, sp, 16
1373 ; RV32I-NEXT: ret
1374 ;
1375 ; RV64I-LABEL: round_f64:
1376 ; RV64I: # %bb.0:
1377 ; RV64I-NEXT: addi sp, sp, -16
1378 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1379 ; RV64I-NEXT: call round
1380 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1381 ; RV64I-NEXT: addi sp, sp, 16
1382 ; RV64I-NEXT: ret
1383 %1 = call double @llvm.experimental.constrained.round.f64(double %a, metadata !"fpexcept.strict") strictfp
1384 ret double %1
1385 }
1387 declare double @llvm.experimental.constrained.roundeven.f64(double, metadata)
1389 define double @roundeven_f64(double %a) nounwind strictfp {
1390 ; RV32IFD-LABEL: roundeven_f64:
1391 ; RV32IFD: # %bb.0:
1392 ; RV32IFD-NEXT: addi sp, sp, -16
1393 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1394 ; RV32IFD-NEXT: call roundeven
1395 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1396 ; RV32IFD-NEXT: addi sp, sp, 16
1397 ; RV32IFD-NEXT: ret
1398 ;
1399 ; RV64IFD-LABEL: roundeven_f64:
1400 ; RV64IFD: # %bb.0:
1401 ; RV64IFD-NEXT: addi sp, sp, -16
1402 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1403 ; RV64IFD-NEXT: call roundeven
1404 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1405 ; RV64IFD-NEXT: addi sp, sp, 16
1406 ; RV64IFD-NEXT: ret
1407 ;
1408 ; RV32IZFINXZDINX-LABEL: roundeven_f64:
1409 ; RV32IZFINXZDINX: # %bb.0:
1410 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1411 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1412 ; RV32IZFINXZDINX-NEXT: call roundeven
1413 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1414 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1415 ; RV32IZFINXZDINX-NEXT: ret
1416 ;
1417 ; RV64IZFINXZDINX-LABEL: roundeven_f64:
1418 ; RV64IZFINXZDINX: # %bb.0:
1419 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
1420 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1421 ; RV64IZFINXZDINX-NEXT: call roundeven
1422 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1423 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
1424 ; RV64IZFINXZDINX-NEXT: ret
1425 ;
1426 ; RV32I-LABEL: roundeven_f64:
1427 ; RV32I: # %bb.0:
1428 ; RV32I-NEXT: addi sp, sp, -16
1429 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1430 ; RV32I-NEXT: call roundeven
1431 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1432 ; RV32I-NEXT: addi sp, sp, 16
1433 ; RV32I-NEXT: ret
1434 ;
1435 ; RV64I-LABEL: roundeven_f64:
1436 ; RV64I: # %bb.0:
1437 ; RV64I-NEXT: addi sp, sp, -16
1438 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1439 ; RV64I-NEXT: call roundeven
1440 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1441 ; RV64I-NEXT: addi sp, sp, 16
1442 ; RV64I-NEXT: ret
1443 %1 = call double @llvm.experimental.constrained.roundeven.f64(double %a, metadata !"fpexcept.strict") strictfp
1444 ret double %1
1445 }
1447 declare iXLen @llvm.experimental.constrained.lrint.iXLen.f64(double, metadata, metadata)
1449 define iXLen @lrint_f64(double %a) nounwind strictfp {
1450 ; RV32IFD-LABEL: lrint_f64:
1451 ; RV32IFD: # %bb.0:
1452 ; RV32IFD-NEXT: fcvt.w.d a0, fa0
1453 ; RV32IFD-NEXT: ret
1454 ;
1455 ; RV64IFD-LABEL: lrint_f64:
1456 ; RV64IFD: # %bb.0:
1457 ; RV64IFD-NEXT: fcvt.l.d a0, fa0
1458 ; RV64IFD-NEXT: ret
1459 ;
1460 ; RV32IZFINXZDINX-LABEL: lrint_f64:
1461 ; RV32IZFINXZDINX: # %bb.0:
1462 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0
1463 ; RV32IZFINXZDINX-NEXT: ret
1464 ;
1465 ; RV64IZFINXZDINX-LABEL: lrint_f64:
1466 ; RV64IZFINXZDINX: # %bb.0:
1467 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0
1468 ; RV64IZFINXZDINX-NEXT: ret
1469 ;
1470 ; RV32I-LABEL: lrint_f64:
1471 ; RV32I: # %bb.0:
1472 ; RV32I-NEXT: addi sp, sp, -16
1473 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1474 ; RV32I-NEXT: call lrint
1475 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1476 ; RV32I-NEXT: addi sp, sp, 16
1477 ; RV32I-NEXT: ret
1478 ;
1479 ; RV64I-LABEL: lrint_f64:
1480 ; RV64I: # %bb.0:
1481 ; RV64I-NEXT: addi sp, sp, -16
1482 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1483 ; RV64I-NEXT: call lrint
1484 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1485 ; RV64I-NEXT: addi sp, sp, 16
1486 ; RV64I-NEXT: ret
1487 %1 = call iXLen @llvm.experimental.constrained.lrint.iXLen.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
1488 ret iXLen %1
1489 }
1491 declare iXLen @llvm.experimental.constrained.lround.iXLen.f64(double, metadata)
1493 define iXLen @lround_f64(double %a) nounwind strictfp {
1494 ; RV32IFD-LABEL: lround_f64:
1495 ; RV32IFD: # %bb.0:
1496 ; RV32IFD-NEXT: fcvt.w.d a0, fa0, rmm
1497 ; RV32IFD-NEXT: ret
1498 ;
1499 ; RV64IFD-LABEL: lround_f64:
1500 ; RV64IFD: # %bb.0:
1501 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm
1502 ; RV64IFD-NEXT: ret
1503 ;
1504 ; RV32IZFINXZDINX-LABEL: lround_f64:
1505 ; RV32IZFINXZDINX: # %bb.0:
1506 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rmm
1507 ; RV32IZFINXZDINX-NEXT: ret
1508 ;
1509 ; RV64IZFINXZDINX-LABEL: lround_f64:
1510 ; RV64IZFINXZDINX: # %bb.0:
1511 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rmm
1512 ; RV64IZFINXZDINX-NEXT: ret
1513 ;
1514 ; RV32I-LABEL: lround_f64:
1515 ; RV32I: # %bb.0:
1516 ; RV32I-NEXT: addi sp, sp, -16
1517 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1518 ; RV32I-NEXT: call lround
1519 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1520 ; RV32I-NEXT: addi sp, sp, 16
1521 ; RV32I-NEXT: ret
1522 ;
1523 ; RV64I-LABEL: lround_f64:
1524 ; RV64I: # %bb.0:
1525 ; RV64I-NEXT: addi sp, sp, -16
1526 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1527 ; RV64I-NEXT: call lround
1528 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1529 ; RV64I-NEXT: addi sp, sp, 16
1530 ; RV64I-NEXT: ret
1531 %1 = call iXLen @llvm.experimental.constrained.lround.iXLen.f64(double %a, metadata !"fpexcept.strict") strictfp
1532 ret iXLen %1
1533 }
1535 declare i64 @llvm.experimental.constrained.llrint.i64.f64(double, metadata, metadata)
1537 define i64 @llrint_f64(double %a) nounwind strictfp {
1538 ; RV32IFD-LABEL: llrint_f64:
1539 ; RV32IFD: # %bb.0:
1540 ; RV32IFD-NEXT: addi sp, sp, -16
1541 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1542 ; RV32IFD-NEXT: call llrint
1543 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1544 ; RV32IFD-NEXT: addi sp, sp, 16
1545 ; RV32IFD-NEXT: ret
1546 ;
1547 ; RV64IFD-LABEL: llrint_f64:
1548 ; RV64IFD: # %bb.0:
1549 ; RV64IFD-NEXT: fcvt.l.d a0, fa0
1550 ; RV64IFD-NEXT: ret
1551 ;
1552 ; RV32IZFINXZDINX-LABEL: llrint_f64:
1553 ; RV32IZFINXZDINX: # %bb.0:
1554 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1555 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1556 ; RV32IZFINXZDINX-NEXT: call llrint
1557 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1558 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1559 ; RV32IZFINXZDINX-NEXT: ret
1560 ;
1561 ; RV64IZFINXZDINX-LABEL: llrint_f64:
1562 ; RV64IZFINXZDINX: # %bb.0:
1563 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0
1564 ; RV64IZFINXZDINX-NEXT: ret
1565 ;
1566 ; RV32I-LABEL: llrint_f64:
1567 ; RV32I: # %bb.0:
1568 ; RV32I-NEXT: addi sp, sp, -16
1569 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1570 ; RV32I-NEXT: call llrint
1571 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1572 ; RV32I-NEXT: addi sp, sp, 16
1573 ; RV32I-NEXT: ret
1574 ;
1575 ; RV64I-LABEL: llrint_f64:
1576 ; RV64I: # %bb.0:
1577 ; RV64I-NEXT: addi sp, sp, -16
1578 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1579 ; RV64I-NEXT: call llrint
1580 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1581 ; RV64I-NEXT: addi sp, sp, 16
1582 ; RV64I-NEXT: ret
1583 %1 = call i64 @llvm.experimental.constrained.llrint.i64.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
1584 ret i64 %1
1585 }
1587 declare i64 @llvm.experimental.constrained.llround.i64.f64(double, metadata)
1589 define i64 @llround_f64(double %a) nounwind strictfp {
1590 ; RV32IFD-LABEL: llround_f64:
1591 ; RV32IFD: # %bb.0:
1592 ; RV32IFD-NEXT: addi sp, sp, -16
1593 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1594 ; RV32IFD-NEXT: call llround
1595 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1596 ; RV32IFD-NEXT: addi sp, sp, 16
1597 ; RV32IFD-NEXT: ret
1598 ;
1599 ; RV64IFD-LABEL: llround_f64:
1600 ; RV64IFD: # %bb.0:
1601 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm
1602 ; RV64IFD-NEXT: ret
1603 ;
1604 ; RV32IZFINXZDINX-LABEL: llround_f64:
1605 ; RV32IZFINXZDINX: # %bb.0:
1606 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1607 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1608 ; RV32IZFINXZDINX-NEXT: call llround
1609 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1610 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1611 ; RV32IZFINXZDINX-NEXT: ret
1612 ;
1613 ; RV64IZFINXZDINX-LABEL: llround_f64:
1614 ; RV64IZFINXZDINX: # %bb.0:
1615 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rmm
1616 ; RV64IZFINXZDINX-NEXT: ret
1617 ;
1618 ; RV32I-LABEL: llround_f64:
1619 ; RV32I: # %bb.0:
1620 ; RV32I-NEXT: addi sp, sp, -16
1621 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1622 ; RV32I-NEXT: call llround
1623 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1624 ; RV32I-NEXT: addi sp, sp, 16
1625 ; RV32I-NEXT: ret
1626 ;
1627 ; RV64I-LABEL: llround_f64:
1628 ; RV64I: # %bb.0:
1629 ; RV64I-NEXT: addi sp, sp, -16
1630 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1631 ; RV64I-NEXT: call llround
1632 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1633 ; RV64I-NEXT: addi sp, sp, 16
1634 ; RV64I-NEXT: ret
1635 %1 = call i64 @llvm.experimental.constrained.llround.i64.f64(double %a, metadata !"fpexcept.strict") strictfp
1636 ret i64 %1
1637 }
1639 declare double @llvm.experimental.constrained.atan2.f64(double, double, metadata, metadata)
1641 define double @atan2_f64(double %a, double %b) nounwind strictfp {
1642 ; RV32IFD-LABEL: atan2_f64:
1643 ; RV32IFD: # %bb.0:
1644 ; RV32IFD-NEXT: addi sp, sp, -16
1645 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1646 ; RV32IFD-NEXT: call atan2
1647 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1648 ; RV32IFD-NEXT: addi sp, sp, 16
1649 ; RV32IFD-NEXT: ret
1650 ;
1651 ; RV64IFD-LABEL: atan2_f64:
1652 ; RV64IFD: # %bb.0:
1653 ; RV64IFD-NEXT: addi sp, sp, -16
1654 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1655 ; RV64IFD-NEXT: call atan2
1656 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1657 ; RV64IFD-NEXT: addi sp, sp, 16
1658 ; RV64IFD-NEXT: ret
1659 ;
1660 ; RV32IZFINXZDINX-LABEL: atan2_f64:
1661 ; RV32IZFINXZDINX: # %bb.0:
1662 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1663 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1664 ; RV32IZFINXZDINX-NEXT: call atan2
1665 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1666 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1667 ; RV32IZFINXZDINX-NEXT: ret
1668 ;
1669 ; RV64IZFINXZDINX-LABEL: atan2_f64:
1670 ; RV64IZFINXZDINX: # %bb.0:
1671 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
1672 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1673 ; RV64IZFINXZDINX-NEXT: call atan2
1674 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1675 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
1676 ; RV64IZFINXZDINX-NEXT: ret
1677 ;
1678 ; RV32I-LABEL: atan2_f64:
1679 ; RV32I: # %bb.0:
1680 ; RV32I-NEXT: addi sp, sp, -16
1681 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1682 ; RV32I-NEXT: call atan2
1683 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1684 ; RV32I-NEXT: addi sp, sp, 16
1685 ; RV32I-NEXT: ret
1686 ;
1687 ; RV64I-LABEL: atan2_f64:
1688 ; RV64I: # %bb.0:
1689 ; RV64I-NEXT: addi sp, sp, -16
1690 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1691 ; RV64I-NEXT: call atan2
1692 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1693 ; RV64I-NEXT: addi sp, sp, 16
1694 ; RV64I-NEXT: ret
1695 %1 = call double @llvm.experimental.constrained.atan2.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
1696 ret double %1
1697 }