| blob | 265d553a3e5d91aac900d04868686a675eef5873 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
3 ; RUN: -target-abi=ilp32f | FileCheck -check-prefix=CHECKIF %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
5 ; RUN: -target-abi=lp64f | FileCheck -check-prefix=CHECKIF %s
6 ; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
7 ; RUN: -target-abi=ilp32 | FileCheck -check-prefix=CHECKIZFINX %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
9 ; RUN: -target-abi=lp64 | FileCheck -check-prefix=CHECKIZFINX %s
10 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
11 ; RUN: | FileCheck -check-prefix=RV32I %s
12 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
13 ; RUN: | FileCheck -check-prefix=RV64I %s
15 define i32 @fcmp_false(float %a, float %b) nounwind {
16 ; CHECKIF-LABEL: fcmp_false:
17 ; CHECKIF: # %bb.0:
18 ; CHECKIF-NEXT: li a0, 0
19 ; CHECKIF-NEXT: ret
20 ;
21 ; CHECKIZFINX-LABEL: fcmp_false:
22 ; CHECKIZFINX: # %bb.0:
23 ; CHECKIZFINX-NEXT: li a0, 0
24 ; CHECKIZFINX-NEXT: ret
25 ;
26 ; RV32I-LABEL: fcmp_false:
27 ; RV32I: # %bb.0:
28 ; RV32I-NEXT: li a0, 0
29 ; RV32I-NEXT: ret
30 ;
31 ; RV64I-LABEL: fcmp_false:
32 ; RV64I: # %bb.0:
33 ; RV64I-NEXT: li a0, 0
34 ; RV64I-NEXT: ret
35 %1 = fcmp false float %a, %b
36 %2 = zext i1 %1 to i32
37 ret i32 %2
38 }
40 define i32 @fcmp_oeq(float %a, float %b) nounwind {
41 ; CHECKIF-LABEL: fcmp_oeq:
42 ; CHECKIF: # %bb.0:
43 ; CHECKIF-NEXT: feq.s a0, fa0, fa1
44 ; CHECKIF-NEXT: ret
45 ;
46 ; CHECKIZFINX-LABEL: fcmp_oeq:
47 ; CHECKIZFINX: # %bb.0:
48 ; CHECKIZFINX-NEXT: feq.s a0, a0, a1
49 ; CHECKIZFINX-NEXT: ret
50 ;
51 ; RV32I-LABEL: fcmp_oeq:
52 ; RV32I: # %bb.0:
53 ; RV32I-NEXT: addi sp, sp, -16
54 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
55 ; RV32I-NEXT: call __eqsf2
56 ; RV32I-NEXT: seqz a0, a0
57 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
58 ; RV32I-NEXT: addi sp, sp, 16
59 ; RV32I-NEXT: ret
60 ;
61 ; RV64I-LABEL: fcmp_oeq:
62 ; RV64I: # %bb.0:
63 ; RV64I-NEXT: addi sp, sp, -16
64 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
65 ; RV64I-NEXT: call __eqsf2
66 ; RV64I-NEXT: seqz a0, a0
67 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
68 ; RV64I-NEXT: addi sp, sp, 16
69 ; RV64I-NEXT: ret
70 %1 = fcmp oeq float %a, %b
71 %2 = zext i1 %1 to i32
72 ret i32 %2
73 }
75 define i32 @fcmp_ogt(float %a, float %b) nounwind {
76 ; CHECKIF-LABEL: fcmp_ogt:
77 ; CHECKIF: # %bb.0:
78 ; CHECKIF-NEXT: flt.s a0, fa1, fa0
79 ; CHECKIF-NEXT: ret
80 ;
81 ; CHECKIZFINX-LABEL: fcmp_ogt:
82 ; CHECKIZFINX: # %bb.0:
83 ; CHECKIZFINX-NEXT: flt.s a0, a1, a0
84 ; CHECKIZFINX-NEXT: ret
85 ;
86 ; RV32I-LABEL: fcmp_ogt:
87 ; RV32I: # %bb.0:
88 ; RV32I-NEXT: addi sp, sp, -16
89 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
90 ; RV32I-NEXT: call __gtsf2
91 ; RV32I-NEXT: sgtz a0, a0
92 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
93 ; RV32I-NEXT: addi sp, sp, 16
94 ; RV32I-NEXT: ret
95 ;
96 ; RV64I-LABEL: fcmp_ogt:
97 ; RV64I: # %bb.0:
98 ; RV64I-NEXT: addi sp, sp, -16
99 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
100 ; RV64I-NEXT: call __gtsf2
101 ; RV64I-NEXT: sgtz a0, a0
102 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
103 ; RV64I-NEXT: addi sp, sp, 16
104 ; RV64I-NEXT: ret
105 %1 = fcmp ogt float %a, %b
106 %2 = zext i1 %1 to i32
107 ret i32 %2
108 }
110 define i32 @fcmp_oge(float %a, float %b) nounwind {
111 ; CHECKIF-LABEL: fcmp_oge:
112 ; CHECKIF: # %bb.0:
113 ; CHECKIF-NEXT: fle.s a0, fa1, fa0
114 ; CHECKIF-NEXT: ret
115 ;
116 ; CHECKIZFINX-LABEL: fcmp_oge:
117 ; CHECKIZFINX: # %bb.0:
118 ; CHECKIZFINX-NEXT: fle.s a0, a1, a0
119 ; CHECKIZFINX-NEXT: ret
120 ;
121 ; RV32I-LABEL: fcmp_oge:
122 ; RV32I: # %bb.0:
123 ; RV32I-NEXT: addi sp, sp, -16
124 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
125 ; RV32I-NEXT: call __gesf2
126 ; RV32I-NEXT: slti a0, a0, 0
127 ; RV32I-NEXT: xori a0, a0, 1
128 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
129 ; RV32I-NEXT: addi sp, sp, 16
130 ; RV32I-NEXT: ret
131 ;
132 ; RV64I-LABEL: fcmp_oge:
133 ; RV64I: # %bb.0:
134 ; RV64I-NEXT: addi sp, sp, -16
135 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
136 ; RV64I-NEXT: call __gesf2
137 ; RV64I-NEXT: slti a0, a0, 0
138 ; RV64I-NEXT: xori a0, a0, 1
139 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
140 ; RV64I-NEXT: addi sp, sp, 16
141 ; RV64I-NEXT: ret
142 %1 = fcmp oge float %a, %b
143 %2 = zext i1 %1 to i32
144 ret i32 %2
145 }
147 define i32 @fcmp_olt(float %a, float %b) nounwind {
148 ; CHECKIF-LABEL: fcmp_olt:
149 ; CHECKIF: # %bb.0:
150 ; CHECKIF-NEXT: flt.s a0, fa0, fa1
151 ; CHECKIF-NEXT: ret
152 ;
153 ; CHECKIZFINX-LABEL: fcmp_olt:
154 ; CHECKIZFINX: # %bb.0:
155 ; CHECKIZFINX-NEXT: flt.s a0, a0, a1
156 ; CHECKIZFINX-NEXT: ret
157 ;
158 ; RV32I-LABEL: fcmp_olt:
159 ; RV32I: # %bb.0:
160 ; RV32I-NEXT: addi sp, sp, -16
161 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
162 ; RV32I-NEXT: call __ltsf2
163 ; RV32I-NEXT: slti a0, a0, 0
164 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
165 ; RV32I-NEXT: addi sp, sp, 16
166 ; RV32I-NEXT: ret
167 ;
168 ; RV64I-LABEL: fcmp_olt:
169 ; RV64I: # %bb.0:
170 ; RV64I-NEXT: addi sp, sp, -16
171 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
172 ; RV64I-NEXT: call __ltsf2
173 ; RV64I-NEXT: slti a0, a0, 0
174 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
175 ; RV64I-NEXT: addi sp, sp, 16
176 ; RV64I-NEXT: ret
177 %1 = fcmp olt float %a, %b
178 %2 = zext i1 %1 to i32
179 ret i32 %2
180 }
182 define i32 @fcmp_ole(float %a, float %b) nounwind {
183 ; CHECKIF-LABEL: fcmp_ole:
184 ; CHECKIF: # %bb.0:
185 ; CHECKIF-NEXT: fle.s a0, fa0, fa1
186 ; CHECKIF-NEXT: ret
187 ;
188 ; CHECKIZFINX-LABEL: fcmp_ole:
189 ; CHECKIZFINX: # %bb.0:
190 ; CHECKIZFINX-NEXT: fle.s a0, a0, a1
191 ; CHECKIZFINX-NEXT: ret
192 ;
193 ; RV32I-LABEL: fcmp_ole:
194 ; RV32I: # %bb.0:
195 ; RV32I-NEXT: addi sp, sp, -16
196 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
197 ; RV32I-NEXT: call __lesf2
198 ; RV32I-NEXT: slti a0, a0, 1
199 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
200 ; RV32I-NEXT: addi sp, sp, 16
201 ; RV32I-NEXT: ret
202 ;
203 ; RV64I-LABEL: fcmp_ole:
204 ; RV64I: # %bb.0:
205 ; RV64I-NEXT: addi sp, sp, -16
206 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
207 ; RV64I-NEXT: call __lesf2
208 ; RV64I-NEXT: slti a0, a0, 1
209 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
210 ; RV64I-NEXT: addi sp, sp, 16
211 ; RV64I-NEXT: ret
212 %1 = fcmp ole float %a, %b
213 %2 = zext i1 %1 to i32
214 ret i32 %2
215 }
217 define i32 @fcmp_one(float %a, float %b) nounwind {
218 ; CHECKIF-LABEL: fcmp_one:
219 ; CHECKIF: # %bb.0:
220 ; CHECKIF-NEXT: flt.s a0, fa0, fa1
221 ; CHECKIF-NEXT: flt.s a1, fa1, fa0
222 ; CHECKIF-NEXT: or a0, a1, a0
223 ; CHECKIF-NEXT: ret
224 ;
225 ; CHECKIZFINX-LABEL: fcmp_one:
226 ; CHECKIZFINX: # %bb.0:
227 ; CHECKIZFINX-NEXT: flt.s a2, a0, a1
228 ; CHECKIZFINX-NEXT: flt.s a0, a1, a0
229 ; CHECKIZFINX-NEXT: or a0, a0, a2
230 ; CHECKIZFINX-NEXT: ret
231 ;
232 ; RV32I-LABEL: fcmp_one:
233 ; RV32I: # %bb.0:
234 ; RV32I-NEXT: addi sp, sp, -16
235 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
236 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
237 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
238 ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
239 ; RV32I-NEXT: mv s0, a1
240 ; RV32I-NEXT: mv s1, a0
241 ; RV32I-NEXT: call __eqsf2
242 ; RV32I-NEXT: snez s2, a0
243 ; RV32I-NEXT: mv a0, s1
244 ; RV32I-NEXT: mv a1, s0
245 ; RV32I-NEXT: call __unordsf2
246 ; RV32I-NEXT: seqz a0, a0
247 ; RV32I-NEXT: and a0, a0, s2
248 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
249 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
250 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
251 ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
252 ; RV32I-NEXT: addi sp, sp, 16
253 ; RV32I-NEXT: ret
254 ;
255 ; RV64I-LABEL: fcmp_one:
256 ; RV64I: # %bb.0:
257 ; RV64I-NEXT: addi sp, sp, -32
258 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
259 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
260 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
261 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
262 ; RV64I-NEXT: mv s0, a1
263 ; RV64I-NEXT: mv s1, a0
264 ; RV64I-NEXT: call __eqsf2
265 ; RV64I-NEXT: snez s2, a0
266 ; RV64I-NEXT: mv a0, s1
267 ; RV64I-NEXT: mv a1, s0
268 ; RV64I-NEXT: call __unordsf2
269 ; RV64I-NEXT: seqz a0, a0
270 ; RV64I-NEXT: and a0, a0, s2
271 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
272 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
273 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
274 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
275 ; RV64I-NEXT: addi sp, sp, 32
276 ; RV64I-NEXT: ret
277 %1 = fcmp one float %a, %b
278 %2 = zext i1 %1 to i32
279 ret i32 %2
280 }
282 define i32 @fcmp_ord(float %a, float %b) nounwind {
283 ; CHECKIF-LABEL: fcmp_ord:
284 ; CHECKIF: # %bb.0:
285 ; CHECKIF-NEXT: feq.s a0, fa1, fa1
286 ; CHECKIF-NEXT: feq.s a1, fa0, fa0
287 ; CHECKIF-NEXT: and a0, a1, a0
288 ; CHECKIF-NEXT: ret
289 ;
290 ; CHECKIZFINX-LABEL: fcmp_ord:
291 ; CHECKIZFINX: # %bb.0:
292 ; CHECKIZFINX-NEXT: feq.s a1, a1, a1
293 ; CHECKIZFINX-NEXT: feq.s a0, a0, a0
294 ; CHECKIZFINX-NEXT: and a0, a0, a1
295 ; CHECKIZFINX-NEXT: ret
296 ;
297 ; RV32I-LABEL: fcmp_ord:
298 ; RV32I: # %bb.0:
299 ; RV32I-NEXT: addi sp, sp, -16
300 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
301 ; RV32I-NEXT: call __unordsf2
302 ; RV32I-NEXT: seqz a0, a0
303 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
304 ; RV32I-NEXT: addi sp, sp, 16
305 ; RV32I-NEXT: ret
306 ;
307 ; RV64I-LABEL: fcmp_ord:
308 ; RV64I: # %bb.0:
309 ; RV64I-NEXT: addi sp, sp, -16
310 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
311 ; RV64I-NEXT: call __unordsf2
312 ; RV64I-NEXT: seqz a0, a0
313 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
314 ; RV64I-NEXT: addi sp, sp, 16
315 ; RV64I-NEXT: ret
316 %1 = fcmp ord float %a, %b
317 %2 = zext i1 %1 to i32
318 ret i32 %2
319 }
321 define i32 @fcmp_ueq(float %a, float %b) nounwind {
322 ; CHECKIF-LABEL: fcmp_ueq:
323 ; CHECKIF: # %bb.0:
324 ; CHECKIF-NEXT: flt.s a0, fa0, fa1
325 ; CHECKIF-NEXT: flt.s a1, fa1, fa0
326 ; CHECKIF-NEXT: or a0, a1, a0
327 ; CHECKIF-NEXT: xori a0, a0, 1
328 ; CHECKIF-NEXT: ret
329 ;
330 ; CHECKIZFINX-LABEL: fcmp_ueq:
331 ; CHECKIZFINX: # %bb.0:
332 ; CHECKIZFINX-NEXT: flt.s a2, a0, a1
333 ; CHECKIZFINX-NEXT: flt.s a0, a1, a0
334 ; CHECKIZFINX-NEXT: or a0, a0, a2
335 ; CHECKIZFINX-NEXT: xori a0, a0, 1
336 ; CHECKIZFINX-NEXT: ret
337 ;
338 ; RV32I-LABEL: fcmp_ueq:
339 ; RV32I: # %bb.0:
340 ; RV32I-NEXT: addi sp, sp, -16
341 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
342 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
343 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
344 ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
345 ; RV32I-NEXT: mv s0, a1
346 ; RV32I-NEXT: mv s1, a0
347 ; RV32I-NEXT: call __eqsf2
348 ; RV32I-NEXT: seqz s2, a0
349 ; RV32I-NEXT: mv a0, s1
350 ; RV32I-NEXT: mv a1, s0
351 ; RV32I-NEXT: call __unordsf2
352 ; RV32I-NEXT: snez a0, a0
353 ; RV32I-NEXT: or a0, a0, s2
354 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
355 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
356 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
357 ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
358 ; RV32I-NEXT: addi sp, sp, 16
359 ; RV32I-NEXT: ret
360 ;
361 ; RV64I-LABEL: fcmp_ueq:
362 ; RV64I: # %bb.0:
363 ; RV64I-NEXT: addi sp, sp, -32
364 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
365 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
366 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
367 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
368 ; RV64I-NEXT: mv s0, a1
369 ; RV64I-NEXT: mv s1, a0
370 ; RV64I-NEXT: call __eqsf2
371 ; RV64I-NEXT: seqz s2, a0
372 ; RV64I-NEXT: mv a0, s1
373 ; RV64I-NEXT: mv a1, s0
374 ; RV64I-NEXT: call __unordsf2
375 ; RV64I-NEXT: snez a0, a0
376 ; RV64I-NEXT: or a0, a0, s2
377 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
378 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
379 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
380 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
381 ; RV64I-NEXT: addi sp, sp, 32
382 ; RV64I-NEXT: ret
383 %1 = fcmp ueq float %a, %b
384 %2 = zext i1 %1 to i32
385 ret i32 %2
386 }
388 define i32 @fcmp_ugt(float %a, float %b) nounwind {
389 ; CHECKIF-LABEL: fcmp_ugt:
390 ; CHECKIF: # %bb.0:
391 ; CHECKIF-NEXT: fle.s a0, fa0, fa1
392 ; CHECKIF-NEXT: xori a0, a0, 1
393 ; CHECKIF-NEXT: ret
394 ;
395 ; CHECKIZFINX-LABEL: fcmp_ugt:
396 ; CHECKIZFINX: # %bb.0:
397 ; CHECKIZFINX-NEXT: fle.s a0, a0, a1
398 ; CHECKIZFINX-NEXT: xori a0, a0, 1
399 ; CHECKIZFINX-NEXT: ret
400 ;
401 ; RV32I-LABEL: fcmp_ugt:
402 ; RV32I: # %bb.0:
403 ; RV32I-NEXT: addi sp, sp, -16
404 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
405 ; RV32I-NEXT: call __lesf2
406 ; RV32I-NEXT: sgtz a0, a0
407 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
408 ; RV32I-NEXT: addi sp, sp, 16
409 ; RV32I-NEXT: ret
410 ;
411 ; RV64I-LABEL: fcmp_ugt:
412 ; RV64I: # %bb.0:
413 ; RV64I-NEXT: addi sp, sp, -16
414 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
415 ; RV64I-NEXT: call __lesf2
416 ; RV64I-NEXT: sgtz a0, a0
417 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
418 ; RV64I-NEXT: addi sp, sp, 16
419 ; RV64I-NEXT: ret
420 %1 = fcmp ugt float %a, %b
421 %2 = zext i1 %1 to i32
422 ret i32 %2
423 }
425 define i32 @fcmp_uge(float %a, float %b) nounwind {
426 ; CHECKIF-LABEL: fcmp_uge:
427 ; CHECKIF: # %bb.0:
428 ; CHECKIF-NEXT: flt.s a0, fa0, fa1
429 ; CHECKIF-NEXT: xori a0, a0, 1
430 ; CHECKIF-NEXT: ret
431 ;
432 ; CHECKIZFINX-LABEL: fcmp_uge:
433 ; CHECKIZFINX: # %bb.0:
434 ; CHECKIZFINX-NEXT: flt.s a0, a0, a1
435 ; CHECKIZFINX-NEXT: xori a0, a0, 1
436 ; CHECKIZFINX-NEXT: ret
437 ;
438 ; RV32I-LABEL: fcmp_uge:
439 ; RV32I: # %bb.0:
440 ; RV32I-NEXT: addi sp, sp, -16
441 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
442 ; RV32I-NEXT: call __ltsf2
443 ; RV32I-NEXT: slti a0, a0, 0
444 ; RV32I-NEXT: xori a0, a0, 1
445 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
446 ; RV32I-NEXT: addi sp, sp, 16
447 ; RV32I-NEXT: ret
448 ;
449 ; RV64I-LABEL: fcmp_uge:
450 ; RV64I: # %bb.0:
451 ; RV64I-NEXT: addi sp, sp, -16
452 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
453 ; RV64I-NEXT: call __ltsf2
454 ; RV64I-NEXT: slti a0, a0, 0
455 ; RV64I-NEXT: xori a0, a0, 1
456 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
457 ; RV64I-NEXT: addi sp, sp, 16
458 ; RV64I-NEXT: ret
459 %1 = fcmp uge float %a, %b
460 %2 = zext i1 %1 to i32
461 ret i32 %2
462 }
464 define i32 @fcmp_ult(float %a, float %b) nounwind {
465 ; CHECKIF-LABEL: fcmp_ult:
466 ; CHECKIF: # %bb.0:
467 ; CHECKIF-NEXT: fle.s a0, fa1, fa0
468 ; CHECKIF-NEXT: xori a0, a0, 1
469 ; CHECKIF-NEXT: ret
470 ;
471 ; CHECKIZFINX-LABEL: fcmp_ult:
472 ; CHECKIZFINX: # %bb.0:
473 ; CHECKIZFINX-NEXT: fle.s a0, a1, a0
474 ; CHECKIZFINX-NEXT: xori a0, a0, 1
475 ; CHECKIZFINX-NEXT: ret
476 ;
477 ; RV32I-LABEL: fcmp_ult:
478 ; RV32I: # %bb.0:
479 ; RV32I-NEXT: addi sp, sp, -16
480 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
481 ; RV32I-NEXT: call __gesf2
482 ; RV32I-NEXT: slti a0, a0, 0
483 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
484 ; RV32I-NEXT: addi sp, sp, 16
485 ; RV32I-NEXT: ret
486 ;
487 ; RV64I-LABEL: fcmp_ult:
488 ; RV64I: # %bb.0:
489 ; RV64I-NEXT: addi sp, sp, -16
490 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
491 ; RV64I-NEXT: call __gesf2
492 ; RV64I-NEXT: slti a0, a0, 0
493 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
494 ; RV64I-NEXT: addi sp, sp, 16
495 ; RV64I-NEXT: ret
496 %1 = fcmp ult float %a, %b
497 %2 = zext i1 %1 to i32
498 ret i32 %2
499 }
501 define i32 @fcmp_ule(float %a, float %b) nounwind {
502 ; CHECKIF-LABEL: fcmp_ule:
503 ; CHECKIF: # %bb.0:
504 ; CHECKIF-NEXT: flt.s a0, fa1, fa0
505 ; CHECKIF-NEXT: xori a0, a0, 1
506 ; CHECKIF-NEXT: ret
507 ;
508 ; CHECKIZFINX-LABEL: fcmp_ule:
509 ; CHECKIZFINX: # %bb.0:
510 ; CHECKIZFINX-NEXT: flt.s a0, a1, a0
511 ; CHECKIZFINX-NEXT: xori a0, a0, 1
512 ; CHECKIZFINX-NEXT: ret
513 ;
514 ; RV32I-LABEL: fcmp_ule:
515 ; RV32I: # %bb.0:
516 ; RV32I-NEXT: addi sp, sp, -16
517 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
518 ; RV32I-NEXT: call __gtsf2
519 ; RV32I-NEXT: slti a0, a0, 1
520 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
521 ; RV32I-NEXT: addi sp, sp, 16
522 ; RV32I-NEXT: ret
523 ;
524 ; RV64I-LABEL: fcmp_ule:
525 ; RV64I: # %bb.0:
526 ; RV64I-NEXT: addi sp, sp, -16
527 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
528 ; RV64I-NEXT: call __gtsf2
529 ; RV64I-NEXT: slti a0, a0, 1
530 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
531 ; RV64I-NEXT: addi sp, sp, 16
532 ; RV64I-NEXT: ret
533 %1 = fcmp ule float %a, %b
534 %2 = zext i1 %1 to i32
535 ret i32 %2
536 }
538 define i32 @fcmp_une(float %a, float %b) nounwind {
539 ; CHECKIF-LABEL: fcmp_une:
540 ; CHECKIF: # %bb.0:
541 ; CHECKIF-NEXT: feq.s a0, fa0, fa1
542 ; CHECKIF-NEXT: xori a0, a0, 1
543 ; CHECKIF-NEXT: ret
544 ;
545 ; CHECKIZFINX-LABEL: fcmp_une:
546 ; CHECKIZFINX: # %bb.0:
547 ; CHECKIZFINX-NEXT: feq.s a0, a0, a1
548 ; CHECKIZFINX-NEXT: xori a0, a0, 1
549 ; CHECKIZFINX-NEXT: ret
550 ;
551 ; RV32I-LABEL: fcmp_une:
552 ; RV32I: # %bb.0:
553 ; RV32I-NEXT: addi sp, sp, -16
554 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
555 ; RV32I-NEXT: call __nesf2
556 ; RV32I-NEXT: snez a0, a0
557 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
558 ; RV32I-NEXT: addi sp, sp, 16
559 ; RV32I-NEXT: ret
560 ;
561 ; RV64I-LABEL: fcmp_une:
562 ; RV64I: # %bb.0:
563 ; RV64I-NEXT: addi sp, sp, -16
564 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
565 ; RV64I-NEXT: call __nesf2
566 ; RV64I-NEXT: snez a0, a0
567 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
568 ; RV64I-NEXT: addi sp, sp, 16
569 ; RV64I-NEXT: ret
570 %1 = fcmp une float %a, %b
571 %2 = zext i1 %1 to i32
572 ret i32 %2
573 }
575 define i32 @fcmp_uno(float %a, float %b) nounwind {
576 ; CHECKIF-LABEL: fcmp_uno:
577 ; CHECKIF: # %bb.0:
578 ; CHECKIF-NEXT: feq.s a0, fa1, fa1
579 ; CHECKIF-NEXT: feq.s a1, fa0, fa0
580 ; CHECKIF-NEXT: and a0, a1, a0
581 ; CHECKIF-NEXT: xori a0, a0, 1
582 ; CHECKIF-NEXT: ret
583 ;
584 ; CHECKIZFINX-LABEL: fcmp_uno:
585 ; CHECKIZFINX: # %bb.0:
586 ; CHECKIZFINX-NEXT: feq.s a1, a1, a1
587 ; CHECKIZFINX-NEXT: feq.s a0, a0, a0
588 ; CHECKIZFINX-NEXT: and a0, a0, a1
589 ; CHECKIZFINX-NEXT: xori a0, a0, 1
590 ; CHECKIZFINX-NEXT: ret
591 ;
592 ; RV32I-LABEL: fcmp_uno:
593 ; RV32I: # %bb.0:
594 ; RV32I-NEXT: addi sp, sp, -16
595 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
596 ; RV32I-NEXT: call __unordsf2
597 ; RV32I-NEXT: snez a0, a0
598 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
599 ; RV32I-NEXT: addi sp, sp, 16
600 ; RV32I-NEXT: ret
601 ;
602 ; RV64I-LABEL: fcmp_uno:
603 ; RV64I: # %bb.0:
604 ; RV64I-NEXT: addi sp, sp, -16
605 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
606 ; RV64I-NEXT: call __unordsf2
607 ; RV64I-NEXT: snez a0, a0
608 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
609 ; RV64I-NEXT: addi sp, sp, 16
610 ; RV64I-NEXT: ret
611 %1 = fcmp uno float %a, %b
612 %2 = zext i1 %1 to i32
613 ret i32 %2
614 }
616 define i32 @fcmp_true(float %a, float %b) nounwind {
617 ; CHECKIF-LABEL: fcmp_true:
618 ; CHECKIF: # %bb.0:
619 ; CHECKIF-NEXT: li a0, 1
620 ; CHECKIF-NEXT: ret
621 ;
622 ; CHECKIZFINX-LABEL: fcmp_true:
623 ; CHECKIZFINX: # %bb.0:
624 ; CHECKIZFINX-NEXT: li a0, 1
625 ; CHECKIZFINX-NEXT: ret
626 ;
627 ; RV32I-LABEL: fcmp_true:
628 ; RV32I: # %bb.0:
629 ; RV32I-NEXT: li a0, 1
630 ; RV32I-NEXT: ret
631 ;
632 ; RV64I-LABEL: fcmp_true:
633 ; RV64I: # %bb.0:
634 ; RV64I-NEXT: li a0, 1
635 ; RV64I-NEXT: ret
636 %1 = fcmp true float %a, %b
637 %2 = zext i1 %1 to i32
638 ret i32 %2
639 }