| blob | 1045df1c3e76686d04580a0d120dcb52a2e9c162 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
3 ; RUN: -target-abi ilp32f < %s | FileCheck %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
5 ; RUN: -target-abi lp64f < %s | FileCheck %s
6 ; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
7 ; RUN: -target-abi ilp32 < %s \
8 ; RUN: | FileCheck -check-prefix=RV32IZHINX %s
9 ; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
10 ; RUN: -target-abi lp64 < %s \
11 ; RUN: | FileCheck -check-prefix=RV64IZHINX %s
12 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
13 ; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
14 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
15 ; RUN: -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
16 ; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
17 ; RUN: -target-abi ilp32 < %s \
18 ; RUN: | FileCheck -check-prefixes=CHECKIZHINXMIN,RV32IZHINXMIN %s
19 ; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
20 ; RUN: -target-abi lp64 < %s \
21 ; RUN: | FileCheck -check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN %s
23 ; TODO: constant pool shouldn't be necessary for RV32IZfh and RV64IZfh
24 define half @half_imm() nounwind {
25 ; CHECK-LABEL: half_imm:
26 ; CHECK: # %bb.0:
27 ; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
28 ; CHECK-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
29 ; CHECK-NEXT: ret
30 ;
31 ; RV32IZHINX-LABEL: half_imm:
32 ; RV32IZHINX: # %bb.0:
33 ; RV32IZHINX-NEXT: lui a0, 4
34 ; RV32IZHINX-NEXT: addi a0, a0, 512
35 ; RV32IZHINX-NEXT: # kill: def $x10_h killed $x10_h killed $x10
36 ; RV32IZHINX-NEXT: ret
37 ;
38 ; RV64IZHINX-LABEL: half_imm:
39 ; RV64IZHINX: # %bb.0:
40 ; RV64IZHINX-NEXT: lui a0, 4
41 ; RV64IZHINX-NEXT: addiw a0, a0, 512
42 ; RV64IZHINX-NEXT: # kill: def $x10_h killed $x10_h killed $x10
43 ; RV64IZHINX-NEXT: ret
44 ;
45 ; CHECKIZFHMIN-LABEL: half_imm:
46 ; CHECKIZFHMIN: # %bb.0:
47 ; CHECKIZFHMIN-NEXT: lui a0, %hi(.LCPI0_0)
48 ; CHECKIZFHMIN-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
49 ; CHECKIZFHMIN-NEXT: ret
50 ;
51 ; RV32IZHINXMIN-LABEL: half_imm:
52 ; RV32IZHINXMIN: # %bb.0:
53 ; RV32IZHINXMIN-NEXT: lui a0, 4
54 ; RV32IZHINXMIN-NEXT: addi a0, a0, 512
55 ; RV32IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10
56 ; RV32IZHINXMIN-NEXT: ret
57 ;
58 ; RV64IZHINXMIN-LABEL: half_imm:
59 ; RV64IZHINXMIN: # %bb.0:
60 ; RV64IZHINXMIN-NEXT: lui a0, 4
61 ; RV64IZHINXMIN-NEXT: addiw a0, a0, 512
62 ; RV64IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10
63 ; RV64IZHINXMIN-NEXT: ret
64 ret half 3.0
65 }
67 define half @half_imm_op(half %a) nounwind {
68 ; CHECK-LABEL: half_imm_op:
69 ; CHECK: # %bb.0:
70 ; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
71 ; CHECK-NEXT: flh fa5, %lo(.LCPI1_0)(a0)
72 ; CHECK-NEXT: fadd.h fa0, fa0, fa5
73 ; CHECK-NEXT: ret
74 ;
75 ; RV32IZHINX-LABEL: half_imm_op:
76 ; RV32IZHINX: # %bb.0:
77 ; RV32IZHINX-NEXT: li a1, 15
78 ; RV32IZHINX-NEXT: slli a1, a1, 10
79 ; RV32IZHINX-NEXT: fadd.h a0, a0, a1
80 ; RV32IZHINX-NEXT: ret
81 ;
82 ; RV64IZHINX-LABEL: half_imm_op:
83 ; RV64IZHINX: # %bb.0:
84 ; RV64IZHINX-NEXT: li a1, 15
85 ; RV64IZHINX-NEXT: slli a1, a1, 10
86 ; RV64IZHINX-NEXT: fadd.h a0, a0, a1
87 ; RV64IZHINX-NEXT: ret
88 ;
89 ; CHECKIZFHMIN-LABEL: half_imm_op:
90 ; CHECKIZFHMIN: # %bb.0:
91 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
92 ; CHECKIZFHMIN-NEXT: lui a0, 260096
93 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
94 ; CHECKIZFHMIN-NEXT: fadd.s fa5, fa5, fa4
95 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
96 ; CHECKIZFHMIN-NEXT: ret
97 ;
98 ; CHECKIZHINXMIN-LABEL: half_imm_op:
99 ; CHECKIZHINXMIN: # %bb.0:
100 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
101 ; CHECKIZHINXMIN-NEXT: lui a1, 260096
102 ; CHECKIZHINXMIN-NEXT: fadd.s a0, a0, a1
103 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
104 ; CHECKIZHINXMIN-NEXT: ret
105 %1 = fadd half %a, 1.0
106 ret half %1
107 }
109 define half @half_positive_zero(ptr %pf) nounwind {
110 ; CHECK-LABEL: half_positive_zero:
111 ; CHECK: # %bb.0:
112 ; CHECK-NEXT: fmv.h.x fa0, zero
113 ; CHECK-NEXT: ret
114 ;
115 ; RV32IZHINX-LABEL: half_positive_zero:
116 ; RV32IZHINX: # %bb.0:
117 ; RV32IZHINX-NEXT: li a0, 0
118 ; RV32IZHINX-NEXT: ret
119 ;
120 ; RV64IZHINX-LABEL: half_positive_zero:
121 ; RV64IZHINX: # %bb.0:
122 ; RV64IZHINX-NEXT: li a0, 0
123 ; RV64IZHINX-NEXT: ret
124 ;
125 ; CHECKIZFHMIN-LABEL: half_positive_zero:
126 ; CHECKIZFHMIN: # %bb.0:
127 ; CHECKIZFHMIN-NEXT: fmv.h.x fa0, zero
128 ; CHECKIZFHMIN-NEXT: ret
129 ;
130 ; CHECKIZHINXMIN-LABEL: half_positive_zero:
131 ; CHECKIZHINXMIN: # %bb.0:
132 ; CHECKIZHINXMIN-NEXT: li a0, 0
133 ; CHECKIZHINXMIN-NEXT: ret
134 ret half 0.0
135 }
137 define half @half_negative_zero(ptr %pf) nounwind {
138 ; CHECK-LABEL: half_negative_zero:
139 ; CHECK: # %bb.0:
140 ; CHECK-NEXT: lui a0, 1048568
141 ; CHECK-NEXT: fmv.h.x fa0, a0
142 ; CHECK-NEXT: ret
143 ;
144 ; RV32IZHINX-LABEL: half_negative_zero:
145 ; RV32IZHINX: # %bb.0:
146 ; RV32IZHINX-NEXT: lui a0, 1048568
147 ; RV32IZHINX-NEXT: ret
148 ;
149 ; RV64IZHINX-LABEL: half_negative_zero:
150 ; RV64IZHINX: # %bb.0:
151 ; RV64IZHINX-NEXT: lui a0, 1048568
152 ; RV64IZHINX-NEXT: ret
153 ;
154 ; CHECKIZFHMIN-LABEL: half_negative_zero:
155 ; CHECKIZFHMIN: # %bb.0:
156 ; CHECKIZFHMIN-NEXT: lui a0, 1048568
157 ; CHECKIZFHMIN-NEXT: fmv.h.x fa0, a0
158 ; CHECKIZFHMIN-NEXT: ret
159 ;
160 ; CHECKIZHINXMIN-LABEL: half_negative_zero:
161 ; CHECKIZHINXMIN: # %bb.0:
162 ; CHECKIZHINXMIN-NEXT: lui a0, 1048568
163 ; CHECKIZHINXMIN-NEXT: ret
164 ret half -0.0
165 }