| blob | de7b0a78208a3e9116e8de1db09086e225eef6db |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=zfh -verify-machineinstrs < %s \
3 ; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32ZFH %s
4 ; RUN: llc -mtriple=riscv64 -mattr=zfh -verify-machineinstrs < %s \
5 ; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64ZFH %s
6 ; RUN: llc -mtriple=riscv32 -mattr=zfh,+d -verify-machineinstrs < %s \
7 ; RUN: -target-abi=ilp32d | FileCheck -check-prefix=RV32DZFH %s
8 ; RUN: llc -mtriple=riscv64 -mattr=zfh,+d -verify-machineinstrs < %s \
9 ; RUN: -target-abi=lp64d | FileCheck -check-prefix=RV64DZFH %s
11 @gh = external global half
13 define half @constraint_f_half(half %a) nounwind {
14 ; RV32ZFH-LABEL: constraint_f_half:
15 ; RV32ZFH: # %bb.0:
16 ; RV32ZFH-NEXT: lui a0, %hi(gh)
17 ; RV32ZFH-NEXT: flh fa5, %lo(gh)(a0)
18 ; RV32ZFH-NEXT: #APP
19 ; RV32ZFH-NEXT: fadd.h fa0, fa0, fa5
20 ; RV32ZFH-NEXT: #NO_APP
21 ; RV32ZFH-NEXT: ret
22 ;
23 ; RV64ZFH-LABEL: constraint_f_half:
24 ; RV64ZFH: # %bb.0:
25 ; RV64ZFH-NEXT: lui a0, %hi(gh)
26 ; RV64ZFH-NEXT: flh fa5, %lo(gh)(a0)
27 ; RV64ZFH-NEXT: #APP
28 ; RV64ZFH-NEXT: fadd.h fa0, fa0, fa5
29 ; RV64ZFH-NEXT: #NO_APP
30 ; RV64ZFH-NEXT: ret
31 ;
32 ; RV32DZFH-LABEL: constraint_f_half:
33 ; RV32DZFH: # %bb.0:
34 ; RV32DZFH-NEXT: lui a0, %hi(gh)
35 ; RV32DZFH-NEXT: flh fa5, %lo(gh)(a0)
36 ; RV32DZFH-NEXT: #APP
37 ; RV32DZFH-NEXT: fadd.h fa0, fa0, fa5
38 ; RV32DZFH-NEXT: #NO_APP
39 ; RV32DZFH-NEXT: ret
40 ;
41 ; RV64DZFH-LABEL: constraint_f_half:
42 ; RV64DZFH: # %bb.0:
43 ; RV64DZFH-NEXT: lui a0, %hi(gh)
44 ; RV64DZFH-NEXT: flh fa5, %lo(gh)(a0)
45 ; RV64DZFH-NEXT: #APP
46 ; RV64DZFH-NEXT: fadd.h fa0, fa0, fa5
47 ; RV64DZFH-NEXT: #NO_APP
48 ; RV64DZFH-NEXT: ret
49 %1 = load half, ptr @gh
50 %2 = tail call half asm "fadd.h $0, $1, $2", "=f,f,f"(half %a, half %1)
51 ret half %2
52 }
54 define half @constraint_cf_half(half %a) nounwind {
55 ; RV32ZFH-LABEL: constraint_cf_half:
56 ; RV32ZFH: # %bb.0:
57 ; RV32ZFH-NEXT: lui a0, %hi(gh)
58 ; RV32ZFH-NEXT: flh fa5, %lo(gh)(a0)
59 ; RV32ZFH-NEXT: #APP
60 ; RV32ZFH-NEXT: fadd.h fa0, fa0, fa5
61 ; RV32ZFH-NEXT: #NO_APP
62 ; RV32ZFH-NEXT: ret
63 ;
64 ; RV64ZFH-LABEL: constraint_cf_half:
65 ; RV64ZFH: # %bb.0:
66 ; RV64ZFH-NEXT: lui a0, %hi(gh)
67 ; RV64ZFH-NEXT: flh fa5, %lo(gh)(a0)
68 ; RV64ZFH-NEXT: #APP
69 ; RV64ZFH-NEXT: fadd.h fa0, fa0, fa5
70 ; RV64ZFH-NEXT: #NO_APP
71 ; RV64ZFH-NEXT: ret
72 ;
73 ; RV32DZFH-LABEL: constraint_cf_half:
74 ; RV32DZFH: # %bb.0:
75 ; RV32DZFH-NEXT: lui a0, %hi(gh)
76 ; RV32DZFH-NEXT: flh fa5, %lo(gh)(a0)
77 ; RV32DZFH-NEXT: #APP
78 ; RV32DZFH-NEXT: fadd.h fa0, fa0, fa5
79 ; RV32DZFH-NEXT: #NO_APP
80 ; RV32DZFH-NEXT: ret
81 ;
82 ; RV64DZFH-LABEL: constraint_cf_half:
83 ; RV64DZFH: # %bb.0:
84 ; RV64DZFH-NEXT: lui a0, %hi(gh)
85 ; RV64DZFH-NEXT: flh fa5, %lo(gh)(a0)
86 ; RV64DZFH-NEXT: #APP
87 ; RV64DZFH-NEXT: fadd.h fa0, fa0, fa5
88 ; RV64DZFH-NEXT: #NO_APP
89 ; RV64DZFH-NEXT: ret
90 %1 = load half, ptr @gh
91 %2 = tail call half asm "fadd.h $0, $1, $2", "=^cf,^cf,^cf"(half %a, half %1)
92 ret half %2
93 }
95 define half @constraint_f_half_abi_name(half %a) nounwind {
96 ; RV32ZFH-LABEL: constraint_f_half_abi_name:
97 ; RV32ZFH: # %bb.0:
98 ; RV32ZFH-NEXT: addi sp, sp, -16
99 ; RV32ZFH-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill
100 ; RV32ZFH-NEXT: lui a0, %hi(gh)
101 ; RV32ZFH-NEXT: flh fs0, %lo(gh)(a0)
102 ; RV32ZFH-NEXT: #APP
103 ; RV32ZFH-NEXT: fadd.s ft0, fa0, fs0
104 ; RV32ZFH-NEXT: #NO_APP
105 ; RV32ZFH-NEXT: fmv.h fa0, ft0
106 ; RV32ZFH-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
107 ; RV32ZFH-NEXT: addi sp, sp, 16
108 ; RV32ZFH-NEXT: ret
109 ;
110 ; RV64ZFH-LABEL: constraint_f_half_abi_name:
111 ; RV64ZFH: # %bb.0:
112 ; RV64ZFH-NEXT: addi sp, sp, -16
113 ; RV64ZFH-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill
114 ; RV64ZFH-NEXT: lui a0, %hi(gh)
115 ; RV64ZFH-NEXT: flh fs0, %lo(gh)(a0)
116 ; RV64ZFH-NEXT: #APP
117 ; RV64ZFH-NEXT: fadd.s ft0, fa0, fs0
118 ; RV64ZFH-NEXT: #NO_APP
119 ; RV64ZFH-NEXT: fmv.h fa0, ft0
120 ; RV64ZFH-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
121 ; RV64ZFH-NEXT: addi sp, sp, 16
122 ; RV64ZFH-NEXT: ret
123 ;
124 ; RV32DZFH-LABEL: constraint_f_half_abi_name:
125 ; RV32DZFH: # %bb.0:
126 ; RV32DZFH-NEXT: addi sp, sp, -16
127 ; RV32DZFH-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill
128 ; RV32DZFH-NEXT: lui a0, %hi(gh)
129 ; RV32DZFH-NEXT: flh fs0, %lo(gh)(a0)
130 ; RV32DZFH-NEXT: #APP
131 ; RV32DZFH-NEXT: fadd.s ft0, fa0, fs0
132 ; RV32DZFH-NEXT: #NO_APP
133 ; RV32DZFH-NEXT: fmv.h fa0, ft0
134 ; RV32DZFH-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload
135 ; RV32DZFH-NEXT: addi sp, sp, 16
136 ; RV32DZFH-NEXT: ret
137 ;
138 ; RV64DZFH-LABEL: constraint_f_half_abi_name:
139 ; RV64DZFH: # %bb.0:
140 ; RV64DZFH-NEXT: addi sp, sp, -16
141 ; RV64DZFH-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill
142 ; RV64DZFH-NEXT: lui a0, %hi(gh)
143 ; RV64DZFH-NEXT: flh fs0, %lo(gh)(a0)
144 ; RV64DZFH-NEXT: #APP
145 ; RV64DZFH-NEXT: fadd.s ft0, fa0, fs0
146 ; RV64DZFH-NEXT: #NO_APP
147 ; RV64DZFH-NEXT: fmv.h fa0, ft0
148 ; RV64DZFH-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload
149 ; RV64DZFH-NEXT: addi sp, sp, 16
150 ; RV64DZFH-NEXT: ret
151 %1 = load half, ptr @gh
152 %2 = tail call half asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(half %a, half %1)
153 ret half %2
154 }
156 define half @constraint_gpr(half %x) {
157 ; RV32ZFH-LABEL: constraint_gpr:
158 ; RV32ZFH: # %bb.0:
159 ; RV32ZFH-NEXT: fmv.x.h a0, fa0
160 ; RV32ZFH-NEXT: #APP
161 ; RV32ZFH-NEXT: mv a0, a0
162 ; RV32ZFH-NEXT: #NO_APP
163 ; RV32ZFH-NEXT: fmv.h.x fa0, a0
164 ; RV32ZFH-NEXT: ret
165 ;
166 ; RV64ZFH-LABEL: constraint_gpr:
167 ; RV64ZFH: # %bb.0:
168 ; RV64ZFH-NEXT: fmv.x.h a0, fa0
169 ; RV64ZFH-NEXT: #APP
170 ; RV64ZFH-NEXT: mv a0, a0
171 ; RV64ZFH-NEXT: #NO_APP
172 ; RV64ZFH-NEXT: fmv.h.x fa0, a0
173 ; RV64ZFH-NEXT: ret
174 ;
175 ; RV32DZFH-LABEL: constraint_gpr:
176 ; RV32DZFH: # %bb.0:
177 ; RV32DZFH-NEXT: fmv.x.h a0, fa0
178 ; RV32DZFH-NEXT: #APP
179 ; RV32DZFH-NEXT: mv a0, a0
180 ; RV32DZFH-NEXT: #NO_APP
181 ; RV32DZFH-NEXT: fmv.h.x fa0, a0
182 ; RV32DZFH-NEXT: ret
183 ;
184 ; RV64DZFH-LABEL: constraint_gpr:
185 ; RV64DZFH: # %bb.0:
186 ; RV64DZFH-NEXT: fmv.x.h a0, fa0
187 ; RV64DZFH-NEXT: #APP
188 ; RV64DZFH-NEXT: mv a0, a0
189 ; RV64DZFH-NEXT: #NO_APP
190 ; RV64DZFH-NEXT: fmv.h.x fa0, a0
191 ; RV64DZFH-NEXT: ret
192 %1 = tail call half asm sideeffect alignstack "mv $0, $1", "={x10},{x10}"(half %x)
193 ret half %1
194 }