| blob | 086d2a1d6f3b2f61f5ccd2b93ebb4e04dc590708 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2 ; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs < %s \
3 ; RUN: -target-abi=ilp32 | FileCheck -check-prefix=RV32ZHINX %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs < %s \
5 ; RUN: -target-abi=lp64 | FileCheck -check-prefix=RV64ZHINX %s
6 ; RUN: llc -mtriple=riscv32 -mattr=+zdinx,+zhinx -verify-machineinstrs < %s \
7 ; RUN: -target-abi=ilp32 | FileCheck -check-prefix=RV32DINXZHINX %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+zdinx,+zhinx -verify-machineinstrs < %s \
9 ; RUN: -target-abi=lp64 | FileCheck -check-prefix=RV64DINXZHINX %s
11 @gh = external global half
13 define half @constraint_r_half(half %a) nounwind {
14 ; RV32ZHINX-LABEL: constraint_r_half:
15 ; RV32ZHINX: # %bb.0:
16 ; RV32ZHINX-NEXT: lui a1, %hi(gh)
17 ; RV32ZHINX-NEXT: lh a1, %lo(gh)(a1)
18 ; RV32ZHINX-NEXT: #APP
19 ; RV32ZHINX-NEXT: fadd.h a0, a0, a1
20 ; RV32ZHINX-NEXT: #NO_APP
21 ; RV32ZHINX-NEXT: ret
22 ;
23 ; RV64ZHINX-LABEL: constraint_r_half:
24 ; RV64ZHINX: # %bb.0:
25 ; RV64ZHINX-NEXT: lui a1, %hi(gh)
26 ; RV64ZHINX-NEXT: lh a1, %lo(gh)(a1)
27 ; RV64ZHINX-NEXT: #APP
28 ; RV64ZHINX-NEXT: fadd.h a0, a0, a1
29 ; RV64ZHINX-NEXT: #NO_APP
30 ; RV64ZHINX-NEXT: ret
31 ;
32 ; RV32DINXZHINX-LABEL: constraint_r_half:
33 ; RV32DINXZHINX: # %bb.0:
34 ; RV32DINXZHINX-NEXT: lui a1, %hi(gh)
35 ; RV32DINXZHINX-NEXT: lh a1, %lo(gh)(a1)
36 ; RV32DINXZHINX-NEXT: #APP
37 ; RV32DINXZHINX-NEXT: fadd.h a0, a0, a1
38 ; RV32DINXZHINX-NEXT: #NO_APP
39 ; RV32DINXZHINX-NEXT: ret
40 ;
41 ; RV64DINXZHINX-LABEL: constraint_r_half:
42 ; RV64DINXZHINX: # %bb.0:
43 ; RV64DINXZHINX-NEXT: lui a1, %hi(gh)
44 ; RV64DINXZHINX-NEXT: lh a1, %lo(gh)(a1)
45 ; RV64DINXZHINX-NEXT: #APP
46 ; RV64DINXZHINX-NEXT: fadd.h a0, a0, a1
47 ; RV64DINXZHINX-NEXT: #NO_APP
48 ; RV64DINXZHINX-NEXT: ret
49 %1 = load half, ptr @gh
50 %2 = tail call half asm "fadd.h $0, $1, $2", "=r,r,r"(half %a, half %1)
51 ret half %2
52 }
54 define half @constraint_cr_half(half %a) nounwind {
55 ; RV32ZHINX-LABEL: constraint_cr_half:
56 ; RV32ZHINX: # %bb.0:
57 ; RV32ZHINX-NEXT: lui a1, %hi(gh)
58 ; RV32ZHINX-NEXT: lh a1, %lo(gh)(a1)
59 ; RV32ZHINX-NEXT: #APP
60 ; RV32ZHINX-NEXT: fadd.h a0, a0, a1
61 ; RV32ZHINX-NEXT: #NO_APP
62 ; RV32ZHINX-NEXT: ret
63 ;
64 ; RV64ZHINX-LABEL: constraint_cr_half:
65 ; RV64ZHINX: # %bb.0:
66 ; RV64ZHINX-NEXT: lui a1, %hi(gh)
67 ; RV64ZHINX-NEXT: lh a1, %lo(gh)(a1)
68 ; RV64ZHINX-NEXT: #APP
69 ; RV64ZHINX-NEXT: fadd.h a0, a0, a1
70 ; RV64ZHINX-NEXT: #NO_APP
71 ; RV64ZHINX-NEXT: ret
72 ;
73 ; RV32DINXZHINX-LABEL: constraint_cr_half:
74 ; RV32DINXZHINX: # %bb.0:
75 ; RV32DINXZHINX-NEXT: lui a1, %hi(gh)
76 ; RV32DINXZHINX-NEXT: lh a1, %lo(gh)(a1)
77 ; RV32DINXZHINX-NEXT: #APP
78 ; RV32DINXZHINX-NEXT: fadd.h a0, a0, a1
79 ; RV32DINXZHINX-NEXT: #NO_APP
80 ; RV32DINXZHINX-NEXT: ret
81 ;
82 ; RV64DINXZHINX-LABEL: constraint_cr_half:
83 ; RV64DINXZHINX: # %bb.0:
84 ; RV64DINXZHINX-NEXT: lui a1, %hi(gh)
85 ; RV64DINXZHINX-NEXT: lh a1, %lo(gh)(a1)
86 ; RV64DINXZHINX-NEXT: #APP
87 ; RV64DINXZHINX-NEXT: fadd.h a0, a0, a1
88 ; RV64DINXZHINX-NEXT: #NO_APP
89 ; RV64DINXZHINX-NEXT: ret
90 %1 = load half, ptr @gh
91 %2 = tail call half asm "fadd.h $0, $1, $2", "=^cr,^cr,^cr"(half %a, half %1)
92 ret half %2
93 }
95 define half @constraint_half_abi_name(half %a) nounwind {
96 ; RV32ZHINX-LABEL: constraint_half_abi_name:
97 ; RV32ZHINX: # %bb.0:
98 ; RV32ZHINX-NEXT: addi sp, sp, -16
99 ; RV32ZHINX-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
100 ; RV32ZHINX-NEXT: lui a1, %hi(gh)
101 ; RV32ZHINX-NEXT: lh s0, %lo(gh)(a1)
102 ; RV32ZHINX-NEXT: # kill: def $x10_h killed $x10_h def $x10
103 ; RV32ZHINX-NEXT: #APP
104 ; RV32ZHINX-NEXT: fadd.s t0, a0, s0
105 ; RV32ZHINX-NEXT: #NO_APP
106 ; RV32ZHINX-NEXT: mv a0, t0
107 ; RV32ZHINX-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
108 ; RV32ZHINX-NEXT: addi sp, sp, 16
109 ; RV32ZHINX-NEXT: ret
110 ;
111 ; RV64ZHINX-LABEL: constraint_half_abi_name:
112 ; RV64ZHINX: # %bb.0:
113 ; RV64ZHINX-NEXT: addi sp, sp, -16
114 ; RV64ZHINX-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
115 ; RV64ZHINX-NEXT: lui a1, %hi(gh)
116 ; RV64ZHINX-NEXT: lh s0, %lo(gh)(a1)
117 ; RV64ZHINX-NEXT: # kill: def $x10_h killed $x10_h def $x10
118 ; RV64ZHINX-NEXT: #APP
119 ; RV64ZHINX-NEXT: fadd.s t0, a0, s0
120 ; RV64ZHINX-NEXT: #NO_APP
121 ; RV64ZHINX-NEXT: mv a0, t0
122 ; RV64ZHINX-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
123 ; RV64ZHINX-NEXT: addi sp, sp, 16
124 ; RV64ZHINX-NEXT: ret
125 ;
126 ; RV32DINXZHINX-LABEL: constraint_half_abi_name:
127 ; RV32DINXZHINX: # %bb.0:
128 ; RV32DINXZHINX-NEXT: addi sp, sp, -16
129 ; RV32DINXZHINX-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
130 ; RV32DINXZHINX-NEXT: lui a1, %hi(gh)
131 ; RV32DINXZHINX-NEXT: lh s0, %lo(gh)(a1)
132 ; RV32DINXZHINX-NEXT: # kill: def $x10_h killed $x10_h def $x10
133 ; RV32DINXZHINX-NEXT: #APP
134 ; RV32DINXZHINX-NEXT: fadd.s t0, a0, s0
135 ; RV32DINXZHINX-NEXT: #NO_APP
136 ; RV32DINXZHINX-NEXT: mv a0, t0
137 ; RV32DINXZHINX-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
138 ; RV32DINXZHINX-NEXT: addi sp, sp, 16
139 ; RV32DINXZHINX-NEXT: ret
140 ;
141 ; RV64DINXZHINX-LABEL: constraint_half_abi_name:
142 ; RV64DINXZHINX: # %bb.0:
143 ; RV64DINXZHINX-NEXT: addi sp, sp, -16
144 ; RV64DINXZHINX-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
145 ; RV64DINXZHINX-NEXT: lui a1, %hi(gh)
146 ; RV64DINXZHINX-NEXT: lh s0, %lo(gh)(a1)
147 ; RV64DINXZHINX-NEXT: # kill: def $x10_h killed $x10_h def $x10
148 ; RV64DINXZHINX-NEXT: #APP
149 ; RV64DINXZHINX-NEXT: fadd.s t0, a0, s0
150 ; RV64DINXZHINX-NEXT: #NO_APP
151 ; RV64DINXZHINX-NEXT: mv a0, t0
152 ; RV64DINXZHINX-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
153 ; RV64DINXZHINX-NEXT: addi sp, sp, 16
154 ; RV64DINXZHINX-NEXT: ret
155 %1 = load half, ptr @gh
156 %2 = tail call half asm "fadd.s $0, $1, $2", "={t0},{a0},{s0}"(half %a, half %1)
157 ret half %2
158 }
160 define half @constraint_f_half(half %a) nounwind {
161 ; RV32ZHINX-LABEL: constraint_f_half:
162 ; RV32ZHINX: # %bb.0:
163 ; RV32ZHINX-NEXT: lui a1, %hi(gh)
164 ; RV32ZHINX-NEXT: lh a1, %lo(gh)(a1)
165 ; RV32ZHINX-NEXT: #APP
166 ; RV32ZHINX-NEXT: fadd.h a0, a0, a1
167 ; RV32ZHINX-NEXT: #NO_APP
168 ; RV32ZHINX-NEXT: ret
169 ;
170 ; RV64ZHINX-LABEL: constraint_f_half:
171 ; RV64ZHINX: # %bb.0:
172 ; RV64ZHINX-NEXT: lui a1, %hi(gh)
173 ; RV64ZHINX-NEXT: lh a1, %lo(gh)(a1)
174 ; RV64ZHINX-NEXT: #APP
175 ; RV64ZHINX-NEXT: fadd.h a0, a0, a1
176 ; RV64ZHINX-NEXT: #NO_APP
177 ; RV64ZHINX-NEXT: ret
178 ;
179 ; RV32DINXZHINX-LABEL: constraint_f_half:
180 ; RV32DINXZHINX: # %bb.0:
181 ; RV32DINXZHINX-NEXT: lui a1, %hi(gh)
182 ; RV32DINXZHINX-NEXT: lh a1, %lo(gh)(a1)
183 ; RV32DINXZHINX-NEXT: #APP
184 ; RV32DINXZHINX-NEXT: fadd.h a0, a0, a1
185 ; RV32DINXZHINX-NEXT: #NO_APP
186 ; RV32DINXZHINX-NEXT: ret
187 ;
188 ; RV64DINXZHINX-LABEL: constraint_f_half:
189 ; RV64DINXZHINX: # %bb.0:
190 ; RV64DINXZHINX-NEXT: lui a1, %hi(gh)
191 ; RV64DINXZHINX-NEXT: lh a1, %lo(gh)(a1)
192 ; RV64DINXZHINX-NEXT: #APP
193 ; RV64DINXZHINX-NEXT: fadd.h a0, a0, a1
194 ; RV64DINXZHINX-NEXT: #NO_APP
195 ; RV64DINXZHINX-NEXT: ret
196 %1 = load half, ptr @gh
197 %2 = tail call half asm "fadd.h $0, $1, $2", "=f,f,f"(half %a, half %1)
198 ret half %2
199 }
201 define half @constraint_cf_half(half %a) nounwind {
202 ; RV32ZHINX-LABEL: constraint_cf_half:
203 ; RV32ZHINX: # %bb.0:
204 ; RV32ZHINX-NEXT: lui a1, %hi(gh)
205 ; RV32ZHINX-NEXT: lh a1, %lo(gh)(a1)
206 ; RV32ZHINX-NEXT: #APP
207 ; RV32ZHINX-NEXT: fadd.h a0, a0, a1
208 ; RV32ZHINX-NEXT: #NO_APP
209 ; RV32ZHINX-NEXT: ret
210 ;
211 ; RV64ZHINX-LABEL: constraint_cf_half:
212 ; RV64ZHINX: # %bb.0:
213 ; RV64ZHINX-NEXT: lui a1, %hi(gh)
214 ; RV64ZHINX-NEXT: lh a1, %lo(gh)(a1)
215 ; RV64ZHINX-NEXT: #APP
216 ; RV64ZHINX-NEXT: fadd.h a0, a0, a1
217 ; RV64ZHINX-NEXT: #NO_APP
218 ; RV64ZHINX-NEXT: ret
219 ;
220 ; RV32DINXZHINX-LABEL: constraint_cf_half:
221 ; RV32DINXZHINX: # %bb.0:
222 ; RV32DINXZHINX-NEXT: lui a1, %hi(gh)
223 ; RV32DINXZHINX-NEXT: lh a1, %lo(gh)(a1)
224 ; RV32DINXZHINX-NEXT: #APP
225 ; RV32DINXZHINX-NEXT: fadd.h a0, a0, a1
226 ; RV32DINXZHINX-NEXT: #NO_APP
227 ; RV32DINXZHINX-NEXT: ret
228 ;
229 ; RV64DINXZHINX-LABEL: constraint_cf_half:
230 ; RV64DINXZHINX: # %bb.0:
231 ; RV64DINXZHINX-NEXT: lui a1, %hi(gh)
232 ; RV64DINXZHINX-NEXT: lh a1, %lo(gh)(a1)
233 ; RV64DINXZHINX-NEXT: #APP
234 ; RV64DINXZHINX-NEXT: fadd.h a0, a0, a1
235 ; RV64DINXZHINX-NEXT: #NO_APP
236 ; RV64DINXZHINX-NEXT: ret
237 %1 = load half, ptr @gh
238 %2 = tail call half asm "fadd.h $0, $1, $2", "=^cf,^cf,^cf"(half %a, half %1)
239 ret half %2
240 }