1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2 ; RUN: llc -mtriple=riscv32 -mattr=+v < %s | FileCheck %s -check-prefix=RV32
3 ; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s -check-prefix=RV64
7 define i16 @ctz_v4i32(<4 x i32> %a) {
8 ; RV32-LABEL: ctz_v4i32:
10 ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
11 ; RV32-NEXT: vmsne.vi v0, v8, 0
12 ; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
13 ; RV32-NEXT: vmv.v.i v8, 0
14 ; RV32-NEXT: vmerge.vim v8, v8, -1, v0
16 ; RV32-NEXT: vrsub.vi v9, v9, 4
17 ; RV32-NEXT: vand.vv v8, v8, v9
18 ; RV32-NEXT: vredmaxu.vs v8, v8, v8
19 ; RV32-NEXT: vmv.x.s a0, v8
21 ; RV32-NEXT: sub a1, a1, a0
22 ; RV32-NEXT: andi a0, a1, 255
25 ; RV64-LABEL: ctz_v4i32:
27 ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
28 ; RV64-NEXT: vmsne.vi v0, v8, 0
29 ; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
30 ; RV64-NEXT: vmv.v.i v8, 0
31 ; RV64-NEXT: vmerge.vim v8, v8, -1, v0
33 ; RV64-NEXT: vrsub.vi v9, v9, 4
34 ; RV64-NEXT: vand.vv v8, v8, v9
35 ; RV64-NEXT: vredmaxu.vs v8, v8, v8
36 ; RV64-NEXT: vmv.x.s a0, v8
38 ; RV64-NEXT: subw a1, a1, a0
39 ; RV64-NEXT: andi a0, a1, 255
41 %res = call i16 @llvm.experimental.cttz.elts.i16.v4i32(<4 x i32> %a, i1 0)
47 define i32 @ctz_v2i1_poison(<2 x i1> %a) {
48 ; RV32-LABEL: ctz_v2i1_poison:
50 ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
51 ; RV32-NEXT: vfirst.m a0, v0
54 ; RV64-LABEL: ctz_v2i1_poison:
56 ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
57 ; RV64-NEXT: vfirst.m a0, v0
59 %res = call i32 @llvm.experimental.cttz.elts.i32.v2i1(<2 x i1> %a, i1 1)
63 declare i32 @llvm.experimental.cttz.elts.i32.v2i1(<2 x i1>, i1)
64 declare i16 @llvm.experimental.cttz.elts.i16.v4i32(<4 x i32>, i1)